arch/arm/mach-omap2/clock3xxx_data.c

   1 /*
   2  * OMAP3 clock data
   3  *
   4  * Copyright (C) 2007-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2011 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/clk.h>
  21 #include <linux/list.h>
  22
  23 #include <plat/clkdev_omap.h>
  24
  25 #include "clock.h"
  26 #include "clock3xxx.h"
  27 #include "clock34xx.h"
  28 #include "clock36xx.h"
  29 #include "clock3517.h"
  30
  31 #include "cm2xxx_3xxx.h"
  32 #include "cm-regbits-34xx.h"
  33 #include "prm2xxx_3xxx.h"
  34 #include "prm-regbits-34xx.h"
  35 #include "control.h"
  36
  37 /*
  38  * clocks
  39  */
  40
  41 #define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
  42
  43 /* Maximum DPLL multiplier, divider values for OMAP3 */
  44 #define OMAP3_MAX_DPLL_MULT             2047
  45 #define OMAP3630_MAX_JTYPE_DPLL_MULT    4095
  46 #define OMAP3_MAX_DPLL_DIV              128
  47
  48 /*
  49  * DPLL1 supplies clock to the MPU.
  50  * DPLL2 supplies clock to the IVA2.
  51  * DPLL3 supplies CORE domain clocks.
  52  * DPLL4 supplies peripheral clocks.
  53  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  54  */
  55
  56 /* Forward declarations for DPLL bypass clocks */
  57 static struct clk dpll1_fck;
  58 static struct clk dpll2_fck;
  59
  60 /* PRM CLOCKS */
  61
  62 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  63 static struct clk omap_32k_fck = {
  64         .name           = "omap_32k_fck",
  65         .ops            = &clkops_null,
  66         .rate           = 32768,
  67 };
  68
  69 static struct clk secure_32k_fck = {
  70         .name           = "secure_32k_fck",
  71         .ops            = &clkops_null,
  72         .rate           = 32768,
  73 };
  74
  75 /* Virtual source clocks for osc_sys_ck */
  76 static struct clk virt_12m_ck = {
  77         .name           = "virt_12m_ck",
  78         .ops            = &clkops_null,
  79         .rate           = 12000000,
  80 };
  81
  82 static struct clk virt_13m_ck = {
  83         .name           = "virt_13m_ck",
  84         .ops            = &clkops_null,
  85         .rate           = 13000000,
  86 };
  87
  88 static struct clk virt_16_8m_ck = {
  89         .name           = "virt_16_8m_ck",
  90         .ops            = &clkops_null,
  91         .rate           = 16800000,
  92 };
  93
  94 static struct clk virt_19_2m_ck = {
  95         .name           = "virt_19_2m_ck",
  96         .ops            = &clkops_null,
  97         .rate           = 19200000,
  98 };
  99
 100 static struct clk virt_26m_ck = {
 101         .name           = "virt_26m_ck",
 102         .ops            = &clkops_null,
 103         .rate           = 26000000,
 104 };
 105
 106 static struct clk virt_38_4m_ck = {
 107         .name           = "virt_38_4m_ck",
 108         .ops            = &clkops_null,
 109         .rate           = 38400000,
 110 };
 111
 112 static const struct clksel_rate osc_sys_12m_rates[] = {
 113         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 114         { .div = 0 }
 115 };
 116
 117 static const struct clksel_rate osc_sys_13m_rates[] = {
 118         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 119         { .div = 0 }
 120 };
 121
 122 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 123         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
 124         { .div = 0 }
 125 };
 126
 127 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 128         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
 129         { .div = 0 }
 130 };
 131
 132 static const struct clksel_rate osc_sys_26m_rates[] = {
 133         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
 134         { .div = 0 }
 135 };
 136
 137 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 138         { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
 139         { .div = 0 }
 140 };
 141
 142 static const struct clksel osc_sys_clksel[] = {
 143         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 144         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 145         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 146         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 147         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 148         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 149         { .parent = NULL },
 150 };
 151
 152 /* Oscillator clock */
 153 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 154 static struct clk osc_sys_ck = {
 155         .name           = "osc_sys_ck",
 156         .ops            = &clkops_null,
 157         .init           = &omap2_init_clksel_parent,
 158         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 159         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 160         .clksel         = osc_sys_clksel,
 161         /* REVISIT: deal with autoextclkmode? */
 162         .recalc         = &omap2_clksel_recalc,
 163 };
 164
 165 static const struct clksel_rate div2_rates[] = {
 166         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 167         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 168         { .div = 0 }
 169 };
 170
 171 static const struct clksel sys_clksel[] = {
 172         { .parent = &osc_sys_ck, .rates = div2_rates },
 173         { .parent = NULL }
 174 };
 175
 176 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 177 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 178 static struct clk sys_ck = {
 179         .name           = "sys_ck",
 180         .ops            = &clkops_null,
 181         .parent         = &osc_sys_ck,
 182         .init           = &omap2_init_clksel_parent,
 183         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 184         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 185         .clksel         = sys_clksel,
 186         .recalc         = &omap2_clksel_recalc,
 187 };
 188
 189 static struct clk sys_altclk = {
 190         .name           = "sys_altclk",
 191         .ops            = &clkops_null,
 192 };
 193
 194 /* Optional external clock input for some McBSPs */
 195 static struct clk mcbsp_clks = {
 196         .name           = "mcbsp_clks",
 197         .ops            = &clkops_null,
 198 };
 199
 200 /* PRM EXTERNAL CLOCK OUTPUT */
 201
 202 static struct clk sys_clkout1 = {
 203         .name           = "sys_clkout1",
 204         .ops            = &clkops_omap2_dflt,
 205         .parent         = &osc_sys_ck,
 206         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 207         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 208         .recalc         = &followparent_recalc,
 209 };
 210
 211 /* DPLLS */
 212
 213 /* CM CLOCKS */
 214
 215 static const struct clksel_rate div16_dpll_rates[] = {
 216         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 217         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 218         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 219         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 220         { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
 221         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 222         { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
 223         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
 224         { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
 225         { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
 226         { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
 227         { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
 228         { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
 229         { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
 230         { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
 231         { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
 232         { .div = 0 }
 233 };
 234
 235 static const struct clksel_rate dpll4_rates[] = {
 236         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 237         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 238         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 239         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 240         { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
 241         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 242         { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
 243         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
 244         { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
 245         { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
 246         { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
 247         { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
 248         { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
 249         { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
 250         { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
 251         { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
 252         { .div = 17, .val = 17, .flags = RATE_IN_36XX },
 253         { .div = 18, .val = 18, .flags = RATE_IN_36XX },
 254         { .div = 19, .val = 19, .flags = RATE_IN_36XX },
 255         { .div = 20, .val = 20, .flags = RATE_IN_36XX },
 256         { .div = 21, .val = 21, .flags = RATE_IN_36XX },
 257         { .div = 22, .val = 22, .flags = RATE_IN_36XX },
 258         { .div = 23, .val = 23, .flags = RATE_IN_36XX },
 259         { .div = 24, .val = 24, .flags = RATE_IN_36XX },
 260         { .div = 25, .val = 25, .flags = RATE_IN_36XX },
 261         { .div = 26, .val = 26, .flags = RATE_IN_36XX },
 262         { .div = 27, .val = 27, .flags = RATE_IN_36XX },
 263         { .div = 28, .val = 28, .flags = RATE_IN_36XX },
 264         { .div = 29, .val = 29, .flags = RATE_IN_36XX },
 265         { .div = 30, .val = 30, .flags = RATE_IN_36XX },
 266         { .div = 31, .val = 31, .flags = RATE_IN_36XX },
 267         { .div = 32, .val = 32, .flags = RATE_IN_36XX },
 268         { .div = 0 }
 269 };
 270
 271 /* DPLL1 */
 272 /* MPU clock source */
 273 /* Type: DPLL */
 274 static struct dpll_data dpll1_dd = {
 275         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 276         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 277         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 278         .clk_bypass     = &dpll1_fck,
 279         .clk_ref        = &sys_ck,
 280         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 281         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 282         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 283         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 284         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 285         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 286         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 287         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 288         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 289         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 290         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 291         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 292         .min_divider    = 1,
 293         .max_divider    = OMAP3_MAX_DPLL_DIV,
 294 };
 295
 296 static struct clk dpll1_ck = {
 297         .name           = "dpll1_ck",
 298         .ops            = &clkops_omap3_noncore_dpll_ops,
 299         .parent         = &sys_ck,
 300         .dpll_data      = &dpll1_dd,
 301         .round_rate     = &omap2_dpll_round_rate,
 302         .set_rate       = &omap3_noncore_dpll_set_rate,
 303         .clkdm_name     = "dpll1_clkdm",
 304         .recalc         = &omap3_dpll_recalc,
 305 };
 306
 307 /*
 308  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 309  * DPLL isn't bypassed.
 310  */
 311 static struct clk dpll1_x2_ck = {
 312         .name           = "dpll1_x2_ck",
 313         .ops            = &clkops_null,
 314         .parent         = &dpll1_ck,
 315         .clkdm_name     = "dpll1_clkdm",
 316         .recalc         = &omap3_clkoutx2_recalc,
 317 };
 318
 319 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 320 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 321         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 322         { .parent = NULL }
 323 };
 324
 325 /*
 326  * Does not exist in the TRM - needed to separate the M2 divider from
 327  * bypass selection in mpu_ck
 328  */
 329 static struct clk dpll1_x2m2_ck = {
 330         .name           = "dpll1_x2m2_ck",
 331         .ops            = &clkops_null,
 332         .parent         = &dpll1_x2_ck,
 333         .init           = &omap2_init_clksel_parent,
 334         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 335         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 336         .clksel         = div16_dpll1_x2m2_clksel,
 337         .clkdm_name     = "dpll1_clkdm",
 338         .recalc         = &omap2_clksel_recalc,
 339 };
 340
 341 /* DPLL2 */
 342 /* IVA2 clock source */
 343 /* Type: DPLL */
 344
 345 static struct dpll_data dpll2_dd = {
 346         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 347         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 348         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 349         .clk_bypass     = &dpll2_fck,
 350         .clk_ref        = &sys_ck,
 351         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 352         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 353         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 354         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 355                                 (1 << DPLL_LOW_POWER_BYPASS),
 356         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 357         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 358         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 359         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 360         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 361         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 362         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 363         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 364         .min_divider    = 1,
 365         .max_divider    = OMAP3_MAX_DPLL_DIV,
 366 };
 367
 368 static struct clk dpll2_ck = {
 369         .name           = "dpll2_ck",
 370         .ops            = &clkops_omap3_noncore_dpll_ops,
 371         .parent         = &sys_ck,
 372         .dpll_data      = &dpll2_dd,
 373         .round_rate     = &omap2_dpll_round_rate,
 374         .set_rate       = &omap3_noncore_dpll_set_rate,
 375         .clkdm_name     = "dpll2_clkdm",
 376         .recalc         = &omap3_dpll_recalc,
 377 };
 378
 379 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 380         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 381         { .parent = NULL }
 382 };
 383
 384 /*
 385  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 386  * or CLKOUTX2. CLKOUT seems most plausible.
 387  */
 388 static struct clk dpll2_m2_ck = {
 389         .name           = "dpll2_m2_ck",
 390         .ops            = &clkops_null,
 391         .parent         = &dpll2_ck,
 392         .init           = &omap2_init_clksel_parent,
 393         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 394                                           OMAP3430_CM_CLKSEL2_PLL),
 395         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 396         .clksel         = div16_dpll2_m2x2_clksel,
 397         .clkdm_name     = "dpll2_clkdm",
 398         .recalc         = &omap2_clksel_recalc,
 399 };
 400
 401 /*
 402  * DPLL3
 403  * Source clock for all interfaces and for some device fclks
 404  * REVISIT: Also supports fast relock bypass - not included below
 405  */
 406 static struct dpll_data dpll3_dd = {
 407         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 408         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 409         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 410         .clk_bypass     = &sys_ck,
 411         .clk_ref        = &sys_ck,
 412         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 413         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 414         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 415         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 416         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 417         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 418         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 419         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 420         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 421         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 422         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 423         .min_divider    = 1,
 424         .max_divider    = OMAP3_MAX_DPLL_DIV,
 425 };
 426
 427 static struct clk dpll3_ck = {
 428         .name           = "dpll3_ck",
 429         .ops            = &clkops_omap3_core_dpll_ops,
 430         .parent         = &sys_ck,
 431         .dpll_data      = &dpll3_dd,
 432         .round_rate     = &omap2_dpll_round_rate,
 433         .clkdm_name     = "dpll3_clkdm",
 434         .recalc         = &omap3_dpll_recalc,
 435 };
 436
 437 /*
 438  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 439  * DPLL isn't bypassed
 440  */
 441 static struct clk dpll3_x2_ck = {
 442         .name           = "dpll3_x2_ck",
 443         .ops            = &clkops_null,
 444         .parent         = &dpll3_ck,
 445         .clkdm_name     = "dpll3_clkdm",
 446         .recalc         = &omap3_clkoutx2_recalc,
 447 };
 448
 449 static const struct clksel_rate div31_dpll3_rates[] = {
 450         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 451         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 452         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
 453         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
 454         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
 455         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
 456         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
 457         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
 458         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
 459         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
 460         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
 461         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
 462         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
 463         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
 464         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
 465         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
 466         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
 467         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
 468         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
 469         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
 470         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
 471         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
 472         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
 473         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
 474         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
 475         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
 476         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
 477         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
 478         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
 479         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
 480         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
 481         { .div = 0 },
 482 };
 483
 484 static const struct clksel div31_dpll3m2_clksel[] = {
 485         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 486         { .parent = NULL }
 487 };
 488
 489 /* DPLL3 output M2 - primary control point for CORE speed */
 490 static struct clk dpll3_m2_ck = {
 491         .name           = "dpll3_m2_ck",
 492         .ops            = &clkops_null,
 493         .parent         = &dpll3_ck,
 494         .init           = &omap2_init_clksel_parent,
 495         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 496         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 497         .clksel         = div31_dpll3m2_clksel,
 498         .clkdm_name     = "dpll3_clkdm",
 499         .round_rate     = &omap2_clksel_round_rate,
 500         .set_rate       = &omap3_core_dpll_m2_set_rate,
 501         .recalc         = &omap2_clksel_recalc,
 502 };
 503
 504 static struct clk core_ck = {
 505         .name           = "core_ck",
 506         .ops            = &clkops_null,
 507         .parent         = &dpll3_m2_ck,
 508         .recalc         = &followparent_recalc,
 509 };
 510
 511 static struct clk dpll3_m2x2_ck = {
 512         .name           = "dpll3_m2x2_ck",
 513         .ops            = &clkops_null,
 514         .parent         = &dpll3_m2_ck,
 515         .clkdm_name     = "dpll3_clkdm",
 516         .recalc         = &omap3_clkoutx2_recalc,
 517 };
 518
 519 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 520 static const struct clksel div16_dpll3_clksel[] = {
 521         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 522         { .parent = NULL }
 523 };
 524
 525 /* This virtual clock is the source for dpll3_m3x2_ck */
 526 static struct clk dpll3_m3_ck = {
 527         .name           = "dpll3_m3_ck",
 528         .ops            = &clkops_null,
 529         .parent         = &dpll3_ck,
 530         .init           = &omap2_init_clksel_parent,
 531         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 532         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 533         .clksel         = div16_dpll3_clksel,
 534         .clkdm_name     = "dpll3_clkdm",
 535         .recalc         = &omap2_clksel_recalc,
 536 };
 537
 538 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 539 static struct clk dpll3_m3x2_ck = {
 540         .name           = "dpll3_m3x2_ck",
 541         .ops            = &clkops_omap2_dflt_wait,
 542         .parent         = &dpll3_m3_ck,
 543         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 544         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 545         .flags          = INVERT_ENABLE,
 546         .clkdm_name     = "dpll3_clkdm",
 547         .recalc         = &omap3_clkoutx2_recalc,
 548 };
 549
 550 static struct clk emu_core_alwon_ck = {
 551         .name           = "emu_core_alwon_ck",
 552         .ops            = &clkops_null,
 553         .parent         = &dpll3_m3x2_ck,
 554         .clkdm_name     = "dpll3_clkdm",
 555         .recalc         = &followparent_recalc,
 556 };
 557
 558 /* DPLL4 */
 559 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 560 /* Type: DPLL */
 561 static struct dpll_data dpll4_dd;
 562
 563 static struct dpll_data dpll4_dd_34xx __initdata = {
 564         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 565         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 566         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 567         .clk_bypass     = &sys_ck,
 568         .clk_ref        = &sys_ck,
 569         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 570         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 571         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 572         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 573         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 574         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 575         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 576         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 577         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 578         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 579         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 580         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 581         .min_divider    = 1,
 582         .max_divider    = OMAP3_MAX_DPLL_DIV,
 583 };
 584
 585 static struct dpll_data dpll4_dd_3630 __initdata = {
 586         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 587         .mult_mask      = OMAP3630_PERIPH_DPLL_MULT_MASK,
 588         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 589         .clk_bypass     = &sys_ck,
 590         .clk_ref        = &sys_ck,
 591         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 592         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 593         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 594         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 595         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 596         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 597         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 598         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 599         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 600         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 601         .dco_mask       = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
 602         .sddiv_mask     = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
 603         .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
 604         .min_divider    = 1,
 605         .max_divider    = OMAP3_MAX_DPLL_DIV,
 606         .flags          = DPLL_J_TYPE
 607 };
 608
 609 static struct clk dpll4_ck = {
 610         .name           = "dpll4_ck",
 611         .ops            = &clkops_omap3_noncore_dpll_ops,
 612         .parent         = &sys_ck,
 613         .dpll_data      = &dpll4_dd,
 614         .round_rate     = &omap2_dpll_round_rate,
 615         .set_rate       = &omap3_dpll4_set_rate,
 616         .clkdm_name     = "dpll4_clkdm",
 617         .recalc         = &omap3_dpll_recalc,
 618 };
 619
 620 /*
 621  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 622  * DPLL isn't bypassed --
 623  * XXX does this serve any downstream clocks?
 624  */
 625 static struct clk dpll4_x2_ck = {
 626         .name           = "dpll4_x2_ck",
 627         .ops            = &clkops_null,
 628         .parent         = &dpll4_ck,
 629         .clkdm_name     = "dpll4_clkdm",
 630         .recalc         = &omap3_clkoutx2_recalc,
 631 };
 632
 633 static const struct clksel dpll4_clksel[] = {
 634         { .parent = &dpll4_ck, .rates = dpll4_rates },
 635         { .parent = NULL }
 636 };
 637
 638 /* This virtual clock is the source for dpll4_m2x2_ck */
 639 static struct clk dpll4_m2_ck = {
 640         .name           = "dpll4_m2_ck",
 641         .ops            = &clkops_null,
 642         .parent         = &dpll4_ck,
 643         .init           = &omap2_init_clksel_parent,
 644         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 645         .clksel_mask    = OMAP3630_DIV_96M_MASK,
 646         .clksel         = dpll4_clksel,
 647         .clkdm_name     = "dpll4_clkdm",
 648         .recalc         = &omap2_clksel_recalc,
 649 };
 650
 651 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 652 static struct clk dpll4_m2x2_ck = {
 653         .name           = "dpll4_m2x2_ck",
 654         .ops            = &clkops_omap2_dflt_wait,
 655         .parent         = &dpll4_m2_ck,
 656         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 657         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 658         .flags          = INVERT_ENABLE,
 659         .clkdm_name     = "dpll4_clkdm",
 660         .recalc         = &omap3_clkoutx2_recalc,
 661 };
 662
 663 /*
 664  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 665  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 666  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 667  * CM_96K_(F)CLK.
 668  */
 669
 670 /* Adding 192MHz Clock node needed by SGX */
 671 static struct clk omap_192m_alwon_fck = {
 672         .name           = "omap_192m_alwon_fck",
 673         .ops            = &clkops_null,
 674         .parent         = &dpll4_m2x2_ck,
 675         .recalc         = &followparent_recalc,
 676 };
 677
 678 static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
 679         { .div = 1, .val = 1, .flags = RATE_IN_36XX },
 680         { .div = 2, .val = 2, .flags = RATE_IN_36XX },
 681         { .div = 0 }
 682 };
 683
 684 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 685         { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
 686         { .parent = NULL }
 687 };
 688
 689 static const struct clksel_rate omap_96m_dpll_rates[] = {
 690         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 691         { .div = 0 }
 692 };
 693
 694 static const struct clksel_rate omap_96m_sys_rates[] = {
 695         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 696         { .div = 0 }
 697 };
 698
 699 static struct clk omap_96m_alwon_fck = {
 700         .name           = "omap_96m_alwon_fck",
 701         .ops            = &clkops_null,
 702         .parent         = &dpll4_m2x2_ck,
 703         .recalc         = &followparent_recalc,
 704 };
 705
 706 static struct clk omap_96m_alwon_fck_3630 = {
 707         .name           = "omap_96m_alwon_fck",
 708         .parent         = &omap_192m_alwon_fck,
 709         .init           = &omap2_init_clksel_parent,
 710         .ops            = &clkops_null,
 711         .recalc         = &omap2_clksel_recalc,
 712         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 713         .clksel_mask    = OMAP3630_CLKSEL_96M_MASK,
 714         .clksel         = omap_96m_alwon_fck_clksel
 715 };
 716
 717 static struct clk cm_96m_fck = {
 718         .name           = "cm_96m_fck",
 719         .ops            = &clkops_null,
 720         .parent         = &omap_96m_alwon_fck,
 721         .recalc         = &followparent_recalc,
 722 };
 723
 724 static const struct clksel omap_96m_fck_clksel[] = {
 725         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 726         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 727         { .parent = NULL }
 728 };
 729
 730 static struct clk omap_96m_fck = {
 731         .name           = "omap_96m_fck",
 732         .ops            = &clkops_null,
 733         .parent         = &sys_ck,
 734         .init           = &omap2_init_clksel_parent,
 735         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 736         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 737         .clksel         = omap_96m_fck_clksel,
 738         .recalc         = &omap2_clksel_recalc,
 739 };
 740
 741 /* This virtual clock is the source for dpll4_m3x2_ck */
 742 static struct clk dpll4_m3_ck = {
 743         .name           = "dpll4_m3_ck",
 744         .ops            = &clkops_null,
 745         .parent         = &dpll4_ck,
 746         .init           = &omap2_init_clksel_parent,
 747         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 748         .clksel_mask    = OMAP3630_CLKSEL_TV_MASK,
 749         .clksel         = dpll4_clksel,
 750         .clkdm_name     = "dpll4_clkdm",
 751         .recalc         = &omap2_clksel_recalc,
 752 };
 753
 754 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 755 static struct clk dpll4_m3x2_ck = {
 756         .name           = "dpll4_m3x2_ck",
 757         .ops            = &clkops_omap2_dflt_wait,
 758         .parent         = &dpll4_m3_ck,
 759         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 760         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 761         .flags          = INVERT_ENABLE,
 762         .clkdm_name     = "dpll4_clkdm",
 763         .recalc         = &omap3_clkoutx2_recalc,
 764 };
 765
 766 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 767         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 768         { .div = 0 }
 769 };
 770
 771 static const struct clksel_rate omap_54m_alt_rates[] = {
 772         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 773         { .div = 0 }
 774 };
 775
 776 static const struct clksel omap_54m_clksel[] = {
 777         { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 778         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 779         { .parent = NULL }
 780 };
 781
 782 static struct clk omap_54m_fck = {
 783         .name           = "omap_54m_fck",
 784         .ops            = &clkops_null,
 785         .init           = &omap2_init_clksel_parent,
 786         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 787         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 788         .clksel         = omap_54m_clksel,
 789         .recalc         = &omap2_clksel_recalc,
 790 };
 791
 792 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 793         { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
 794         { .div = 0 }
 795 };
 796
 797 static const struct clksel_rate omap_48m_alt_rates[] = {
 798         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 799         { .div = 0 }
 800 };
 801
 802 static const struct clksel omap_48m_clksel[] = {
 803         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 804         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 805         { .parent = NULL }
 806 };
 807
 808 static struct clk omap_48m_fck = {
 809         .name           = "omap_48m_fck",
 810         .ops            = &clkops_null,
 811         .init           = &omap2_init_clksel_parent,
 812         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 813         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 814         .clksel         = omap_48m_clksel,
 815         .recalc         = &omap2_clksel_recalc,
 816 };
 817
 818 static struct clk omap_12m_fck = {
 819         .name           = "omap_12m_fck",
 820         .ops            = &clkops_null,
 821         .parent         = &omap_48m_fck,
 822         .fixed_div      = 4,
 823         .recalc         = &omap_fixed_divisor_recalc,
 824 };
 825
 826 /* This virtual clock is the source for dpll4_m4x2_ck */
 827 static struct clk dpll4_m4_ck = {
 828         .name           = "dpll4_m4_ck",
 829         .ops            = &clkops_null,
 830         .parent         = &dpll4_ck,
 831         .init           = &omap2_init_clksel_parent,
 832         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 833         .clksel_mask    = OMAP3630_CLKSEL_DSS1_MASK,
 834         .clksel         = dpll4_clksel,
 835         .clkdm_name     = "dpll4_clkdm",
 836         .recalc         = &omap2_clksel_recalc,
 837         .set_rate       = &omap2_clksel_set_rate,
 838         .round_rate     = &omap2_clksel_round_rate,
 839 };
 840
 841 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 842 static struct clk dpll4_m4x2_ck = {
 843         .name           = "dpll4_m4x2_ck",
 844         .ops            = &clkops_omap2_dflt_wait,
 845         .parent         = &dpll4_m4_ck,
 846         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 847         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 848         .flags          = INVERT_ENABLE,
 849         .clkdm_name     = "dpll4_clkdm",
 850         .recalc         = &omap3_clkoutx2_recalc,
 851 };
 852
 853 /* This virtual clock is the source for dpll4_m5x2_ck */
 854 static struct clk dpll4_m5_ck = {
 855         .name           = "dpll4_m5_ck",
 856         .ops            = &clkops_null,
 857         .parent         = &dpll4_ck,
 858         .init           = &omap2_init_clksel_parent,
 859         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 860         .clksel_mask    = OMAP3630_CLKSEL_CAM_MASK,
 861         .clksel         = dpll4_clksel,
 862         .clkdm_name     = "dpll4_clkdm",
 863         .set_rate       = &omap2_clksel_set_rate,
 864         .round_rate     = &omap2_clksel_round_rate,
 865         .recalc         = &omap2_clksel_recalc,
 866 };
 867
 868 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 869 static struct clk dpll4_m5x2_ck = {
 870         .name           = "dpll4_m5x2_ck",
 871         .ops            = &clkops_omap2_dflt_wait,
 872         .parent         = &dpll4_m5_ck,
 873         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 874         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 875         .flags          = INVERT_ENABLE,
 876         .clkdm_name     = "dpll4_clkdm",
 877         .recalc         = &omap3_clkoutx2_recalc,
 878 };
 879
 880 /* This virtual clock is the source for dpll4_m6x2_ck */
 881 static struct clk dpll4_m6_ck = {
 882         .name           = "dpll4_m6_ck",
 883         .ops            = &clkops_null,
 884         .parent         = &dpll4_ck,
 885         .init           = &omap2_init_clksel_parent,
 886         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 887         .clksel_mask    = OMAP3630_DIV_DPLL4_MASK,
 888         .clksel         = dpll4_clksel,
 889         .clkdm_name     = "dpll4_clkdm",
 890         .recalc         = &omap2_clksel_recalc,
 891 };
 892
 893 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 894 static struct clk dpll4_m6x2_ck = {
 895         .name           = "dpll4_m6x2_ck",
 896         .ops            = &clkops_omap2_dflt_wait,
 897         .parent         = &dpll4_m6_ck,
 898         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 899         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 900         .flags          = INVERT_ENABLE,
 901         .clkdm_name     = "dpll4_clkdm",
 902         .recalc         = &omap3_clkoutx2_recalc,
 903 };
 904
 905 static struct clk emu_per_alwon_ck = {
 906         .name           = "emu_per_alwon_ck",
 907         .ops            = &clkops_null,
 908         .parent         = &dpll4_m6x2_ck,
 909         .clkdm_name     = "dpll4_clkdm",
 910         .recalc         = &followparent_recalc,
 911 };
 912
 913 /* DPLL5 */
 914 /* Supplies 120MHz clock, USIM source clock */
 915 /* Type: DPLL */
 916 /* 3430ES2 only */
 917 static struct dpll_data dpll5_dd = {
 918         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 919         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 920         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 921         .clk_bypass     = &sys_ck,
 922         .clk_ref        = &sys_ck,
 923         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 924         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 925         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 926         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 927         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 928         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 929         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 930         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 931         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 932         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 933         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 934         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 935         .min_divider    = 1,
 936         .max_divider    = OMAP3_MAX_DPLL_DIV,
 937 };
 938
 939 static struct clk dpll5_ck = {
 940         .name           = "dpll5_ck",
 941         .ops            = &clkops_omap3_noncore_dpll_ops,
 942         .parent         = &sys_ck,
 943         .dpll_data      = &dpll5_dd,
 944         .round_rate     = &omap2_dpll_round_rate,
 945         .set_rate       = &omap3_dpll5_set_rate,
 946         .clkdm_name     = "dpll5_clkdm",
 947         .recalc         = &omap3_dpll_recalc,
 948 };
 949
 950 static const struct clksel div16_dpll5_clksel[] = {
 951         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 952         { .parent = NULL }
 953 };
 954
 955 static struct clk dpll5_m2_ck = {
 956         .name           = "dpll5_m2_ck",
 957         .ops            = &clkops_null,
 958         .parent         = &dpll5_ck,
 959         .init           = &omap2_init_clksel_parent,
 960         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 961         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 962         .clksel         = div16_dpll5_clksel,
 963         .clkdm_name     = "dpll5_clkdm",
 964         .recalc         = &omap2_clksel_recalc,
 965 };
 966
 967 /* CM EXTERNAL CLOCK OUTPUTS */
 968
 969 static const struct clksel_rate clkout2_src_core_rates[] = {
 970         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 971         { .div = 0 }
 972 };
 973
 974 static const struct clksel_rate clkout2_src_sys_rates[] = {
 975         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 976         { .div = 0 }
 977 };
 978
 979 static const struct clksel_rate clkout2_src_96m_rates[] = {
 980         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
 981         { .div = 0 }
 982 };
 983
 984 static const struct clksel_rate clkout2_src_54m_rates[] = {
 985         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
 986         { .div = 0 }
 987 };
 988
 989 static const struct clksel clkout2_src_clksel[] = {
 990         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
 991         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
 992         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
 993         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
 994         { .parent = NULL }
 995 };
 996
 997 static struct clk clkout2_src_ck = {
 998         .name           = "clkout2_src_ck",
 999         .ops            = &clkops_omap2_dflt,
1000         .init           = &omap2_init_clksel_parent,
1001         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
1002         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
1003         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1004         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
1005         .clksel         = clkout2_src_clksel,
1006         .clkdm_name     = "core_clkdm",
1007         .recalc         = &omap2_clksel_recalc,
1008 };
1009
1010 static const struct clksel_rate sys_clkout2_rates[] = {
1011         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1012         { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1013         { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
1014         { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
1015         { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
1016         { .div = 0 },
1017 };
1018
1019 static const struct clksel sys_clkout2_clksel[] = {
1020         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1021         { .parent = NULL },
1022 };
1023
1024 static struct clk sys_clkout2 = {
1025         .name           = "sys_clkout2",
1026         .ops            = &clkops_null,
1027         .init           = &omap2_init_clksel_parent,
1028         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1029         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1030         .clksel         = sys_clkout2_clksel,
1031         .recalc         = &omap2_clksel_recalc,
1032         .round_rate     = &omap2_clksel_round_rate,
1033         .set_rate       = &omap2_clksel_set_rate
1034 };
1035
1036 /* CM OUTPUT CLOCKS */
1037
1038 static struct clk corex2_fck = {
1039         .name           = "corex2_fck",
1040         .ops            = &clkops_null,
1041         .parent         = &dpll3_m2x2_ck,
1042         .recalc         = &followparent_recalc,
1043 };
1044
1045 /* DPLL power domain clock controls */
1046
1047 static const struct clksel_rate div4_rates[] = {
1048         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1049         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1050         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1051         { .div = 0 }
1052 };
1053
1054 static const struct clksel div4_core_clksel[] = {
1055         { .parent = &core_ck, .rates = div4_rates },
1056         { .parent = NULL }
1057 };
1058
1059 /*
1060  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1061  * may be inconsistent here?
1062  */
1063 static struct clk dpll1_fck = {
1064         .name           = "dpll1_fck",
1065         .ops            = &clkops_null,
1066         .parent         = &core_ck,
1067         .init           = &omap2_init_clksel_parent,
1068         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1069         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1070         .clksel         = div4_core_clksel,
1071         .recalc         = &omap2_clksel_recalc,
1072 };
1073
1074 static struct clk mpu_ck = {
1075         .name           = "mpu_ck",
1076         .ops            = &clkops_null,
1077         .parent         = &dpll1_x2m2_ck,
1078         .clkdm_name     = "mpu_clkdm",
1079         .recalc         = &followparent_recalc,
1080 };
1081
1082 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1083 static const struct clksel_rate arm_fck_rates[] = {
1084         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1085         { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1086         { .div = 0 },
1087 };
1088
1089 static const struct clksel arm_fck_clksel[] = {
1090         { .parent = &mpu_ck, .rates = arm_fck_rates },
1091         { .parent = NULL }
1092 };
1093
1094 static struct clk arm_fck = {
1095         .name           = "arm_fck",
1096         .ops            = &clkops_null,
1097         .parent         = &mpu_ck,
1098         .init           = &omap2_init_clksel_parent,
1099         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1100         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1101         .clksel         = arm_fck_clksel,
1102         .clkdm_name     = "mpu_clkdm",
1103         .recalc         = &omap2_clksel_recalc,
1104 };
1105
1106 /* XXX What about neon_clkdm ? */
1107
1108 /*
1109  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1110  * although it is referenced - so this is a guess
1111  */
1112 static struct clk emu_mpu_alwon_ck = {
1113         .name           = "emu_mpu_alwon_ck",
1114         .ops            = &clkops_null,
1115         .parent         = &mpu_ck,
1116         .recalc         = &followparent_recalc,
1117 };
1118
1119 static struct clk dpll2_fck = {
1120         .name           = "dpll2_fck",
1121         .ops            = &clkops_null,
1122         .parent         = &core_ck,
1123         .init           = &omap2_init_clksel_parent,
1124         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1125         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1126         .clksel         = div4_core_clksel,
1127         .recalc         = &omap2_clksel_recalc,
1128 };
1129
1130 static struct clk iva2_ck = {
1131         .name           = "iva2_ck",
1132         .ops            = &clkops_omap2_dflt_wait,
1133         .parent         = &dpll2_m2_ck,
1134         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1135         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1136         .clkdm_name     = "iva2_clkdm",
1137         .recalc         = &followparent_recalc,
1138 };
1139
1140 /* Common interface clocks */
1141
1142 static const struct clksel div2_core_clksel[] = {
1143         { .parent = &core_ck, .rates = div2_rates },
1144         { .parent = NULL }
1145 };
1146
1147 static struct clk l3_ick = {
1148         .name           = "l3_ick",
1149         .ops            = &clkops_null,
1150         .parent         = &core_ck,
1151         .init           = &omap2_init_clksel_parent,
1152         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1153         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1154         .clksel         = div2_core_clksel,
1155         .clkdm_name     = "core_l3_clkdm",
1156         .recalc         = &omap2_clksel_recalc,
1157 };
1158
1159 static const struct clksel div2_l3_clksel[] = {
1160         { .parent = &l3_ick, .rates = div2_rates },
1161         { .parent = NULL }
1162 };
1163
1164 static struct clk l4_ick = {
1165         .name           = "l4_ick",
1166         .ops            = &clkops_null,
1167         .parent         = &l3_ick,
1168         .init           = &omap2_init_clksel_parent,
1169         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1170         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1171         .clksel         = div2_l3_clksel,
1172         .clkdm_name     = "core_l4_clkdm",
1173         .recalc         = &omap2_clksel_recalc,
1174
1175 };
1176
1177 static const struct clksel div2_l4_clksel[] = {
1178         { .parent = &l4_ick, .rates = div2_rates },
1179         { .parent = NULL }
1180 };
1181
1182 static struct clk rm_ick = {
1183         .name           = "rm_ick",
1184         .ops            = &clkops_null,
1185         .parent         = &l4_ick,
1186         .init           = &omap2_init_clksel_parent,
1187         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1188         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1189         .clksel         = div2_l4_clksel,
1190         .recalc         = &omap2_clksel_recalc,
1191 };
1192
1193 /* GFX power domain */
1194
1195 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1196
1197 static const struct clksel gfx_l3_clksel[] = {
1198         { .parent = &l3_ick, .rates = gfx_l3_rates },
1199         { .parent = NULL }
1200 };
1201
1202 /*
1203  * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
1204  * This interface clock does not have a CM_AUTOIDLE bit
1205  */
1206 static struct clk gfx_l3_ck = {
1207         .name           = "gfx_l3_ck",
1208         .ops            = &clkops_omap2_dflt_wait,
1209         .parent         = &l3_ick,
1210         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1211         .enable_bit     = OMAP_EN_GFX_SHIFT,
1212         .recalc         = &followparent_recalc,
1213 };
1214
1215 static struct clk gfx_l3_fck = {
1216         .name           = "gfx_l3_fck",
1217         .ops            = &clkops_null,
1218         .parent         = &gfx_l3_ck,
1219         .init           = &omap2_init_clksel_parent,
1220         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1221         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1222         .clksel         = gfx_l3_clksel,
1223         .clkdm_name     = "gfx_3430es1_clkdm",
1224         .recalc         = &omap2_clksel_recalc,
1225 };
1226
1227 static struct clk gfx_l3_ick = {
1228         .name           = "gfx_l3_ick",
1229         .ops            = &clkops_null,
1230         .parent         = &gfx_l3_ck,
1231         .clkdm_name     = "gfx_3430es1_clkdm",
1232         .recalc         = &followparent_recalc,
1233 };
1234
1235 static struct clk gfx_cg1_ck = {
1236         .name           = "gfx_cg1_ck",
1237         .ops            = &clkops_omap2_dflt_wait,
1238         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1239         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1240         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1241         .clkdm_name     = "gfx_3430es1_clkdm",
1242         .recalc         = &followparent_recalc,
1243 };
1244
1245 static struct clk gfx_cg2_ck = {
1246         .name           = "gfx_cg2_ck",
1247         .ops            = &clkops_omap2_dflt_wait,
1248         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1249         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1250         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1251         .clkdm_name     = "gfx_3430es1_clkdm",
1252         .recalc         = &followparent_recalc,
1253 };
1254
1255 /* SGX power domain - 3430ES2 only */
1256
1257 static const struct clksel_rate sgx_core_rates[] = {
1258         { .div = 2, .val = 5, .flags = RATE_IN_36XX },
1259         { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
1260         { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
1261         { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
1262         { .div = 0 },
1263 };
1264
1265 static const struct clksel_rate sgx_192m_rates[] = {
1266         { .div = 1,  .val = 4, .flags = RATE_IN_36XX },
1267         { .div = 0 },
1268 };
1269
1270 static const struct clksel_rate sgx_corex2_rates[] = {
1271         { .div = 3, .val = 6, .flags = RATE_IN_36XX },
1272         { .div = 5, .val = 7, .flags = RATE_IN_36XX },
1273         { .div = 0 },
1274 };
1275
1276 static const struct clksel_rate sgx_96m_rates[] = {
1277         { .div = 1,  .val = 3, .flags = RATE_IN_3XXX },
1278         { .div = 0 },
1279 };
1280
1281 static const struct clksel sgx_clksel[] = {
1282         { .parent = &core_ck,    .rates = sgx_core_rates },
1283         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1284         { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
1285         { .parent = &corex2_fck, .rates = sgx_corex2_rates },
1286         { .parent = NULL }
1287 };
1288
1289 static struct clk sgx_fck = {
1290         .name           = "sgx_fck",
1291         .ops            = &clkops_omap2_dflt_wait,
1292         .init           = &omap2_init_clksel_parent,
1293         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1294         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1295         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1296         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1297         .clksel         = sgx_clksel,
1298         .clkdm_name     = "sgx_clkdm",
1299         .recalc         = &omap2_clksel_recalc,
1300         .set_rate       = &omap2_clksel_set_rate,
1301         .round_rate     = &omap2_clksel_round_rate
1302 };
1303
1304 /* This interface clock does not have a CM_AUTOIDLE bit */
1305 static struct clk sgx_ick = {
1306         .name           = "sgx_ick",
1307         .ops            = &clkops_omap2_dflt_wait,
1308         .parent         = &l3_ick,
1309         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1310         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1311         .clkdm_name     = "sgx_clkdm",
1312         .recalc         = &followparent_recalc,
1313 };
1314
1315 /* CORE power domain */
1316
1317 static struct clk d2d_26m_fck = {
1318         .name           = "d2d_26m_fck",
1319         .ops            = &clkops_omap2_dflt_wait,
1320         .parent         = &sys_ck,
1321         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1322         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1323         .clkdm_name     = "d2d_clkdm",
1324         .recalc         = &followparent_recalc,
1325 };
1326
1327 static struct clk modem_fck = {
1328         .name           = "modem_fck",
1329         .ops            = &clkops_omap2_mdmclk_dflt_wait,
1330         .parent         = &sys_ck,
1331         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1332         .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
1333         .clkdm_name     = "d2d_clkdm",
1334         .recalc         = &followparent_recalc,
1335 };
1336
1337 static struct clk sad2d_ick = {
1338         .name           = "sad2d_ick",
1339         .ops            = &clkops_omap2_iclk_dflt_wait,
1340         .parent         = &l3_ick,
1341         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1342         .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
1343         .clkdm_name     = "d2d_clkdm",
1344         .recalc         = &followparent_recalc,
1345 };
1346
1347 static struct clk mad2d_ick = {
1348         .name           = "mad2d_ick",
1349         .ops            = &clkops_omap2_iclk_dflt_wait,
1350         .parent         = &l3_ick,
1351         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1352         .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
1353         .clkdm_name     = "d2d_clkdm",
1354         .recalc         = &followparent_recalc,
1355 };
1356
1357 static const struct clksel omap343x_gpt_clksel[] = {
1358         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1359         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1360         { .parent = NULL}
1361 };
1362
1363 static struct clk gpt10_fck = {
1364         .name           = "gpt10_fck",
1365         .ops            = &clkops_omap2_dflt_wait,
1366         .parent         = &sys_ck,
1367         .init           = &omap2_init_clksel_parent,
1368         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1369         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1370         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1371         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1372         .clksel         = omap343x_gpt_clksel,
1373         .clkdm_name     = "core_l4_clkdm",
1374         .recalc         = &omap2_clksel_recalc,
1375 };
1376
1377 static struct clk gpt11_fck = {
1378         .name           = "gpt11_fck",
1379         .ops            = &clkops_omap2_dflt_wait,
1380         .parent         = &sys_ck,
1381         .init           = &omap2_init_clksel_parent,
1382         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1383         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1384         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1385         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1386         .clksel         = omap343x_gpt_clksel,
1387         .clkdm_name     = "core_l4_clkdm",
1388         .recalc         = &omap2_clksel_recalc,
1389 };
1390
1391 static struct clk cpefuse_fck = {
1392         .name           = "cpefuse_fck",
1393         .ops            = &clkops_omap2_dflt,
1394         .parent         = &sys_ck,
1395         .clkdm_name     = "core_l4_clkdm",
1396         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1397         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1398         .recalc         = &followparent_recalc,
1399 };
1400
1401 static struct clk ts_fck = {
1402         .name           = "ts_fck",
1403         .ops            = &clkops_omap2_dflt,
1404         .parent         = &omap_32k_fck,
1405         .clkdm_name     = "core_l4_clkdm",
1406         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1407         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1408         .recalc         = &followparent_recalc,
1409 };
1410
1411 static struct clk usbtll_fck = {
1412         .name           = "usbtll_fck",
1413         .ops            = &clkops_omap2_dflt_wait,
1414         .parent         = &dpll5_m2_ck,
1415         .clkdm_name     = "core_l4_clkdm",
1416         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1417         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1418         .recalc         = &followparent_recalc,
1419 };
1420
1421 /* CORE 96M FCLK-derived clocks */
1422
1423 static struct clk core_96m_fck = {
1424         .name           = "core_96m_fck",
1425         .ops            = &clkops_null,
1426         .parent         = &omap_96m_fck,
1427         .clkdm_name     = "core_l4_clkdm",
1428         .recalc         = &followparent_recalc,
1429 };
1430
1431 static struct clk mmchs3_fck = {
1432         .name           = "mmchs3_fck",
1433         .ops            = &clkops_omap2_dflt_wait,
1434         .parent         = &core_96m_fck,
1435         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1436         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1437         .clkdm_name     = "core_l4_clkdm",
1438         .recalc         = &followparent_recalc,
1439 };
1440
1441 static struct clk mmchs2_fck = {
1442         .name           = "mmchs2_fck",
1443         .ops            = &clkops_omap2_dflt_wait,
1444         .parent         = &core_96m_fck,
1445         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1446         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1447         .clkdm_name     = "core_l4_clkdm",
1448         .recalc         = &followparent_recalc,
1449 };
1450
1451 static struct clk mspro_fck = {
1452         .name           = "mspro_fck",
1453         .ops            = &clkops_omap2_dflt_wait,
1454         .parent         = &core_96m_fck,
1455         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1456         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1457         .clkdm_name     = "core_l4_clkdm",
1458         .recalc         = &followparent_recalc,
1459 };
1460
1461 static struct clk mmchs1_fck = {
1462         .name           = "mmchs1_fck",
1463         .ops            = &clkops_omap2_dflt_wait,
1464         .parent         = &core_96m_fck,
1465         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1466         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1467         .clkdm_name     = "core_l4_clkdm",
1468         .recalc         = &followparent_recalc,
1469 };
1470
1471 static struct clk i2c3_fck = {
1472         .name           = "i2c3_fck",
1473         .ops            = &clkops_omap2_dflt_wait,
1474         .parent         = &core_96m_fck,
1475         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1476         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1477         .clkdm_name     = "core_l4_clkdm",
1478         .recalc         = &followparent_recalc,
1479 };
1480
1481 static struct clk i2c2_fck = {
1482         .name           = "i2c2_fck",
1483         .ops            = &clkops_omap2_dflt_wait,
1484         .parent         = &core_96m_fck,
1485         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1486         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1487         .clkdm_name     = "core_l4_clkdm",
1488         .recalc         = &followparent_recalc,
1489 };
1490
1491 static struct clk i2c1_fck = {
1492         .name           = "i2c1_fck",
1493         .ops            = &clkops_omap2_dflt_wait,
1494         .parent         = &core_96m_fck,
1495         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1496         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1497         .clkdm_name     = "core_l4_clkdm",
1498         .recalc         = &followparent_recalc,
1499 };
1500
1501 /*
1502  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1503  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1504  */
1505 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1506         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1507         { .div = 0 }
1508 };
1509
1510 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1511         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1512         { .div = 0 }
1513 };
1514
1515 static const struct clksel mcbsp_15_clksel[] = {
1516         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1517         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1518         { .parent = NULL }
1519 };
1520
1521 static struct clk mcbsp5_fck = {
1522         .name           = "mcbsp5_fck",
1523         .ops            = &clkops_omap2_dflt_wait,
1524         .init           = &omap2_init_clksel_parent,
1525         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1526         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1527         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1528         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1529         .clksel         = mcbsp_15_clksel,
1530         .clkdm_name     = "core_l4_clkdm",
1531         .recalc         = &omap2_clksel_recalc,
1532 };
1533
1534 static struct clk mcbsp1_fck = {
1535         .name           = "mcbsp1_fck",
1536         .ops            = &clkops_omap2_dflt_wait,
1537         .init           = &omap2_init_clksel_parent,
1538         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1539         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1540         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1541         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1542         .clksel         = mcbsp_15_clksel,
1543         .clkdm_name     = "core_l4_clkdm",
1544         .recalc         = &omap2_clksel_recalc,
1545 };
1546
1547 /* CORE_48M_FCK-derived clocks */
1548
1549 static struct clk core_48m_fck = {
1550         .name           = "core_48m_fck",
1551         .ops            = &clkops_null,
1552         .parent         = &omap_48m_fck,
1553         .clkdm_name     = "core_l4_clkdm",
1554         .recalc         = &followparent_recalc,
1555 };
1556
1557 static struct clk mcspi4_fck = {
1558         .name           = "mcspi4_fck",
1559         .ops            = &clkops_omap2_dflt_wait,
1560         .parent         = &core_48m_fck,
1561         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1562         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1563         .recalc         = &followparent_recalc,
1564         .clkdm_name     = "core_l4_clkdm",
1565 };
1566
1567 static struct clk mcspi3_fck = {
1568         .name           = "mcspi3_fck",
1569         .ops            = &clkops_omap2_dflt_wait,
1570         .parent         = &core_48m_fck,
1571         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1572         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1573         .recalc         = &followparent_recalc,
1574         .clkdm_name     = "core_l4_clkdm",
1575 };
1576
1577 static struct clk mcspi2_fck = {
1578         .name           = "mcspi2_fck",
1579         .ops            = &clkops_omap2_dflt_wait,
1580         .parent         = &core_48m_fck,
1581         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1582         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1583         .recalc         = &followparent_recalc,
1584         .clkdm_name     = "core_l4_clkdm",
1585 };
1586
1587 static struct clk mcspi1_fck = {
1588         .name           = "mcspi1_fck",
1589         .ops            = &clkops_omap2_dflt_wait,
1590         .parent         = &core_48m_fck,
1591         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1592         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1593         .recalc         = &followparent_recalc,
1594         .clkdm_name     = "core_l4_clkdm",
1595 };
1596
1597 static struct clk uart2_fck = {
1598         .name           = "uart2_fck",
1599         .ops            = &clkops_omap2_dflt_wait,
1600         .parent         = &core_48m_fck,
1601         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1602         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1603         .clkdm_name     = "core_l4_clkdm",
1604         .recalc         = &followparent_recalc,
1605 };
1606
1607 static struct clk uart1_fck = {
1608         .name           = "uart1_fck",
1609         .ops            = &clkops_omap2_dflt_wait,
1610         .parent         = &core_48m_fck,
1611         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1612         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1613         .clkdm_name     = "core_l4_clkdm",
1614         .recalc         = &followparent_recalc,
1615 };
1616
1617 static struct clk fshostusb_fck = {
1618         .name           = "fshostusb_fck",
1619         .ops            = &clkops_omap2_dflt_wait,
1620         .parent         = &core_48m_fck,
1621         .clkdm_name     = "core_l4_clkdm",
1622         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1623         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1624         .recalc         = &followparent_recalc,
1625 };
1626
1627 /* CORE_12M_FCK based clocks */
1628
1629 static struct clk core_12m_fck = {
1630         .name           = "core_12m_fck",
1631         .ops            = &clkops_null,
1632         .parent         = &omap_12m_fck,
1633         .clkdm_name     = "core_l4_clkdm",
1634         .recalc         = &followparent_recalc,
1635 };
1636
1637 static struct clk hdq_fck = {
1638         .name           = "hdq_fck",
1639         .ops            = &clkops_omap2_dflt_wait,
1640         .parent         = &core_12m_fck,
1641         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1642         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1643         .recalc         = &followparent_recalc,
1644 };
1645
1646 /* DPLL3-derived clock */
1647
1648 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1649         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1650         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1651         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
1652         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1653         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
1654         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
1655         { .div = 0 }
1656 };
1657
1658 static const struct clksel ssi_ssr_clksel[] = {
1659         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1660         { .parent = NULL }
1661 };
1662
1663 static struct clk ssi_ssr_fck_3430es1 = {
1664         .name           = "ssi_ssr_fck",
1665         .ops            = &clkops_omap2_dflt,
1666         .init           = &omap2_init_clksel_parent,
1667         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1668         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1669         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1670         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1671         .clksel         = ssi_ssr_clksel,
1672         .clkdm_name     = "core_l4_clkdm",
1673         .recalc         = &omap2_clksel_recalc,
1674 };
1675
1676 static struct clk ssi_ssr_fck_3430es2 = {
1677         .name           = "ssi_ssr_fck",
1678         .ops            = &clkops_omap3430es2_ssi_wait,
1679         .init           = &omap2_init_clksel_parent,
1680         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1681         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1682         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1683         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1684         .clksel         = ssi_ssr_clksel,
1685         .clkdm_name     = "core_l4_clkdm",
1686         .recalc         = &omap2_clksel_recalc,
1687 };
1688
1689 static struct clk ssi_sst_fck_3430es1 = {
1690         .name           = "ssi_sst_fck",
1691         .ops            = &clkops_null,
1692         .parent         = &ssi_ssr_fck_3430es1,
1693         .fixed_div      = 2,
1694         .recalc         = &omap_fixed_divisor_recalc,
1695 };
1696
1697 static struct clk ssi_sst_fck_3430es2 = {
1698         .name           = "ssi_sst_fck",
1699         .ops            = &clkops_null,
1700         .parent         = &ssi_ssr_fck_3430es2,
1701         .fixed_div      = 2,
1702         .recalc         = &omap_fixed_divisor_recalc,
1703 };
1704
1705
1706
1707 /* CORE_L3_ICK based clocks */
1708
1709 /*
1710  * XXX must add clk_enable/clk_disable for these if standard code won't
1711  * handle it
1712  */
1713 static struct clk core_l3_ick = {
1714         .name           = "core_l3_ick",
1715         .ops            = &clkops_null,
1716         .parent         = &l3_ick,
1717         .clkdm_name     = "core_l3_clkdm",
1718         .recalc         = &followparent_recalc,
1719 };
1720
1721 static struct clk hsotgusb_ick_3430es1 = {
1722         .name           = "hsotgusb_ick",
1723         .ops            = &clkops_omap2_iclk_dflt,
1724         .parent         = &core_l3_ick,
1725         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1726         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1727         .clkdm_name     = "core_l3_clkdm",
1728         .recalc         = &followparent_recalc,
1729 };
1730
1731 static struct clk hsotgusb_ick_3430es2 = {
1732         .name           = "hsotgusb_ick",
1733         .ops            = &clkops_omap3430es2_iclk_hsotgusb_wait,
1734         .parent         = &core_l3_ick,
1735         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1736         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1737         .clkdm_name     = "core_l3_clkdm",
1738         .recalc         = &followparent_recalc,
1739 };
1740
1741 /* This interface clock does not have a CM_AUTOIDLE bit */
1742 static struct clk sdrc_ick = {
1743         .name           = "sdrc_ick",
1744         .ops            = &clkops_omap2_dflt_wait,
1745         .parent         = &core_l3_ick,
1746         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1747         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1748         .flags          = ENABLE_ON_INIT,
1749         .clkdm_name     = "core_l3_clkdm",
1750         .recalc         = &followparent_recalc,
1751 };
1752
1753 static struct clk gpmc_fck = {
1754         .name           = "gpmc_fck",
1755         .ops            = &clkops_null,
1756         .parent         = &core_l3_ick,
1757         .flags          = ENABLE_ON_INIT, /* huh? */
1758         .clkdm_name     = "core_l3_clkdm",
1759         .recalc         = &followparent_recalc,
1760 };
1761
1762 /* SECURITY_L3_ICK based clocks */
1763
1764 static struct clk security_l3_ick = {
1765         .name           = "security_l3_ick",
1766         .ops            = &clkops_null,
1767         .parent         = &l3_ick,
1768         .recalc         = &followparent_recalc,
1769 };
1770
1771 static struct clk pka_ick = {
1772         .name           = "pka_ick",
1773         .ops            = &clkops_omap2_iclk_dflt_wait,
1774         .parent         = &security_l3_ick,
1775         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1776         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1777         .recalc         = &followparent_recalc,
1778 };
1779
1780 /* CORE_L4_ICK based clocks */
1781
1782 static struct clk core_l4_ick = {
1783         .name           = "core_l4_ick",
1784         .ops            = &clkops_null,
1785         .parent         = &l4_ick,
1786         .clkdm_name     = "core_l4_clkdm",
1787         .recalc         = &followparent_recalc,
1788 };
1789
1790 static struct clk usbtll_ick = {
1791         .name           = "usbtll_ick",
1792         .ops            = &clkops_omap2_iclk_dflt_wait,
1793         .parent         = &core_l4_ick,
1794         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1795         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1796         .clkdm_name     = "core_l4_clkdm",
1797         .recalc         = &followparent_recalc,
1798 };
1799
1800 static struct clk mmchs3_ick = {
1801         .name           = "mmchs3_ick",
1802         .ops            = &clkops_omap2_iclk_dflt_wait,
1803         .parent         = &core_l4_ick,
1804         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1805         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1806         .clkdm_name     = "core_l4_clkdm",
1807         .recalc         = &followparent_recalc,
1808 };
1809
1810 /* Intersystem Communication Registers - chassis mode only */
1811 static struct clk icr_ick = {
1812         .name           = "icr_ick",
1813         .ops            = &clkops_omap2_iclk_dflt_wait,
1814         .parent         = &core_l4_ick,
1815         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1816         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1817         .clkdm_name     = "core_l4_clkdm",
1818         .recalc         = &followparent_recalc,
1819 };
1820
1821 static struct clk aes2_ick = {
1822         .name           = "aes2_ick",
1823         .ops            = &clkops_omap2_iclk_dflt_wait,
1824         .parent         = &core_l4_ick,
1825         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1826         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1827         .clkdm_name     = "core_l4_clkdm",
1828         .recalc         = &followparent_recalc,
1829 };
1830
1831 static struct clk sha12_ick = {
1832         .name           = "sha12_ick",
1833         .ops            = &clkops_omap2_iclk_dflt_wait,
1834         .parent         = &core_l4_ick,
1835         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1836         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1837         .clkdm_name     = "core_l4_clkdm",
1838         .recalc         = &followparent_recalc,
1839 };
1840
1841 static struct clk des2_ick = {
1842         .name           = "des2_ick",
1843         .ops            = &clkops_omap2_iclk_dflt_wait,
1844         .parent         = &core_l4_ick,
1845         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1846         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1847         .clkdm_name     = "core_l4_clkdm",
1848         .recalc         = &followparent_recalc,
1849 };
1850
1851 static struct clk mmchs2_ick = {
1852         .name           = "mmchs2_ick",
1853         .ops            = &clkops_omap2_iclk_dflt_wait,
1854         .parent         = &core_l4_ick,
1855         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1856         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1857         .clkdm_name     = "core_l4_clkdm",
1858         .recalc         = &followparent_recalc,
1859 };
1860
1861 static struct clk mmchs1_ick = {
1862         .name           = "mmchs1_ick",
1863         .ops            = &clkops_omap2_iclk_dflt_wait,
1864         .parent         = &core_l4_ick,
1865         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1866         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1867         .clkdm_name     = "core_l4_clkdm",
1868         .recalc         = &followparent_recalc,
1869 };
1870
1871 static struct clk mspro_ick = {
1872         .name           = "mspro_ick",
1873         .ops            = &clkops_omap2_iclk_dflt_wait,
1874         .parent         = &core_l4_ick,
1875         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1876         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1877         .clkdm_name     = "core_l4_clkdm",
1878         .recalc         = &followparent_recalc,
1879 };
1880
1881 static struct clk hdq_ick = {
1882         .name           = "hdq_ick",
1883         .ops            = &clkops_omap2_iclk_dflt_wait,
1884         .parent         = &core_l4_ick,
1885         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1886         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1887         .clkdm_name     = "core_l4_clkdm",
1888         .recalc         = &followparent_recalc,
1889 };
1890
1891 static struct clk mcspi4_ick = {
1892         .name           = "mcspi4_ick",
1893         .ops            = &clkops_omap2_iclk_dflt_wait,
1894         .parent         = &core_l4_ick,
1895         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1896         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1897         .clkdm_name     = "core_l4_clkdm",
1898         .recalc         = &followparent_recalc,
1899 };
1900
1901 static struct clk mcspi3_ick = {
1902         .name           = "mcspi3_ick",
1903         .ops            = &clkops_omap2_iclk_dflt_wait,
1904         .parent         = &core_l4_ick,
1905         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1906         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1907         .clkdm_name     = "core_l4_clkdm",
1908         .recalc         = &followparent_recalc,
1909 };
1910
1911 static struct clk mcspi2_ick = {
1912         .name           = "mcspi2_ick",
1913         .ops            = &clkops_omap2_iclk_dflt_wait,
1914         .parent         = &core_l4_ick,
1915         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1916         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1917         .clkdm_name     = "core_l4_clkdm",
1918         .recalc         = &followparent_recalc,
1919 };
1920
1921 static struct clk mcspi1_ick = {
1922         .name           = "mcspi1_ick",
1923         .ops            = &clkops_omap2_iclk_dflt_wait,
1924         .parent         = &core_l4_ick,
1925         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1926         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1927         .clkdm_name     = "core_l4_clkdm",
1928         .recalc         = &followparent_recalc,
1929 };
1930
1931 static struct clk i2c3_ick = {
1932         .name           = "i2c3_ick",
1933         .ops            = &clkops_omap2_iclk_dflt_wait,
1934         .parent         = &core_l4_ick,
1935         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1936         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1937         .clkdm_name     = "core_l4_clkdm",
1938         .recalc         = &followparent_recalc,
1939 };
1940
1941 static struct clk i2c2_ick = {
1942         .name           = "i2c2_ick",
1943         .ops            = &clkops_omap2_iclk_dflt_wait,
1944         .parent         = &core_l4_ick,
1945         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1946         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1947         .clkdm_name     = "core_l4_clkdm",
1948         .recalc         = &followparent_recalc,
1949 };
1950
1951 static struct clk i2c1_ick = {
1952         .name           = "i2c1_ick",
1953         .ops            = &clkops_omap2_iclk_dflt_wait,
1954         .parent         = &core_l4_ick,
1955         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1956         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1957         .clkdm_name     = "core_l4_clkdm",
1958         .recalc         = &followparent_recalc,
1959 };
1960
1961 static struct clk uart2_ick = {
1962         .name           = "uart2_ick",
1963         .ops            = &clkops_omap2_iclk_dflt_wait,
1964         .parent         = &core_l4_ick,
1965         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1966         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1967         .clkdm_name     = "core_l4_clkdm",
1968         .recalc         = &followparent_recalc,
1969 };
1970
1971 static struct clk uart1_ick = {
1972         .name           = "uart1_ick",
1973         .ops            = &clkops_omap2_iclk_dflt_wait,
1974         .parent         = &core_l4_ick,
1975         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1976         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1977         .clkdm_name     = "core_l4_clkdm",
1978         .recalc         = &followparent_recalc,
1979 };
1980
1981 static struct clk gpt11_ick = {
1982         .name           = "gpt11_ick",
1983         .ops            = &clkops_omap2_iclk_dflt_wait,
1984         .parent         = &core_l4_ick,
1985         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1986         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1987         .clkdm_name     = "core_l4_clkdm",
1988         .recalc         = &followparent_recalc,
1989 };
1990
1991 static struct clk gpt10_ick = {
1992         .name           = "gpt10_ick",
1993         .ops            = &clkops_omap2_iclk_dflt_wait,
1994         .parent         = &core_l4_ick,
1995         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1996         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1997         .clkdm_name     = "core_l4_clkdm",
1998         .recalc         = &followparent_recalc,
1999 };
2000
2001 static struct clk mcbsp5_ick = {
2002         .name           = "mcbsp5_ick",
2003         .ops            = &clkops_omap2_iclk_dflt_wait,
2004         .parent         = &core_l4_ick,
2005         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2006         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2007         .clkdm_name     = "core_l4_clkdm",
2008         .recalc         = &followparent_recalc,
2009 };
2010
2011 static struct clk mcbsp1_ick = {
2012         .name           = "mcbsp1_ick",
2013         .ops            = &clkops_omap2_iclk_dflt_wait,
2014         .parent         = &core_l4_ick,
2015         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2016         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2017         .clkdm_name     = "core_l4_clkdm",
2018         .recalc         = &followparent_recalc,
2019 };
2020
2021 static struct clk fac_ick = {
2022         .name           = "fac_ick",
2023         .ops            = &clkops_omap2_iclk_dflt_wait,
2024         .parent         = &core_l4_ick,
2025         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2026         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2027         .clkdm_name     = "core_l4_clkdm",
2028         .recalc         = &followparent_recalc,
2029 };
2030
2031 static struct clk mailboxes_ick = {
2032         .name           = "mailboxes_ick",
2033         .ops            = &clkops_omap2_iclk_dflt_wait,
2034         .parent         = &core_l4_ick,
2035         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2036         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2037         .clkdm_name     = "core_l4_clkdm",
2038         .recalc         = &followparent_recalc,
2039 };
2040
2041 static struct clk omapctrl_ick = {
2042         .name           = "omapctrl_ick",
2043         .ops            = &clkops_omap2_iclk_dflt_wait,
2044         .parent         = &core_l4_ick,
2045         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2046         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2047         .flags          = ENABLE_ON_INIT,
2048         .clkdm_name     = "core_l4_clkdm",
2049         .recalc         = &followparent_recalc,
2050 };
2051
2052 /* SSI_L4_ICK based clocks */
2053
2054 static struct clk ssi_l4_ick = {
2055         .name           = "ssi_l4_ick",
2056         .ops            = &clkops_null,
2057         .parent         = &l4_ick,
2058         .clkdm_name     = "core_l4_clkdm",
2059         .recalc         = &followparent_recalc,
2060 };
2061
2062 static struct clk ssi_ick_3430es1 = {
2063         .name           = "ssi_ick",
2064         .ops            = &clkops_omap2_iclk_dflt,
2065         .parent         = &ssi_l4_ick,
2066         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2067         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2068         .clkdm_name     = "core_l4_clkdm",
2069         .recalc         = &followparent_recalc,
2070 };
2071
2072 static struct clk ssi_ick_3430es2 = {
2073         .name           = "ssi_ick",
2074         .ops            = &clkops_omap3430es2_iclk_ssi_wait,
2075         .parent         = &ssi_l4_ick,
2076         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2077         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2078         .clkdm_name     = "core_l4_clkdm",
2079         .recalc         = &followparent_recalc,
2080 };
2081
2082 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2083  * but l4_ick makes more sense to me */
2084
2085 static const struct clksel usb_l4_clksel[] = {
2086         { .parent = &l4_ick, .rates = div2_rates },
2087         { .parent = NULL },
2088 };
2089
2090 static struct clk usb_l4_ick = {
2091         .name           = "usb_l4_ick",
2092         .ops            = &clkops_omap2_iclk_dflt_wait,
2093         .parent         = &l4_ick,
2094         .init           = &omap2_init_clksel_parent,
2095         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2096         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2097         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2098         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2099         .clksel         = usb_l4_clksel,
2100         .clkdm_name     = "core_l4_clkdm",
2101         .recalc         = &omap2_clksel_recalc,
2102 };
2103
2104 /* SECURITY_L4_ICK2 based clocks */
2105
2106 static struct clk security_l4_ick2 = {
2107         .name           = "security_l4_ick2",
2108         .ops            = &clkops_null,
2109         .parent         = &l4_ick,
2110         .recalc         = &followparent_recalc,
2111 };
2112
2113 static struct clk aes1_ick = {
2114         .name           = "aes1_ick",
2115         .ops            = &clkops_omap2_iclk_dflt_wait,
2116         .parent         = &security_l4_ick2,
2117         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2118         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2119         .recalc         = &followparent_recalc,
2120 };
2121
2122 static struct clk rng_ick = {
2123         .name           = "rng_ick",
2124         .ops            = &clkops_omap2_iclk_dflt_wait,
2125         .parent         = &security_l4_ick2,
2126         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2127         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2128         .recalc         = &followparent_recalc,
2129 };
2130
2131 static struct clk sha11_ick = {
2132         .name           = "sha11_ick",
2133         .ops            = &clkops_omap2_iclk_dflt_wait,
2134         .parent         = &security_l4_ick2,
2135         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2136         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2137         .recalc         = &followparent_recalc,
2138 };
2139
2140 static struct clk des1_ick = {
2141         .name           = "des1_ick",
2142         .ops            = &clkops_omap2_iclk_dflt_wait,
2143         .parent         = &security_l4_ick2,
2144         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2145         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2146         .recalc         = &followparent_recalc,
2147 };
2148
2149 /* DSS */
2150 static struct clk dss1_alwon_fck_3430es1 = {
2151         .name           = "dss1_alwon_fck",
2152         .ops            = &clkops_omap2_dflt,
2153         .parent         = &dpll4_m4x2_ck,
2154         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2155         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2156         .clkdm_name     = "dss_clkdm",
2157         .recalc         = &followparent_recalc,
2158 };
2159
2160 static struct clk dss1_alwon_fck_3430es2 = {
2161         .name           = "dss1_alwon_fck",
2162         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2163         .parent         = &dpll4_m4x2_ck,
2164         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2165         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2166         .clkdm_name     = "dss_clkdm",
2167         .recalc         = &followparent_recalc,
2168 };
2169
2170 static struct clk dss_tv_fck = {
2171         .name           = "dss_tv_fck",
2172         .ops            = &clkops_omap2_dflt,
2173         .parent         = &omap_54m_fck,
2174         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2175         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2176         .clkdm_name     = "dss_clkdm",
2177         .recalc         = &followparent_recalc,
2178 };
2179
2180 static struct clk dss_96m_fck = {
2181         .name           = "dss_96m_fck",
2182         .ops            = &clkops_omap2_dflt,
2183         .parent         = &omap_96m_fck,
2184         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2185         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2186         .clkdm_name     = "dss_clkdm",
2187         .recalc         = &followparent_recalc,
2188 };
2189
2190 static struct clk dss2_alwon_fck = {
2191         .name           = "dss2_alwon_fck",
2192         .ops            = &clkops_omap2_dflt,
2193         .parent         = &sys_ck,
2194         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2195         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2196         .clkdm_name     = "dss_clkdm",
2197         .recalc         = &followparent_recalc,
2198 };
2199
2200 static struct clk dss_ick_3430es1 = {
2201         /* Handles both L3 and L4 clocks */
2202         .name           = "dss_ick",
2203         .ops            = &clkops_omap2_iclk_dflt,
2204         .parent         = &l4_ick,
2205         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2206         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2207         .clkdm_name     = "dss_clkdm",
2208         .recalc         = &followparent_recalc,
2209 };
2210
2211 static struct clk dss_ick_3430es2 = {
2212         /* Handles both L3 and L4 clocks */
2213         .name           = "dss_ick",
2214         .ops            = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2215         .parent         = &l4_ick,
2216         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2217         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2218         .clkdm_name     = "dss_clkdm",
2219         .recalc         = &followparent_recalc,
2220 };
2221
2222 /* CAM */
2223
2224 static struct clk cam_mclk = {
2225         .name           = "cam_mclk",
2226         .ops            = &clkops_omap2_dflt,
2227         .parent         = &dpll4_m5x2_ck,
2228         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2229         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2230         .clkdm_name     = "cam_clkdm",
2231         .recalc         = &followparent_recalc,
2232 };
2233
2234 static struct clk cam_ick = {
2235         /* Handles both L3 and L4 clocks */
2236         .name           = "cam_ick",
2237         .ops            = &clkops_omap2_iclk_dflt,
2238         .parent         = &l4_ick,
2239         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2240         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2241         .clkdm_name     = "cam_clkdm",
2242         .recalc         = &followparent_recalc,
2243 };
2244
2245 static struct clk csi2_96m_fck = {
2246         .name           = "csi2_96m_fck",
2247         .ops            = &clkops_omap2_dflt,
2248         .parent         = &core_96m_fck,
2249         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2250         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2251         .clkdm_name     = "cam_clkdm",
2252         .recalc         = &followparent_recalc,
2253 };
2254
2255 /* USBHOST - 3430ES2 only */
2256
2257 static struct clk usbhost_120m_fck = {
2258         .name           = "usbhost_120m_fck",
2259         .ops            = &clkops_omap2_dflt,
2260         .parent         = &dpll5_m2_ck,
2261         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2262         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2263         .clkdm_name     = "usbhost_clkdm",
2264         .recalc         = &followparent_recalc,
2265 };
2266
2267 static struct clk usbhost_48m_fck = {
2268         .name           = "usbhost_48m_fck",
2269         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2270         .parent         = &omap_48m_fck,
2271         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2272         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2273         .clkdm_name     = "usbhost_clkdm",
2274         .recalc         = &followparent_recalc,
2275 };
2276
2277 static struct clk usbhost_ick = {
2278         /* Handles both L3 and L4 clocks */
2279         .name           = "usbhost_ick",
2280         .ops            = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2281         .parent         = &l4_ick,
2282         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2283         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2284         .clkdm_name     = "usbhost_clkdm",
2285         .recalc         = &followparent_recalc,
2286 };
2287
2288 /* WKUP */
2289
2290 static const struct clksel_rate usim_96m_rates[] = {
2291         { .div = 2,  .val = 3, .flags = RATE_IN_3XXX },
2292         { .div = 4,  .val = 4, .flags = RATE_IN_3XXX },
2293         { .div = 8,  .val = 5, .flags = RATE_IN_3XXX },
2294         { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
2295         { .div = 0 },
2296 };
2297
2298 static const struct clksel_rate usim_120m_rates[] = {
2299         { .div = 4,  .val = 7,  .flags = RATE_IN_3XXX },
2300         { .div = 8,  .val = 8,  .flags = RATE_IN_3XXX },
2301         { .div = 16, .val = 9,  .flags = RATE_IN_3XXX },
2302         { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
2303         { .div = 0 },
2304 };
2305
2306 static const struct clksel usim_clksel[] = {
2307         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2308         { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
2309         { .parent = &sys_ck,            .rates = div2_rates },
2310         { .parent = NULL },
2311 };
2312
2313 /* 3430ES2 only */
2314 static struct clk usim_fck = {
2315         .name           = "usim_fck",
2316         .ops            = &clkops_omap2_dflt_wait,
2317         .init           = &omap2_init_clksel_parent,
2318         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2319         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2320         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2321         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2322         .clksel         = usim_clksel,
2323         .recalc         = &omap2_clksel_recalc,
2324 };
2325
2326 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2327 static struct clk gpt1_fck = {
2328         .name           = "gpt1_fck",
2329         .ops            = &clkops_omap2_dflt_wait,
2330         .init           = &omap2_init_clksel_parent,
2331         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2332         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2333         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2334         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2335         .clksel         = omap343x_gpt_clksel,
2336         .clkdm_name     = "wkup_clkdm",
2337         .recalc         = &omap2_clksel_recalc,
2338 };
2339
2340 static struct clk wkup_32k_fck = {
2341         .name           = "wkup_32k_fck",
2342         .ops            = &clkops_null,
2343         .parent         = &omap_32k_fck,
2344         .clkdm_name     = "wkup_clkdm",
2345         .recalc         = &followparent_recalc,
2346 };
2347
2348 static struct clk gpio1_dbck = {
2349         .name           = "gpio1_dbck",
2350         .ops            = &clkops_omap2_dflt,
2351         .parent         = &wkup_32k_fck,
2352         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2353         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2354         .clkdm_name     = "wkup_clkdm",
2355         .recalc         = &followparent_recalc,
2356 };
2357
2358 static struct clk wdt2_fck = {
2359         .name           = "wdt2_fck",
2360         .ops            = &clkops_omap2_dflt_wait,
2361         .parent         = &wkup_32k_fck,
2362         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2363         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2364         .clkdm_name     = "wkup_clkdm",
2365         .recalc         = &followparent_recalc,
2366 };
2367
2368 static struct clk wkup_l4_ick = {
2369         .name           = "wkup_l4_ick",
2370         .ops            = &clkops_null,
2371         .parent         = &sys_ck,
2372         .clkdm_name     = "wkup_clkdm",
2373         .recalc         = &followparent_recalc,
2374 };
2375
2376 /* 3430ES2 only */
2377 /* Never specifically named in the TRM, so we have to infer a likely name */
2378 static struct clk usim_ick = {
2379         .name           = "usim_ick",
2380         .ops            = &clkops_omap2_iclk_dflt_wait,
2381         .parent         = &wkup_l4_ick,
2382         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2383         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2384         .clkdm_name     = "wkup_clkdm",
2385         .recalc         = &followparent_recalc,
2386 };
2387
2388 static struct clk wdt2_ick = {
2389         .name           = "wdt2_ick",
2390         .ops            = &clkops_omap2_iclk_dflt_wait,
2391         .parent         = &wkup_l4_ick,
2392         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2393         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2394         .clkdm_name     = "wkup_clkdm",
2395         .recalc         = &followparent_recalc,
2396 };
2397
2398 static struct clk wdt1_ick = {
2399         .name           = "wdt1_ick",
2400         .ops            = &clkops_omap2_iclk_dflt_wait,
2401         .parent         = &wkup_l4_ick,
2402         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2403         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2404         .clkdm_name     = "wkup_clkdm",
2405         .recalc         = &followparent_recalc,
2406 };
2407
2408 static struct clk gpio1_ick = {
2409         .name           = "gpio1_ick",
2410         .ops            = &clkops_omap2_iclk_dflt_wait,
2411         .parent         = &wkup_l4_ick,
2412         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2413         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2414         .clkdm_name     = "wkup_clkdm",
2415         .recalc         = &followparent_recalc,
2416 };
2417
2418 static struct clk omap_32ksync_ick = {
2419         .name           = "omap_32ksync_ick",
2420         .ops            = &clkops_omap2_iclk_dflt_wait,
2421         .parent         = &wkup_l4_ick,
2422         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2423         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2424         .clkdm_name     = "wkup_clkdm",
2425         .recalc         = &followparent_recalc,
2426 };
2427
2428 /* XXX This clock no longer exists in 3430 TRM rev F */
2429 static struct clk gpt12_ick = {
2430         .name           = "gpt12_ick",
2431         .ops            = &clkops_omap2_iclk_dflt_wait,
2432         .parent         = &wkup_l4_ick,
2433         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2434         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2435         .clkdm_name     = "wkup_clkdm",
2436         .recalc         = &followparent_recalc,
2437 };
2438
2439 static struct clk gpt1_ick = {
2440         .name           = "gpt1_ick",
2441         .ops            = &clkops_omap2_iclk_dflt_wait,
2442         .parent         = &wkup_l4_ick,
2443         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2444         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2445         .clkdm_name     = "wkup_clkdm",
2446         .recalc         = &followparent_recalc,
2447 };
2448
2449
2450
2451 /* PER clock domain */
2452
2453 static struct clk per_96m_fck = {
2454         .name           = "per_96m_fck",
2455         .ops            = &clkops_null,
2456         .parent         = &omap_96m_alwon_fck,
2457         .clkdm_name     = "per_clkdm",
2458         .recalc         = &followparent_recalc,
2459 };
2460
2461 static struct clk per_48m_fck = {
2462         .name           = "per_48m_fck",
2463         .ops            = &clkops_null,
2464         .parent         = &omap_48m_fck,
2465         .clkdm_name     = "per_clkdm",
2466         .recalc         = &followparent_recalc,
2467 };
2468
2469 static struct clk uart3_fck = {
2470         .name           = "uart3_fck",
2471         .ops            = &clkops_omap2_dflt_wait,
2472         .parent         = &per_48m_fck,
2473         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2474         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2475         .clkdm_name     = "per_clkdm",
2476         .recalc         = &followparent_recalc,
2477 };
2478
2479 static struct clk uart4_fck = {
2480         .name           = "uart4_fck",
2481         .ops            = &clkops_omap2_dflt_wait,
2482         .parent         = &per_48m_fck,
2483         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2484         .enable_bit     = OMAP3630_EN_UART4_SHIFT,
2485         .clkdm_name     = "per_clkdm",
2486         .recalc         = &followparent_recalc,
2487 };
2488
2489 static struct clk gpt2_fck = {
2490         .name           = "gpt2_fck",
2491         .ops            = &clkops_omap2_dflt_wait,
2492         .init           = &omap2_init_clksel_parent,
2493         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2494         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2495         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2496         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2497         .clksel         = omap343x_gpt_clksel,
2498         .clkdm_name     = "per_clkdm",
2499         .recalc         = &omap2_clksel_recalc,
2500 };
2501
2502 static struct clk gpt3_fck = {
2503         .name           = "gpt3_fck",
2504         .ops            = &clkops_omap2_dflt_wait,
2505         .init           = &omap2_init_clksel_parent,
2506         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2507         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2508         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2509         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2510         .clksel         = omap343x_gpt_clksel,
2511         .clkdm_name     = "per_clkdm",
2512         .recalc         = &omap2_clksel_recalc,
2513 };
2514
2515 static struct clk gpt4_fck = {
2516         .name           = "gpt4_fck",
2517         .ops            = &clkops_omap2_dflt_wait,
2518         .init           = &omap2_init_clksel_parent,
2519         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2520         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2521         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2522         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2523         .clksel         = omap343x_gpt_clksel,
2524         .clkdm_name     = "per_clkdm",
2525         .recalc         = &omap2_clksel_recalc,
2526 };
2527
2528 static struct clk gpt5_fck = {
2529         .name           = "gpt5_fck",
2530         .ops            = &clkops_omap2_dflt_wait,
2531         .init           = &omap2_init_clksel_parent,
2532         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2533         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2534         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2535         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2536         .clksel         = omap343x_gpt_clksel,
2537         .clkdm_name     = "per_clkdm",
2538         .recalc         = &omap2_clksel_recalc,
2539 };
2540
2541 static struct clk gpt6_fck = {
2542         .name           = "gpt6_fck",
2543         .ops            = &clkops_omap2_dflt_wait,
2544         .init           = &omap2_init_clksel_parent,
2545         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2546         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2547         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2548         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2549         .clksel         = omap343x_gpt_clksel,
2550         .clkdm_name     = "per_clkdm",
2551         .recalc         = &omap2_clksel_recalc,
2552 };
2553
2554 static struct clk gpt7_fck = {
2555         .name           = "gpt7_fck",
2556         .ops            = &clkops_omap2_dflt_wait,
2557         .init           = &omap2_init_clksel_parent,
2558         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2559         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2560         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2561         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2562         .clksel         = omap343x_gpt_clksel,
2563         .clkdm_name     = "per_clkdm",
2564         .recalc         = &omap2_clksel_recalc,
2565 };
2566
2567 static struct clk gpt8_fck = {
2568         .name           = "gpt8_fck",
2569         .ops            = &clkops_omap2_dflt_wait,
2570         .init           = &omap2_init_clksel_parent,
2571         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2572         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2573         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2574         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2575         .clksel         = omap343x_gpt_clksel,
2576         .clkdm_name     = "per_clkdm",
2577         .recalc         = &omap2_clksel_recalc,
2578 };
2579
2580 static struct clk gpt9_fck = {
2581         .name           = "gpt9_fck",
2582         .ops            = &clkops_omap2_dflt_wait,
2583         .init           = &omap2_init_clksel_parent,
2584         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2585         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2586         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2587         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2588         .clksel         = omap343x_gpt_clksel,
2589         .clkdm_name     = "per_clkdm",
2590         .recalc         = &omap2_clksel_recalc,
2591 };
2592
2593 static struct clk per_32k_alwon_fck = {
2594         .name           = "per_32k_alwon_fck",
2595         .ops            = &clkops_null,
2596         .parent         = &omap_32k_fck,
2597         .clkdm_name     = "per_clkdm",
2598         .recalc         = &followparent_recalc,
2599 };
2600
2601 static struct clk gpio6_dbck = {
2602         .name           = "gpio6_dbck",
2603         .ops            = &clkops_omap2_dflt,
2604         .parent         = &per_32k_alwon_fck,
2605         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2606         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2607         .clkdm_name     = "per_clkdm",
2608         .recalc         = &followparent_recalc,
2609 };
2610
2611 static struct clk gpio5_dbck = {
2612         .name           = "gpio5_dbck",
2613         .ops            = &clkops_omap2_dflt,
2614         .parent         = &per_32k_alwon_fck,
2615         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2616         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2617         .clkdm_name     = "per_clkdm",
2618         .recalc         = &followparent_recalc,
2619 };
2620
2621 static struct clk gpio4_dbck = {
2622         .name           = "gpio4_dbck",
2623         .ops            = &clkops_omap2_dflt,
2624         .parent         = &per_32k_alwon_fck,
2625         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2626         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2627         .clkdm_name     = "per_clkdm",
2628         .recalc         = &followparent_recalc,
2629 };
2630
2631 static struct clk gpio3_dbck = {
2632         .name           = "gpio3_dbck",
2633         .ops            = &clkops_omap2_dflt,
2634         .parent         = &per_32k_alwon_fck,
2635         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2636         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2637         .clkdm_name     = "per_clkdm",
2638         .recalc         = &followparent_recalc,
2639 };
2640
2641 static struct clk gpio2_dbck = {
2642         .name           = "gpio2_dbck",
2643         .ops            = &clkops_omap2_dflt,
2644         .parent         = &per_32k_alwon_fck,
2645         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2646         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2647         .clkdm_name     = "per_clkdm",
2648         .recalc         = &followparent_recalc,
2649 };
2650
2651 static struct clk wdt3_fck = {
2652         .name           = "wdt3_fck",
2653         .ops            = &clkops_omap2_dflt_wait,
2654         .parent         = &per_32k_alwon_fck,
2655         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2656         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2657         .clkdm_name     = "per_clkdm",
2658         .recalc         = &followparent_recalc,
2659 };
2660
2661 static struct clk per_l4_ick = {
2662         .name           = "per_l4_ick",
2663         .ops            = &clkops_null,
2664         .parent         = &l4_ick,
2665         .clkdm_name     = "per_clkdm",
2666         .recalc         = &followparent_recalc,
2667 };
2668
2669 static struct clk gpio6_ick = {
2670         .name           = "gpio6_ick",
2671         .ops            = &clkops_omap2_iclk_dflt_wait,
2672         .parent         = &per_l4_ick,
2673         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2674         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2675         .clkdm_name     = "per_clkdm",
2676         .recalc         = &followparent_recalc,
2677 };
2678
2679 static struct clk gpio5_ick = {
2680         .name           = "gpio5_ick",
2681         .ops            = &clkops_omap2_iclk_dflt_wait,
2682         .parent         = &per_l4_ick,
2683         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2684         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2685         .clkdm_name     = "per_clkdm",
2686         .recalc         = &followparent_recalc,
2687 };
2688
2689 static struct clk gpio4_ick = {
2690         .name           = "gpio4_ick",
2691         .ops            = &clkops_omap2_iclk_dflt_wait,
2692         .parent         = &per_l4_ick,
2693         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2694         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2695         .clkdm_name     = "per_clkdm",
2696         .recalc         = &followparent_recalc,
2697 };
2698
2699 static struct clk gpio3_ick = {
2700         .name           = "gpio3_ick",
2701         .ops            = &clkops_omap2_iclk_dflt_wait,
2702         .parent         = &per_l4_ick,
2703         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2704         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2705         .clkdm_name     = "per_clkdm",
2706         .recalc         = &followparent_recalc,
2707 };
2708
2709 static struct clk gpio2_ick = {
2710         .name           = "gpio2_ick",
2711         .ops            = &clkops_omap2_iclk_dflt_wait,
2712         .parent         = &per_l4_ick,
2713         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2714         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2715         .clkdm_name     = "per_clkdm",
2716         .recalc         = &followparent_recalc,
2717 };
2718
2719 static struct clk wdt3_ick = {
2720         .name           = "wdt3_ick",
2721         .ops            = &clkops_omap2_iclk_dflt_wait,
2722         .parent         = &per_l4_ick,
2723         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2724         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2725         .clkdm_name     = "per_clkdm",
2726         .recalc         = &followparent_recalc,
2727 };
2728
2729 static struct clk uart3_ick = {
2730         .name           = "uart3_ick",
2731         .ops            = &clkops_omap2_iclk_dflt_wait,
2732         .parent         = &per_l4_ick,
2733         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2734         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2735         .clkdm_name     = "per_clkdm",
2736         .recalc         = &followparent_recalc,
2737 };
2738
2739 static struct clk uart4_ick = {
2740         .name           = "uart4_ick",
2741         .ops            = &clkops_omap2_iclk_dflt_wait,
2742         .parent         = &per_l4_ick,
2743         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2744         .enable_bit     = OMAP3630_EN_UART4_SHIFT,
2745         .clkdm_name     = "per_clkdm",
2746         .recalc         = &followparent_recalc,
2747 };
2748
2749 static struct clk gpt9_ick = {
2750         .name           = "gpt9_ick",
2751         .ops            = &clkops_omap2_iclk_dflt_wait,
2752         .parent         = &per_l4_ick,
2753         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2754         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2755         .clkdm_name     = "per_clkdm",
2756         .recalc         = &followparent_recalc,
2757 };
2758
2759 static struct clk gpt8_ick = {
2760         .name           = "gpt8_ick",
2761         .ops            = &clkops_omap2_iclk_dflt_wait,
2762         .parent         = &per_l4_ick,
2763         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2764         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2765         .clkdm_name     = "per_clkdm",
2766         .recalc         = &followparent_recalc,
2767 };
2768
2769 static struct clk gpt7_ick = {
2770         .name           = "gpt7_ick",
2771         .ops            = &clkops_omap2_iclk_dflt_wait,
2772         .parent         = &per_l4_ick,
2773         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2774         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2775         .clkdm_name     = "per_clkdm",
2776         .recalc         = &followparent_recalc,
2777 };
2778
2779 static struct clk gpt6_ick = {
2780         .name           = "gpt6_ick",
2781         .ops            = &clkops_omap2_iclk_dflt_wait,
2782         .parent         = &per_l4_ick,
2783         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2784         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2785         .clkdm_name     = "per_clkdm",
2786         .recalc         = &followparent_recalc,
2787 };
2788
2789 static struct clk gpt5_ick = {
2790         .name           = "gpt5_ick",
2791         .ops            = &clkops_omap2_iclk_dflt_wait,
2792         .parent         = &per_l4_ick,
2793         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2794         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2795         .clkdm_name     = "per_clkdm",
2796         .recalc         = &followparent_recalc,
2797 };
2798
2799 static struct clk gpt4_ick = {
2800         .name           = "gpt4_ick",
2801         .ops            = &clkops_omap2_iclk_dflt_wait,
2802         .parent         = &per_l4_ick,
2803         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2804         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2805         .clkdm_name     = "per_clkdm",
2806         .recalc         = &followparent_recalc,
2807 };
2808
2809 static struct clk gpt3_ick = {
2810         .name           = "gpt3_ick",
2811         .ops            = &clkops_omap2_iclk_dflt_wait,
2812         .parent         = &per_l4_ick,
2813         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2814         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2815         .clkdm_name     = "per_clkdm",
2816         .recalc         = &followparent_recalc,
2817 };
2818
2819 static struct clk gpt2_ick = {
2820         .name           = "gpt2_ick",
2821         .ops            = &clkops_omap2_iclk_dflt_wait,
2822         .parent         = &per_l4_ick,
2823         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2824         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2825         .clkdm_name     = "per_clkdm",
2826         .recalc         = &followparent_recalc,
2827 };
2828
2829 static struct clk mcbsp2_ick = {
2830         .name           = "mcbsp2_ick",
2831         .ops            = &clkops_omap2_iclk_dflt_wait,
2832         .parent         = &per_l4_ick,
2833         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2834         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2835         .clkdm_name     = "per_clkdm",
2836         .recalc         = &followparent_recalc,
2837 };
2838
2839 static struct clk mcbsp3_ick = {
2840         .name           = "mcbsp3_ick",
2841         .ops            = &clkops_omap2_iclk_dflt_wait,
2842         .parent         = &per_l4_ick,
2843         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2844         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2845         .clkdm_name     = "per_clkdm",
2846         .recalc         = &followparent_recalc,
2847 };
2848
2849 static struct clk mcbsp4_ick = {
2850         .name           = "mcbsp4_ick",
2851         .ops            = &clkops_omap2_iclk_dflt_wait,
2852         .parent         = &per_l4_ick,
2853         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2854         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2855         .clkdm_name     = "per_clkdm",
2856         .recalc         = &followparent_recalc,
2857 };
2858
2859 static const struct clksel mcbsp_234_clksel[] = {
2860         { .parent = &per_96m_fck,  .rates = common_mcbsp_96m_rates },
2861         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2862         { .parent = NULL }
2863 };
2864
2865 static struct clk mcbsp2_fck = {
2866         .name           = "mcbsp2_fck",
2867         .ops            = &clkops_omap2_dflt_wait,
2868         .init           = &omap2_init_clksel_parent,
2869         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2870         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2871         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2872         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2873         .clksel         = mcbsp_234_clksel,
2874         .clkdm_name     = "per_clkdm",
2875         .recalc         = &omap2_clksel_recalc,
2876 };
2877
2878 static struct clk mcbsp3_fck = {
2879         .name           = "mcbsp3_fck",
2880         .ops            = &clkops_omap2_dflt_wait,
2881         .init           = &omap2_init_clksel_parent,
2882         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2883         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2884         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2885         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2886         .clksel         = mcbsp_234_clksel,
2887         .clkdm_name     = "per_clkdm",
2888         .recalc         = &omap2_clksel_recalc,
2889 };
2890
2891 static struct clk mcbsp4_fck = {
2892         .name           = "mcbsp4_fck",
2893         .ops            = &clkops_omap2_dflt_wait,
2894         .init           = &omap2_init_clksel_parent,
2895         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2896         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2897         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2898         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2899         .clksel         = mcbsp_234_clksel,
2900         .clkdm_name     = "per_clkdm",
2901         .recalc         = &omap2_clksel_recalc,
2902 };
2903
2904 /* EMU clocks */
2905
2906 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2907
2908 static const struct clksel_rate emu_src_sys_rates[] = {
2909         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2910         { .div = 0 },
2911 };
2912
2913 static const struct clksel_rate emu_src_core_rates[] = {
2914         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2915         { .div = 0 },
2916 };
2917
2918 static const struct clksel_rate emu_src_per_rates[] = {
2919         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
2920         { .div = 0 },
2921 };
2922
2923 static const struct clksel_rate emu_src_mpu_rates[] = {
2924         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2925         { .div = 0 },
2926 };
2927
2928 static const struct clksel emu_src_clksel[] = {
2929         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2930         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2931         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2932         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2933         { .parent = NULL },
2934 };
2935
2936 /*
2937  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2938  * to switch the source of some of the EMU clocks.
2939  * XXX Are there CLKEN bits for these EMU clks?
2940  */
2941 static struct clk emu_src_ck = {
2942         .name           = "emu_src_ck",
2943         .ops            = &clkops_null,
2944         .init           = &omap2_init_clksel_parent,
2945         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2946         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2947         .clksel         = emu_src_clksel,
2948         .clkdm_name     = "emu_clkdm",
2949         .recalc         = &omap2_clksel_recalc,
2950 };
2951
2952 static const struct clksel_rate pclk_emu_rates[] = {
2953         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2954         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2955         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2956         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2957         { .div = 0 },
2958 };
2959
2960 static const struct clksel pclk_emu_clksel[] = {
2961         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2962         { .parent = NULL },
2963 };
2964
2965 static struct clk pclk_fck = {
2966         .name           = "pclk_fck",
2967         .ops            = &clkops_null,
2968         .init           = &omap2_init_clksel_parent,
2969         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2970         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2971         .clksel         = pclk_emu_clksel,
2972         .clkdm_name     = "emu_clkdm",
2973         .recalc         = &omap2_clksel_recalc,
2974 };
2975
2976 static const struct clksel_rate pclkx2_emu_rates[] = {
2977         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2978         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2979         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2980         { .div = 0 },
2981 };
2982
2983 static const struct clksel pclkx2_emu_clksel[] = {
2984         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2985         { .parent = NULL },
2986 };
2987
2988 static struct clk pclkx2_fck = {
2989         .name           = "pclkx2_fck",
2990         .ops            = &clkops_null,
2991         .init           = &omap2_init_clksel_parent,
2992         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2993         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2994         .clksel         = pclkx2_emu_clksel,
2995         .clkdm_name     = "emu_clkdm",
2996         .recalc         = &omap2_clksel_recalc,
2997 };
2998
2999 static const struct clksel atclk_emu_clksel[] = {
3000         { .parent = &emu_src_ck, .rates = div2_rates },
3001         { .parent = NULL },
3002 };
3003
3004 static struct clk atclk_fck = {
3005         .name           = "atclk_fck",
3006         .ops            = &clkops_null,
3007         .init           = &omap2_init_clksel_parent,
3008         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3009         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3010         .clksel         = atclk_emu_clksel,
3011         .clkdm_name     = "emu_clkdm",
3012         .recalc         = &omap2_clksel_recalc,
3013 };
3014
3015 static struct clk traceclk_src_fck = {
3016         .name           = "traceclk_src_fck",
3017         .ops            = &clkops_null,
3018         .init           = &omap2_init_clksel_parent,
3019         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3020         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3021         .clksel         = emu_src_clksel,
3022         .clkdm_name     = "emu_clkdm",
3023         .recalc         = &omap2_clksel_recalc,
3024 };
3025
3026 static const struct clksel_rate traceclk_rates[] = {
3027         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3028         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3029         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3030         { .div = 0 },
3031 };
3032
3033 static const struct clksel traceclk_clksel[] = {
3034         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3035         { .parent = NULL },
3036 };
3037
3038 static struct clk traceclk_fck = {
3039         .name           = "traceclk_fck",
3040         .ops            = &clkops_null,
3041         .init           = &omap2_init_clksel_parent,
3042         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3043         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3044         .clksel         = traceclk_clksel,
3045         .clkdm_name     = "emu_clkdm",
3046         .recalc         = &omap2_clksel_recalc,
3047 };
3048
3049 /* SR clocks */
3050
3051 /* SmartReflex fclk (VDD1) */
3052 static struct clk sr1_fck = {
3053         .name           = "sr1_fck",
3054         .ops            = &clkops_omap2_dflt_wait,
3055         .parent         = &sys_ck,
3056         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3057         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3058         .clkdm_name     = "wkup_clkdm",
3059         .recalc         = &followparent_recalc,
3060 };
3061
3062 /* SmartReflex fclk (VDD2) */
3063 static struct clk sr2_fck = {
3064         .name           = "sr2_fck",
3065         .ops            = &clkops_omap2_dflt_wait,
3066         .parent         = &sys_ck,
3067         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3068         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3069         .clkdm_name     = "wkup_clkdm",
3070         .recalc         = &followparent_recalc,
3071 };
3072
3073 static struct clk sr_l4_ick = {
3074         .name           = "sr_l4_ick",
3075         .ops            = &clkops_null, /* RMK: missing? */
3076         .parent         = &l4_ick,
3077         .clkdm_name     = "core_l4_clkdm",
3078         .recalc         = &followparent_recalc,
3079 };
3080
3081 /* SECURE_32K_FCK clocks */
3082
3083 static struct clk gpt12_fck = {
3084         .name           = "gpt12_fck",
3085         .ops            = &clkops_null,
3086         .parent         = &secure_32k_fck,
3087         .clkdm_name     = "wkup_clkdm",
3088         .recalc         = &followparent_recalc,
3089 };
3090
3091 static struct clk wdt1_fck = {
3092         .name           = "wdt1_fck",
3093         .ops            = &clkops_null,
3094         .parent         = &secure_32k_fck,
3095         .clkdm_name     = "wkup_clkdm",
3096         .recalc         = &followparent_recalc,
3097 };
3098
3099 /* Clocks for AM35XX */
3100 static struct clk ipss_ick = {
3101         .name           = "ipss_ick",
3102         .ops            = &clkops_am35xx_ipss_wait,
3103         .parent         = &core_l3_ick,
3104         .clkdm_name     = "core_l3_clkdm",
3105         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3106         .enable_bit     = AM35XX_EN_IPSS_SHIFT,
3107         .recalc         = &followparent_recalc,
3108 };
3109
3110 static struct clk emac_ick = {
3111         .name           = "emac_ick",
3112         .ops            = &clkops_am35xx_ipss_module_wait,
3113         .parent         = &ipss_ick,
3114         .clkdm_name     = "core_l3_clkdm",
3115         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3116         .enable_bit     = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
3117         .recalc         = &followparent_recalc,
3118 };
3119
3120 static struct clk rmii_ck = {
3121         .name           = "rmii_ck",
3122         .ops            = &clkops_null,
3123         .rate           = 50000000,
3124 };
3125
3126 static struct clk emac_fck = {
3127         .name           = "emac_fck",
3128         .ops            = &clkops_omap2_dflt,
3129         .parent         = &rmii_ck,
3130         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3131         .enable_bit     = AM35XX_CPGMAC_FCLK_SHIFT,
3132         .recalc         = &followparent_recalc,
3133 };
3134
3135 static struct clk hsotgusb_ick_am35xx = {
3136         .name           = "hsotgusb_ick",
3137         .ops            = &clkops_am35xx_ipss_module_wait,
3138         .parent         = &ipss_ick,
3139         .clkdm_name     = "core_l3_clkdm",
3140         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3141         .enable_bit     = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
3142         .recalc         = &followparent_recalc,
3143 };
3144
3145 static struct clk hsotgusb_fck_am35xx = {
3146         .name           = "hsotgusb_fck",
3147         .ops            = &clkops_omap2_dflt,
3148         .parent         = &sys_ck,
3149         .clkdm_name     = "core_l3_clkdm",
3150         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3151         .enable_bit     = AM35XX_USBOTG_FCLK_SHIFT,
3152         .recalc         = &followparent_recalc,
3153 };
3154
3155 static struct clk hecc_ck = {
3156         .name           = "hecc_ck",
3157         .ops            = &clkops_am35xx_ipss_module_wait,
3158         .parent         = &sys_ck,
3159         .clkdm_name     = "core_l3_clkdm",
3160         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3161         .enable_bit     = AM35XX_HECC_VBUSP_CLK_SHIFT,
3162         .recalc         = &followparent_recalc,
3163 };
3164
3165 static struct clk vpfe_ick = {
3166         .name           = "vpfe_ick",
3167         .ops            = &clkops_am35xx_ipss_module_wait,
3168         .parent         = &ipss_ick,
3169         .clkdm_name     = "core_l3_clkdm",
3170         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3171         .enable_bit     = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3172         .recalc         = &followparent_recalc,
3173 };
3174
3175 static struct clk pclk_ck = {
3176         .name           = "pclk_ck",
3177         .ops            = &clkops_null,
3178         .rate           = 27000000,
3179 };
3180
3181 static struct clk vpfe_fck = {
3182         .name           = "vpfe_fck",
3183         .ops            = &clkops_omap2_dflt,
3184         .parent         = &pclk_ck,
3185         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3186         .enable_bit     = AM35XX_VPFE_FCLK_SHIFT,
3187         .recalc         = &followparent_recalc,
3188 };
3189
3190 /*
3191  * The UART1/2 functional clock acts as the functional
3192  * clock for UART4. No separate fclk control available.
3193  */
3194 static struct clk uart4_ick_am35xx = {
3195         .name           = "uart4_ick",
3196         .ops            = &clkops_omap2_iclk_dflt_wait,
3197         .parent         = &core_l4_ick,
3198         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3199         .enable_bit     = AM35XX_EN_UART4_SHIFT,
3200         .clkdm_name     = "core_l4_clkdm",
3201         .recalc         = &followparent_recalc,
3202 };
3203
3204 static struct clk dummy_apb_pclk = {
3205         .name           = "apb_pclk",
3206         .ops            = &clkops_null,
3207 };
3208
3209 /*
3210  * clkdev
3211  */
3212
3213 /* XXX At some point we should rename this file to clock3xxx_data.c */
3214 static struct omap_clk omap3xxx_clks[] = {
3215         CLK(NULL,       "apb_pclk",     &dummy_apb_pclk,        CK_3XXX),
3216         CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
3217         CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
3218         CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),
3219         CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX  | CK_36XX),
3220         CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
3221         CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_3XXX),
3222         CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3223         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
3224         CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
3225         CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
3226         CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
3227         CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
3228         CLK("omap-mcbsp.3",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
3229         CLK("omap-mcbsp.4",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
3230         CLK("omap-mcbsp.5",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
3231         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
3232         CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_3XXX),
3233         CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
3234         CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_3XXX),
3235         CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
3236         CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_34XX | CK_36XX),
3237         CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_34XX | CK_36XX),
3238         CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_3XXX),
3239         CLK(NULL,       "core_ck",      &core_ck,       CK_3XXX),
3240         CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_3XXX),
3241         CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_3XXX),
3242         CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3243         CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_3XXX),
3244         CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3245         CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3246         CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_3XXX),
3247         CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_3XXX),
3248         CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
3249         CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3250         CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_3XXX),
3251         CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_3XXX),
3252         CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_3XXX),
3253         CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_3XXX),
3254         CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_3XXX),
3255         CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_3XXX),
3256         CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3257         CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_3XXX),
3258         CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3259         CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_3XXX),
3260         CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3261         CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_3XXX),
3262         CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3263         CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
3264         CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3265         CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3266         CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3267         CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3268         CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3269         CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_3XXX),
3270         CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_3XXX),
3271         CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_3XXX),
3272         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
3273         CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
3274         CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3275         CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_34XX | CK_36XX),
3276         CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_34XX | CK_36XX),
3277         CLK(NULL,       "l3_ick",       &l3_ick,        CK_3XXX),
3278         CLK(NULL,       "l4_ick",       &l4_ick,        CK_3XXX),
3279         CLK(NULL,       "rm_ick",       &rm_ick,        CK_3XXX),
3280         CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
3281         CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
3282         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
3283         CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
3284         CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
3285         CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
3286         CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
3287         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
3288         CLK(NULL,       "modem_fck",    &modem_fck,     CK_34XX | CK_36XX),
3289         CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_34XX | CK_36XX),
3290         CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_34XX | CK_36XX),
3291         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_3XXX),
3292         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_3XXX),
3293         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3294         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3295         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3296         CLK("usbhs-omap.0",     "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3297         CLK("omap-mcbsp.1",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
3298         CLK("omap-mcbsp.5",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
3299         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
3300         CLK(NULL,       "mmchs3_fck",   &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3301         CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_3XXX),
3302         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_34XX | CK_36XX),
3303         CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_3XXX),
3304         CLK(NULL,       "i2c3_fck",     &i2c3_fck,      CK_3XXX),
3305         CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_3XXX),
3306         CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_3XXX),
3307         CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_3XXX),
3308         CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_3XXX),
3309         CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_3XXX),
3310         CLK(NULL,       "mcspi4_fck",   &mcspi4_fck,    CK_3XXX),
3311         CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_3XXX),
3312         CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_3XXX),
3313         CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_3XXX),
3314         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_3XXX),
3315         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_3XXX),
3316         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3317         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
3318         CLK("omap_hdq.0",       "fck",  &hdq_fck,       CK_3XXX),
3319         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
3320         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
3321         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
3322         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
3323         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
3324         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
3325         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
3326         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
3327         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
3328         CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
3329         CLK(NULL,       "pka_ick",      &pka_ick,       CK_34XX | CK_36XX),
3330         CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
3331         CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3332         CLK("usbhs-omap.0",     "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3333         CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3334         CLK(NULL,       "icr_ick",      &icr_ick,       CK_34XX | CK_36XX),
3335         CLK("omap-aes", "ick",  &aes2_ick,      CK_34XX | CK_36XX),
3336         CLK("omap-sham",        "ick",  &sha12_ick,     CK_34XX | CK_36XX),
3337         CLK(NULL,       "des2_ick",     &des2_ick,      CK_34XX | CK_36XX),
3338         CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick,    CK_3XXX),
3339         CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick,    CK_3XXX),
3340         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_34XX | CK_36XX),
3341         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
3342         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
3343         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
3344         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
3345         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
3346         CLK("omap_i2c.3", "ick",        &i2c3_ick,      CK_3XXX),
3347         CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_3XXX),
3348         CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_3XXX),
3349         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
3350         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
3351         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
3352         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_3XXX),
3353         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
3354         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
3355         CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
3356         CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
3357         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
3358         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_34XX | CK_36XX),
3359         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
3360         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2PLUS | CK_36XX),
3361         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
3362         CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
3363         CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_34XX | CK_36XX),
3364         CLK("omap_rng", "ick",          &rng_ick,       CK_34XX | CK_36XX),
3365         CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_34XX | CK_36XX),
3366         CLK(NULL,       "des1_ick",     &des1_ick,      CK_34XX | CK_36XX),
3367         CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es1, CK_3430ES1),
3368         CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3369         CLK(NULL,       "dss_tv_fck",   &dss_tv_fck,    CK_3XXX),
3370         CLK(NULL,       "dss_96m_fck",  &dss_96m_fck,   CK_3XXX),
3371         CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck, CK_3XXX),
3372         CLK("omapdss_dss",      "ick",          &dss_ick_3430es1,       CK_3430ES1),
3373         CLK("omapdss_dss",      "ick",          &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3374         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_34XX | CK_36XX),
3375         CLK(NULL,       "cam_ick",      &cam_ick,       CK_34XX | CK_36XX),
3376         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_34XX | CK_36XX),
3377         CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3378         CLK("usbhs-omap.0",     "hs_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3379         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3380         CLK("usbhs-omap.0",     "fs_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3381         CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3382         CLK("usbhs-omap.0",     "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3383         CLK("usbhs-omap.0",     "utmi_p1_gfclk",        &dummy_ck,      CK_3XXX),
3384         CLK("usbhs-omap.0",     "utmi_p2_gfclk",        &dummy_ck,      CK_3XXX),
3385         CLK("usbhs-omap.0",     "xclk60mhsp1_ck",       &dummy_ck,      CK_3XXX),
3386         CLK("usbhs-omap.0",     "xclk60mhsp2_ck",       &dummy_ck,      CK_3XXX),
3387         CLK("usbhs-omap.0",     "usb_host_hs_utmi_p1_clk",      &dummy_ck,      CK_3XXX),
3388         CLK("usbhs-omap.0",     "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
3389         CLK("usbhs-omap.0",     "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
3390         CLK("usbhs-omap.0",     "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
3391         CLK("usbhs-omap.0",     "init_60m_fclk",        &dummy_ck,      CK_3XXX),
3392         CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
3393         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
3394         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
3395         CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_3XXX),
3396         CLK(NULL,       "wdt2_fck",             &wdt2_fck,      CK_3XXX),
3397         CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_34XX | CK_36XX),
3398         CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2PLUS | CK_36XX),
3399         CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
3400         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
3401         CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
3402         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3403         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_3XXX),
3404         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_3XXX),
3405         CLK("omap-mcbsp.2",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
3406         CLK("omap-mcbsp.3",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
3407         CLK("omap-mcbsp.4",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
3408         CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_3XXX),
3409         CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
3410         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
3411         CLK(NULL,       "uart4_fck",    &uart4_fck,     CK_36XX),
3412         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
3413         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
3414         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
3415         CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_3XXX),
3416         CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_3XXX),
3417         CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_3XXX),
3418         CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_3XXX),
3419         CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_3XXX),
3420         CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3421         CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_3XXX),
3422         CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_3XXX),
3423         CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_3XXX),
3424         CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_3XXX),
3425         CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_3XXX),
3426         CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_3XXX),
3427         CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_3XXX),
3428         CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_3XXX),
3429         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_3XXX),
3430         CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_3XXX),
3431         CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_3XXX),
3432         CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_3XXX),
3433         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_3XXX),
3434         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_3XXX),
3435         CLK(NULL,       "uart4_ick",    &uart4_ick,     CK_36XX),
3436         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_3XXX),
3437         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_3XXX),
3438         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_3XXX),
3439         CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_3XXX),
3440         CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_3XXX),
3441         CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_3XXX),
3442         CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_3XXX),
3443         CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_3XXX),
3444         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_3XXX),
3445         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_3XXX),
3446         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_3XXX),
3447         CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_3XXX),
3448         CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_3XXX),
3449         CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_3XXX),
3450         CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_3XXX),
3451         CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_3XXX),
3452         CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_3XXX),
3453         CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_3XXX),
3454         CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3455         CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_3XXX),
3456         CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_34XX | CK_36XX),
3457         CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_34XX | CK_36XX),
3458         CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_34XX | CK_36XX),
3459         CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3460         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_3XXX),
3461         CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_3XXX),
3462         CLK(NULL,       "ipss_ick",     &ipss_ick,      CK_AM35XX),
3463         CLK(NULL,       "rmii_ck",      &rmii_ck,       CK_AM35XX),
3464         CLK(NULL,       "pclk_ck",      &pclk_ck,       CK_AM35XX),
3465         CLK("davinci_emac",     "emac_clk",     &emac_ick,      CK_AM35XX),
3466         CLK("davinci_emac",     "phy_clk",      &emac_fck,      CK_AM35XX),
3467         CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
3468         CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
3469         CLK("musb-am35x",       "ick",          &hsotgusb_ick_am35xx,   CK_AM35XX),
3470         CLK("musb-am35x",       "fck",          &hsotgusb_fck_am35xx,   CK_AM35XX),
3471         CLK(NULL,       "hecc_ck",      &hecc_ck,       CK_AM35XX),
3472         CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
3473         CLK("omap_timer.1",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3474         CLK("omap_timer.2",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3475         CLK("omap_timer.3",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3476         CLK("omap_timer.4",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3477         CLK("omap_timer.5",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3478         CLK("omap_timer.6",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3479         CLK("omap_timer.7",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3480         CLK("omap_timer.8",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3481         CLK("omap_timer.9",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3482         CLK("omap_timer.10",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
3483         CLK("omap_timer.11",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
3484         CLK("omap_timer.12",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
3485         CLK("omap_timer.1",     "sys_ck",       &sys_ck,        CK_3XXX),
3486         CLK("omap_timer.2",     "sys_ck",       &sys_ck,        CK_3XXX),
3487         CLK("omap_timer.3",     "sys_ck",       &sys_ck,        CK_3XXX),
3488         CLK("omap_timer.4",     "sys_ck",       &sys_ck,        CK_3XXX),
3489         CLK("omap_timer.5",     "sys_ck",       &sys_ck,        CK_3XXX),
3490         CLK("omap_timer.6",     "sys_ck",       &sys_ck,        CK_3XXX),
3491         CLK("omap_timer.7",     "sys_ck",       &sys_ck,        CK_3XXX),
3492         CLK("omap_timer.8",     "sys_ck",       &sys_ck,        CK_3XXX),
3493         CLK("omap_timer.9",     "sys_ck",       &sys_ck,        CK_3XXX),
3494         CLK("omap_timer.10",    "sys_ck",       &sys_ck,        CK_3XXX),
3495         CLK("omap_timer.11",    "sys_ck",       &sys_ck,        CK_3XXX),
3496         CLK("omap_timer.12",    "sys_ck",       &sys_ck,        CK_3XXX),
3497 };
3498
3499
3500 int __init omap3xxx_clk_init(void)
3501 {
3502         struct omap_clk *c;
3503         u32 cpu_clkflg = 0;
3504
3505         /*
3506          * 3505 must be tested before 3517, since 3517 returns true
3507          * for both AM3517 chips and AM3517 family chips, which
3508          * includes 3505.  Unfortunately there's no obvious family
3509          * test for 3517/3505 :-(
3510          */
3511         if (cpu_is_omap3505()) {
3512                 cpu_mask = RATE_IN_34XX;
3513                 cpu_clkflg = CK_3505;
3514         } else if (cpu_is_omap3517()) {
3515                 cpu_mask = RATE_IN_34XX;
3516                 cpu_clkflg = CK_3517;
3517         } else if (cpu_is_omap3505()) {
3518                 cpu_mask = RATE_IN_34XX;
3519                 cpu_clkflg = CK_3505;
3520         } else if (cpu_is_omap3630()) {
3521                 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3522                 cpu_clkflg = CK_36XX;
3523         } else if (cpu_is_ti816x()) {
3524                 cpu_mask = RATE_IN_TI816X;
3525                 cpu_clkflg = CK_TI816X;
3526         } else if (cpu_is_omap34xx()) {
3527                 if (omap_rev() == OMAP3430_REV_ES1_0) {
3528                         cpu_mask = RATE_IN_3430ES1;
3529                         cpu_clkflg = CK_3430ES1;
3530                 } else {
3531                         /*
3532                          * Assume that anything that we haven't matched yet
3533                          * has 3430ES2-type clocks.
3534                          */
3535                         cpu_mask = RATE_IN_3430ES2PLUS;
3536                         cpu_clkflg = CK_3430ES2PLUS;
3537                 }
3538         } else {
3539                 WARN(1, "clock: could not identify OMAP3 variant\n");
3540         }
3541
3542         if (omap3_has_192mhz_clk())
3543                 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3544
3545         if (cpu_is_omap3630()) {
3546                 /*
3547                  * XXX This type of dynamic rewriting of the clock tree is
3548                  * deprecated and should be revised soon.
3549                  *
3550                  * For 3630: override clkops_omap2_dflt_wait for the
3551                  * clocks affected from PWRDN reset Limitation
3552                  */
3553                 dpll3_m3x2_ck.ops =
3554                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3555                 dpll4_m2x2_ck.ops =
3556                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3557                 dpll4_m3x2_ck.ops =
3558                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3559                 dpll4_m4x2_ck.ops =
3560                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3561                 dpll4_m5x2_ck.ops =
3562                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3563                 dpll4_m6x2_ck.ops =
3564                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3565         }
3566
3567         /*
3568          * XXX This type of dynamic rewriting of the clock tree is
3569          * deprecated and should be revised soon.
3570          */
3571         if (cpu_is_omap3630())
3572                 dpll4_dd = dpll4_dd_3630;
3573         else
3574                 dpll4_dd = dpll4_dd_34xx;
3575
3576         clk_init(&omap2_clk_functions);
3577
3578         for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3579              c++)
3580                 clk_preinit(c->lk.clk);
3581
3582         for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3583              c++)
3584                 if (c->cpu & cpu_clkflg) {
3585                         clkdev_add(&c->lk);
3586                         clk_register(c->lk.clk);
3587                         omap2_init_clk_clkdm(c->lk.clk);
3588                 }
3589
3590         /* Disable autoidle on all clocks; let the PM code enable it later */
3591         omap_clk_disable_autoidle_all();
3592
3593         recalculate_root_clocks();
3594
3595         pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3596                 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3597                 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3598
3599         /*
3600          * Only enable those clocks we will need, let the drivers
3601          * enable other clocks as necessary
3602          */
3603         clk_enable_init_clocks();
3604
3605         /*
3606          * Lock DPLL5 -- here only until other device init code can
3607          * handle this
3608          */
3609         if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
3610                 omap3_clk_lock_dpll5();
3611
3612         /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3613         sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3614         arm_fck_p = clk_get(NULL, "arm_fck");
3615
3616         return 0;
3617 }