arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  21
  22 #include <mach/control.h>
  23
  24 #include "clock.h"
  25 #include "cm.h"
  26 #include "cm-regbits-34xx.h"
  27 #include "prm.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 #define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
  31
  32 static unsigned long omap3_dpll_recalc(struct clk *clk);
  33 static unsigned long omap3_clkoutx2_recalc(struct clk *clk);
  34 static void omap3_dpll_allow_idle(struct clk *clk);
  35 static void omap3_dpll_deny_idle(struct clk *clk);
  36 static u32 omap3_dpll_autoidle_read(struct clk *clk);
  37 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  38 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
  39 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
  40
  41 /* Maximum DPLL multiplier, divider values for OMAP3 */
  42 #define OMAP3_MAX_DPLL_MULT             2048
  43 #define OMAP3_MAX_DPLL_DIV              128
  44
  45 /*
  46  * DPLL1 supplies clock to the MPU.
  47  * DPLL2 supplies clock to the IVA2.
  48  * DPLL3 supplies CORE domain clocks.
  49  * DPLL4 supplies peripheral clocks.
  50  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  51  */
  52
  53 /* Forward declarations for DPLL bypass clocks */
  54 static struct clk dpll1_fck;
  55 static struct clk dpll2_fck;
  56
  57 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  58 #define DPLL_LOW_POWER_STOP             0x1
  59 #define DPLL_LOW_POWER_BYPASS           0x5
  60 #define DPLL_LOCKED                     0x7
  61
  62 /* PRM CLOCKS */
  63
  64 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  65 static struct clk omap_32k_fck = {
  66         .name           = "omap_32k_fck",
  67         .ops            = &clkops_null,
  68         .rate           = 32768,
  69         .flags          = RATE_FIXED,
  70 };
  71
  72 static struct clk secure_32k_fck = {
  73         .name           = "secure_32k_fck",
  74         .ops            = &clkops_null,
  75         .rate           = 32768,
  76         .flags          = RATE_FIXED,
  77 };
  78
  79 /* Virtual source clocks for osc_sys_ck */
  80 static struct clk virt_12m_ck = {
  81         .name           = "virt_12m_ck",
  82         .ops            = &clkops_null,
  83         .rate           = 12000000,
  84         .flags          = RATE_FIXED,
  85 };
  86
  87 static struct clk virt_13m_ck = {
  88         .name           = "virt_13m_ck",
  89         .ops            = &clkops_null,
  90         .rate           = 13000000,
  91         .flags          = RATE_FIXED,
  92 };
  93
  94 static struct clk virt_16_8m_ck = {
  95         .name           = "virt_16_8m_ck",
  96         .ops            = &clkops_null,
  97         .rate           = 16800000,
  98         .flags          = RATE_FIXED,
  99 };
 100
 101 static struct clk virt_19_2m_ck = {
 102         .name           = "virt_19_2m_ck",
 103         .ops            = &clkops_null,
 104         .rate           = 19200000,
 105         .flags          = RATE_FIXED,
 106 };
 107
 108 static struct clk virt_26m_ck = {
 109         .name           = "virt_26m_ck",
 110         .ops            = &clkops_null,
 111         .rate           = 26000000,
 112         .flags          = RATE_FIXED,
 113 };
 114
 115 static struct clk virt_38_4m_ck = {
 116         .name           = "virt_38_4m_ck",
 117         .ops            = &clkops_null,
 118         .rate           = 38400000,
 119         .flags          = RATE_FIXED,
 120 };
 121
 122 static const struct clksel_rate osc_sys_12m_rates[] = {
 123         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 124         { .div = 0 }
 125 };
 126
 127 static const struct clksel_rate osc_sys_13m_rates[] = {
 128         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 129         { .div = 0 }
 130 };
 131
 132 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 133         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 134         { .div = 0 }
 135 };
 136
 137 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 138         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 139         { .div = 0 }
 140 };
 141
 142 static const struct clksel_rate osc_sys_26m_rates[] = {
 143         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 144         { .div = 0 }
 145 };
 146
 147 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 148         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 149         { .div = 0 }
 150 };
 151
 152 static const struct clksel osc_sys_clksel[] = {
 153         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 154         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 155         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 156         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 157         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 158         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 159         { .parent = NULL },
 160 };
 161
 162 /* Oscillator clock */
 163 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 164 static struct clk osc_sys_ck = {
 165         .name           = "osc_sys_ck",
 166         .ops            = &clkops_null,
 167         .init           = &omap2_init_clksel_parent,
 168         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 169         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 170         .clksel         = osc_sys_clksel,
 171         /* REVISIT: deal with autoextclkmode? */
 172         .flags          = RATE_FIXED,
 173         .recalc         = &omap2_clksel_recalc,
 174 };
 175
 176 static const struct clksel_rate div2_rates[] = {
 177         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 178         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 179         { .div = 0 }
 180 };
 181
 182 static const struct clksel sys_clksel[] = {
 183         { .parent = &osc_sys_ck, .rates = div2_rates },
 184         { .parent = NULL }
 185 };
 186
 187 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 188 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 189 static struct clk sys_ck = {
 190         .name           = "sys_ck",
 191         .ops            = &clkops_null,
 192         .parent         = &osc_sys_ck,
 193         .init           = &omap2_init_clksel_parent,
 194         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 195         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 196         .clksel         = sys_clksel,
 197         .recalc         = &omap2_clksel_recalc,
 198 };
 199
 200 static struct clk sys_altclk = {
 201         .name           = "sys_altclk",
 202         .ops            = &clkops_null,
 203 };
 204
 205 /* Optional external clock input for some McBSPs */
 206 static struct clk mcbsp_clks = {
 207         .name           = "mcbsp_clks",
 208         .ops            = &clkops_null,
 209 };
 210
 211 /* PRM EXTERNAL CLOCK OUTPUT */
 212
 213 static struct clk sys_clkout1 = {
 214         .name           = "sys_clkout1",
 215         .ops            = &clkops_omap2_dflt,
 216         .parent         = &osc_sys_ck,
 217         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 218         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 219         .recalc         = &followparent_recalc,
 220 };
 221
 222 /* DPLLS */
 223
 224 /* CM CLOCKS */
 225
 226 static const struct clksel_rate div16_dpll_rates[] = {
 227         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 228         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 229         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 230         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 231         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 232         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 233         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 234         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 235         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 236         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 237         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 238         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 239         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 240         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 241         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 242         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 243         { .div = 0 }
 244 };
 245
 246 /* DPLL1 */
 247 /* MPU clock source */
 248 /* Type: DPLL */
 249 static struct dpll_data dpll1_dd = {
 250         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 251         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 252         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 253         .clk_bypass     = &dpll1_fck,
 254         .clk_ref        = &sys_ck,
 255         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 256         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 257         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 258         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 259         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 260         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 261         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 262         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 263         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 264         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 265         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 266         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 267         .min_divider    = 1,
 268         .max_divider    = OMAP3_MAX_DPLL_DIV,
 269         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 270 };
 271
 272 static struct clk dpll1_ck = {
 273         .name           = "dpll1_ck",
 274         .ops            = &clkops_null,
 275         .parent         = &sys_ck,
 276         .dpll_data      = &dpll1_dd,
 277         .round_rate     = &omap2_dpll_round_rate,
 278         .set_rate       = &omap3_noncore_dpll_set_rate,
 279         .clkdm_name     = "dpll1_clkdm",
 280         .recalc         = &omap3_dpll_recalc,
 281 };
 282
 283 /*
 284  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 285  * DPLL isn't bypassed.
 286  */
 287 static struct clk dpll1_x2_ck = {
 288         .name           = "dpll1_x2_ck",
 289         .ops            = &clkops_null,
 290         .parent         = &dpll1_ck,
 291         .clkdm_name     = "dpll1_clkdm",
 292         .recalc         = &omap3_clkoutx2_recalc,
 293 };
 294
 295 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 296 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 297         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 298         { .parent = NULL }
 299 };
 300
 301 /*
 302  * Does not exist in the TRM - needed to separate the M2 divider from
 303  * bypass selection in mpu_ck
 304  */
 305 static struct clk dpll1_x2m2_ck = {
 306         .name           = "dpll1_x2m2_ck",
 307         .ops            = &clkops_null,
 308         .parent         = &dpll1_x2_ck,
 309         .init           = &omap2_init_clksel_parent,
 310         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 311         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 312         .clksel         = div16_dpll1_x2m2_clksel,
 313         .clkdm_name     = "dpll1_clkdm",
 314         .recalc         = &omap2_clksel_recalc,
 315 };
 316
 317 /* DPLL2 */
 318 /* IVA2 clock source */
 319 /* Type: DPLL */
 320
 321 static struct dpll_data dpll2_dd = {
 322         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 323         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 324         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 325         .clk_bypass     = &dpll2_fck,
 326         .clk_ref        = &sys_ck,
 327         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 328         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 329         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 330         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 331                                 (1 << DPLL_LOW_POWER_BYPASS),
 332         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 333         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 334         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 335         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 336         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 337         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 338         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 339         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 340         .min_divider    = 1,
 341         .max_divider    = OMAP3_MAX_DPLL_DIV,
 342         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 343 };
 344
 345 static struct clk dpll2_ck = {
 346         .name           = "dpll2_ck",
 347         .ops            = &clkops_noncore_dpll_ops,
 348         .parent         = &sys_ck,
 349         .dpll_data      = &dpll2_dd,
 350         .round_rate     = &omap2_dpll_round_rate,
 351         .set_rate       = &omap3_noncore_dpll_set_rate,
 352         .clkdm_name     = "dpll2_clkdm",
 353         .recalc         = &omap3_dpll_recalc,
 354 };
 355
 356 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 357         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 358         { .parent = NULL }
 359 };
 360
 361 /*
 362  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 363  * or CLKOUTX2. CLKOUT seems most plausible.
 364  */
 365 static struct clk dpll2_m2_ck = {
 366         .name           = "dpll2_m2_ck",
 367         .ops            = &clkops_null,
 368         .parent         = &dpll2_ck,
 369         .init           = &omap2_init_clksel_parent,
 370         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 371                                           OMAP3430_CM_CLKSEL2_PLL),
 372         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 373         .clksel         = div16_dpll2_m2x2_clksel,
 374         .clkdm_name     = "dpll2_clkdm",
 375         .recalc         = &omap2_clksel_recalc,
 376 };
 377
 378 /*
 379  * DPLL3
 380  * Source clock for all interfaces and for some device fclks
 381  * REVISIT: Also supports fast relock bypass - not included below
 382  */
 383 static struct dpll_data dpll3_dd = {
 384         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 385         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 386         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 387         .clk_bypass     = &sys_ck,
 388         .clk_ref        = &sys_ck,
 389         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 390         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 391         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 392         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 393         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 394         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 395         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 396         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 397         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 398         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 399         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 400         .min_divider    = 1,
 401         .max_divider    = OMAP3_MAX_DPLL_DIV,
 402         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 403 };
 404
 405 static struct clk dpll3_ck = {
 406         .name           = "dpll3_ck",
 407         .ops            = &clkops_null,
 408         .parent         = &sys_ck,
 409         .dpll_data      = &dpll3_dd,
 410         .round_rate     = &omap2_dpll_round_rate,
 411         .clkdm_name     = "dpll3_clkdm",
 412         .recalc         = &omap3_dpll_recalc,
 413 };
 414
 415 /*
 416  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 417  * DPLL isn't bypassed
 418  */
 419 static struct clk dpll3_x2_ck = {
 420         .name           = "dpll3_x2_ck",
 421         .ops            = &clkops_null,
 422         .parent         = &dpll3_ck,
 423         .clkdm_name     = "dpll3_clkdm",
 424         .recalc         = &omap3_clkoutx2_recalc,
 425 };
 426
 427 static const struct clksel_rate div31_dpll3_rates[] = {
 428         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 429         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 430         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 431         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 432         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 433         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 434         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 435         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 436         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 437         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 438         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 439         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 440         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 441         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 442         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 443         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 444         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 445         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 446         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 447         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 448         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 449         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 450         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 451         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 452         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 453         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 454         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 455         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 456         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 457         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 458         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 459         { .div = 0 },
 460 };
 461
 462 static const struct clksel div31_dpll3m2_clksel[] = {
 463         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 464         { .parent = NULL }
 465 };
 466
 467 /* DPLL3 output M2 - primary control point for CORE speed */
 468 static struct clk dpll3_m2_ck = {
 469         .name           = "dpll3_m2_ck",
 470         .ops            = &clkops_null,
 471         .parent         = &dpll3_ck,
 472         .init           = &omap2_init_clksel_parent,
 473         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 474         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 475         .clksel         = div31_dpll3m2_clksel,
 476         .clkdm_name     = "dpll3_clkdm",
 477         .round_rate     = &omap2_clksel_round_rate,
 478         .set_rate       = &omap3_core_dpll_m2_set_rate,
 479         .recalc         = &omap2_clksel_recalc,
 480 };
 481
 482 static struct clk core_ck = {
 483         .name           = "core_ck",
 484         .ops            = &clkops_null,
 485         .parent         = &dpll3_m2_ck,
 486         .recalc         = &followparent_recalc,
 487 };
 488
 489 static struct clk dpll3_m2x2_ck = {
 490         .name           = "dpll3_m2x2_ck",
 491         .ops            = &clkops_null,
 492         .parent         = &dpll3_x2_ck,
 493         .clkdm_name     = "dpll3_clkdm",
 494         .recalc         = &followparent_recalc,
 495 };
 496
 497 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 498 static const struct clksel div16_dpll3_clksel[] = {
 499         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 500         { .parent = NULL }
 501 };
 502
 503 /* This virtual clock is the source for dpll3_m3x2_ck */
 504 static struct clk dpll3_m3_ck = {
 505         .name           = "dpll3_m3_ck",
 506         .ops            = &clkops_null,
 507         .parent         = &dpll3_ck,
 508         .init           = &omap2_init_clksel_parent,
 509         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 510         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 511         .clksel         = div16_dpll3_clksel,
 512         .clkdm_name     = "dpll3_clkdm",
 513         .recalc         = &omap2_clksel_recalc,
 514 };
 515
 516 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 517 static struct clk dpll3_m3x2_ck = {
 518         .name           = "dpll3_m3x2_ck",
 519         .ops            = &clkops_omap2_dflt_wait,
 520         .parent         = &dpll3_m3_ck,
 521         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 522         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 523         .flags          = INVERT_ENABLE,
 524         .clkdm_name     = "dpll3_clkdm",
 525         .recalc         = &omap3_clkoutx2_recalc,
 526 };
 527
 528 static struct clk emu_core_alwon_ck = {
 529         .name           = "emu_core_alwon_ck",
 530         .ops            = &clkops_null,
 531         .parent         = &dpll3_m3x2_ck,
 532         .clkdm_name     = "dpll3_clkdm",
 533         .recalc         = &followparent_recalc,
 534 };
 535
 536 /* DPLL4 */
 537 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 538 /* Type: DPLL */
 539 static struct dpll_data dpll4_dd = {
 540         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 541         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 542         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 543         .clk_bypass     = &sys_ck,
 544         .clk_ref        = &sys_ck,
 545         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 546         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 547         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 548         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 549         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 550         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 551         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 552         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 553         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 554         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 555         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 556         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 557         .min_divider    = 1,
 558         .max_divider    = OMAP3_MAX_DPLL_DIV,
 559         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 560 };
 561
 562 static struct clk dpll4_ck = {
 563         .name           = "dpll4_ck",
 564         .ops            = &clkops_noncore_dpll_ops,
 565         .parent         = &sys_ck,
 566         .dpll_data      = &dpll4_dd,
 567         .round_rate     = &omap2_dpll_round_rate,
 568         .set_rate       = &omap3_dpll4_set_rate,
 569         .clkdm_name     = "dpll4_clkdm",
 570         .recalc         = &omap3_dpll_recalc,
 571 };
 572
 573 /*
 574  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 575  * DPLL isn't bypassed --
 576  * XXX does this serve any downstream clocks?
 577  */
 578 static struct clk dpll4_x2_ck = {
 579         .name           = "dpll4_x2_ck",
 580         .ops            = &clkops_null,
 581         .parent         = &dpll4_ck,
 582         .clkdm_name     = "dpll4_clkdm",
 583         .recalc         = &omap3_clkoutx2_recalc,
 584 };
 585
 586 static const struct clksel div16_dpll4_clksel[] = {
 587         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 588         { .parent = NULL }
 589 };
 590
 591 /* This virtual clock is the source for dpll4_m2x2_ck */
 592 static struct clk dpll4_m2_ck = {
 593         .name           = "dpll4_m2_ck",
 594         .ops            = &clkops_null,
 595         .parent         = &dpll4_ck,
 596         .init           = &omap2_init_clksel_parent,
 597         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 598         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 599         .clksel         = div16_dpll4_clksel,
 600         .clkdm_name     = "dpll4_clkdm",
 601         .recalc         = &omap2_clksel_recalc,
 602 };
 603
 604 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 605 static struct clk dpll4_m2x2_ck = {
 606         .name           = "dpll4_m2x2_ck",
 607         .ops            = &clkops_omap2_dflt_wait,
 608         .parent         = &dpll4_m2_ck,
 609         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 610         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 611         .flags          = INVERT_ENABLE,
 612         .clkdm_name     = "dpll4_clkdm",
 613         .recalc         = &omap3_clkoutx2_recalc,
 614 };
 615
 616 /*
 617  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 618  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 619  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 620  * CM_96K_(F)CLK.
 621  */
 622 static struct clk omap_96m_alwon_fck = {
 623         .name           = "omap_96m_alwon_fck",
 624         .ops            = &clkops_null,
 625         .parent         = &dpll4_m2x2_ck,
 626         .recalc         = &followparent_recalc,
 627 };
 628
 629 static struct clk cm_96m_fck = {
 630         .name           = "cm_96m_fck",
 631         .ops            = &clkops_null,
 632         .parent         = &omap_96m_alwon_fck,
 633         .recalc         = &followparent_recalc,
 634 };
 635
 636 static const struct clksel_rate omap_96m_dpll_rates[] = {
 637         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 638         { .div = 0 }
 639 };
 640
 641 static const struct clksel_rate omap_96m_sys_rates[] = {
 642         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 643         { .div = 0 }
 644 };
 645
 646 static const struct clksel omap_96m_fck_clksel[] = {
 647         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 648         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 649         { .parent = NULL }
 650 };
 651
 652 static struct clk omap_96m_fck = {
 653         .name           = "omap_96m_fck",
 654         .ops            = &clkops_null,
 655         .parent         = &sys_ck,
 656         .init           = &omap2_init_clksel_parent,
 657         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 658         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 659         .clksel         = omap_96m_fck_clksel,
 660         .recalc         = &omap2_clksel_recalc,
 661 };
 662
 663 /* This virtual clock is the source for dpll4_m3x2_ck */
 664 static struct clk dpll4_m3_ck = {
 665         .name           = "dpll4_m3_ck",
 666         .ops            = &clkops_null,
 667         .parent         = &dpll4_ck,
 668         .init           = &omap2_init_clksel_parent,
 669         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 670         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 671         .clksel         = div16_dpll4_clksel,
 672         .clkdm_name     = "dpll4_clkdm",
 673         .recalc         = &omap2_clksel_recalc,
 674 };
 675
 676 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 677 static struct clk dpll4_m3x2_ck = {
 678         .name           = "dpll4_m3x2_ck",
 679         .ops            = &clkops_omap2_dflt_wait,
 680         .parent         = &dpll4_m3_ck,
 681         .init           = &omap2_init_clksel_parent,
 682         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 683         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 684         .flags          = INVERT_ENABLE,
 685         .clkdm_name     = "dpll4_clkdm",
 686         .recalc         = &omap3_clkoutx2_recalc,
 687 };
 688
 689 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 690         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 691         { .div = 0 }
 692 };
 693
 694 static const struct clksel_rate omap_54m_alt_rates[] = {
 695         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 696         { .div = 0 }
 697 };
 698
 699 static const struct clksel omap_54m_clksel[] = {
 700         { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 701         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 702         { .parent = NULL }
 703 };
 704
 705 static struct clk omap_54m_fck = {
 706         .name           = "omap_54m_fck",
 707         .ops            = &clkops_null,
 708         .init           = &omap2_init_clksel_parent,
 709         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 710         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 711         .clksel         = omap_54m_clksel,
 712         .recalc         = &omap2_clksel_recalc,
 713 };
 714
 715 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 716         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 717         { .div = 0 }
 718 };
 719
 720 static const struct clksel_rate omap_48m_alt_rates[] = {
 721         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 722         { .div = 0 }
 723 };
 724
 725 static const struct clksel omap_48m_clksel[] = {
 726         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 727         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 728         { .parent = NULL }
 729 };
 730
 731 static struct clk omap_48m_fck = {
 732         .name           = "omap_48m_fck",
 733         .ops            = &clkops_null,
 734         .init           = &omap2_init_clksel_parent,
 735         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 736         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 737         .clksel         = omap_48m_clksel,
 738         .recalc         = &omap2_clksel_recalc,
 739 };
 740
 741 static struct clk omap_12m_fck = {
 742         .name           = "omap_12m_fck",
 743         .ops            = &clkops_null,
 744         .parent         = &omap_48m_fck,
 745         .fixed_div      = 4,
 746         .recalc         = &omap2_fixed_divisor_recalc,
 747 };
 748
 749 /* This virstual clock is the source for dpll4_m4x2_ck */
 750 static struct clk dpll4_m4_ck = {
 751         .name           = "dpll4_m4_ck",
 752         .ops            = &clkops_null,
 753         .parent         = &dpll4_ck,
 754         .init           = &omap2_init_clksel_parent,
 755         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 756         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 757         .clksel         = div16_dpll4_clksel,
 758         .clkdm_name     = "dpll4_clkdm",
 759         .recalc         = &omap2_clksel_recalc,
 760         .set_rate       = &omap2_clksel_set_rate,
 761         .round_rate     = &omap2_clksel_round_rate,
 762 };
 763
 764 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 765 static struct clk dpll4_m4x2_ck = {
 766         .name           = "dpll4_m4x2_ck",
 767         .ops            = &clkops_omap2_dflt_wait,
 768         .parent         = &dpll4_m4_ck,
 769         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 770         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 771         .flags          = INVERT_ENABLE,
 772         .clkdm_name     = "dpll4_clkdm",
 773         .recalc         = &omap3_clkoutx2_recalc,
 774 };
 775
 776 /* This virtual clock is the source for dpll4_m5x2_ck */
 777 static struct clk dpll4_m5_ck = {
 778         .name           = "dpll4_m5_ck",
 779         .ops            = &clkops_null,
 780         .parent         = &dpll4_ck,
 781         .init           = &omap2_init_clksel_parent,
 782         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 783         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 784         .clksel         = div16_dpll4_clksel,
 785         .clkdm_name     = "dpll4_clkdm",
 786         .recalc         = &omap2_clksel_recalc,
 787 };
 788
 789 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 790 static struct clk dpll4_m5x2_ck = {
 791         .name           = "dpll4_m5x2_ck",
 792         .ops            = &clkops_omap2_dflt_wait,
 793         .parent         = &dpll4_m5_ck,
 794         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 795         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 796         .flags          = INVERT_ENABLE,
 797         .clkdm_name     = "dpll4_clkdm",
 798         .recalc         = &omap3_clkoutx2_recalc,
 799 };
 800
 801 /* This virtual clock is the source for dpll4_m6x2_ck */
 802 static struct clk dpll4_m6_ck = {
 803         .name           = "dpll4_m6_ck",
 804         .ops            = &clkops_null,
 805         .parent         = &dpll4_ck,
 806         .init           = &omap2_init_clksel_parent,
 807         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 808         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 809         .clksel         = div16_dpll4_clksel,
 810         .clkdm_name     = "dpll4_clkdm",
 811         .recalc         = &omap2_clksel_recalc,
 812 };
 813
 814 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 815 static struct clk dpll4_m6x2_ck = {
 816         .name           = "dpll4_m6x2_ck",
 817         .ops            = &clkops_omap2_dflt_wait,
 818         .parent         = &dpll4_m6_ck,
 819         .init           = &omap2_init_clksel_parent,
 820         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 821         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 822         .flags          = INVERT_ENABLE,
 823         .clkdm_name     = "dpll4_clkdm",
 824         .recalc         = &omap3_clkoutx2_recalc,
 825 };
 826
 827 static struct clk emu_per_alwon_ck = {
 828         .name           = "emu_per_alwon_ck",
 829         .ops            = &clkops_null,
 830         .parent         = &dpll4_m6x2_ck,
 831         .clkdm_name     = "dpll4_clkdm",
 832         .recalc         = &followparent_recalc,
 833 };
 834
 835 /* DPLL5 */
 836 /* Supplies 120MHz clock, USIM source clock */
 837 /* Type: DPLL */
 838 /* 3430ES2 only */
 839 static struct dpll_data dpll5_dd = {
 840         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 841         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 842         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 843         .clk_bypass     = &sys_ck,
 844         .clk_ref        = &sys_ck,
 845         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 846         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 847         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 848         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 849         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 850         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 851         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 852         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 853         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 854         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 855         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 856         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 857         .min_divider    = 1,
 858         .max_divider    = OMAP3_MAX_DPLL_DIV,
 859         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 860 };
 861
 862 static struct clk dpll5_ck = {
 863         .name           = "dpll5_ck",
 864         .ops            = &clkops_noncore_dpll_ops,
 865         .parent         = &sys_ck,
 866         .dpll_data      = &dpll5_dd,
 867         .round_rate     = &omap2_dpll_round_rate,
 868         .set_rate       = &omap3_noncore_dpll_set_rate,
 869         .clkdm_name     = "dpll5_clkdm",
 870         .recalc         = &omap3_dpll_recalc,
 871 };
 872
 873 static const struct clksel div16_dpll5_clksel[] = {
 874         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 875         { .parent = NULL }
 876 };
 877
 878 static struct clk dpll5_m2_ck = {
 879         .name           = "dpll5_m2_ck",
 880         .ops            = &clkops_null,
 881         .parent         = &dpll5_ck,
 882         .init           = &omap2_init_clksel_parent,
 883         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 884         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 885         .clksel         = div16_dpll5_clksel,
 886         .clkdm_name     = "dpll5_clkdm",
 887         .recalc         = &omap2_clksel_recalc,
 888 };
 889
 890 /* CM EXTERNAL CLOCK OUTPUTS */
 891
 892 static const struct clksel_rate clkout2_src_core_rates[] = {
 893         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 894         { .div = 0 }
 895 };
 896
 897 static const struct clksel_rate clkout2_src_sys_rates[] = {
 898         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 899         { .div = 0 }
 900 };
 901
 902 static const struct clksel_rate clkout2_src_96m_rates[] = {
 903         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 904         { .div = 0 }
 905 };
 906
 907 static const struct clksel_rate clkout2_src_54m_rates[] = {
 908         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 909         { .div = 0 }
 910 };
 911
 912 static const struct clksel clkout2_src_clksel[] = {
 913         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
 914         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
 915         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
 916         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
 917         { .parent = NULL }
 918 };
 919
 920 static struct clk clkout2_src_ck = {
 921         .name           = "clkout2_src_ck",
 922         .ops            = &clkops_omap2_dflt,
 923         .init           = &omap2_init_clksel_parent,
 924         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 925         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 926         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 927         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 928         .clksel         = clkout2_src_clksel,
 929         .clkdm_name     = "core_clkdm",
 930         .recalc         = &omap2_clksel_recalc,
 931 };
 932
 933 static const struct clksel_rate sys_clkout2_rates[] = {
 934         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 935         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 936         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 937         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 938         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 939         { .div = 0 },
 940 };
 941
 942 static const struct clksel sys_clkout2_clksel[] = {
 943         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 944         { .parent = NULL },
 945 };
 946
 947 static struct clk sys_clkout2 = {
 948         .name           = "sys_clkout2",
 949         .ops            = &clkops_null,
 950         .init           = &omap2_init_clksel_parent,
 951         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 952         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
 953         .clksel         = sys_clkout2_clksel,
 954         .recalc         = &omap2_clksel_recalc,
 955 };
 956
 957 /* CM OUTPUT CLOCKS */
 958
 959 static struct clk corex2_fck = {
 960         .name           = "corex2_fck",
 961         .ops            = &clkops_null,
 962         .parent         = &dpll3_m2x2_ck,
 963         .recalc         = &followparent_recalc,
 964 };
 965
 966 /* DPLL power domain clock controls */
 967
 968 static const struct clksel_rate div4_rates[] = {
 969         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 970         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 971         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 972         { .div = 0 }
 973 };
 974
 975 static const struct clksel div4_core_clksel[] = {
 976         { .parent = &core_ck, .rates = div4_rates },
 977         { .parent = NULL }
 978 };
 979
 980 /*
 981  * REVISIT: Are these in DPLL power domain or CM power domain? docs
 982  * may be inconsistent here?
 983  */
 984 static struct clk dpll1_fck = {
 985         .name           = "dpll1_fck",
 986         .ops            = &clkops_null,
 987         .parent         = &core_ck,
 988         .init           = &omap2_init_clksel_parent,
 989         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 990         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
 991         .clksel         = div4_core_clksel,
 992         .recalc         = &omap2_clksel_recalc,
 993 };
 994
 995 static struct clk mpu_ck = {
 996         .name           = "mpu_ck",
 997         .ops            = &clkops_null,
 998         .parent         = &dpll1_x2m2_ck,
 999         .clkdm_name     = "mpu_clkdm",
1000         .recalc         = &followparent_recalc,
1001 };
1002
1003 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1004 static const struct clksel_rate arm_fck_rates[] = {
1005         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1006         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1007         { .div = 0 },
1008 };
1009
1010 static const struct clksel arm_fck_clksel[] = {
1011         { .parent = &mpu_ck, .rates = arm_fck_rates },
1012         { .parent = NULL }
1013 };
1014
1015 static struct clk arm_fck = {
1016         .name           = "arm_fck",
1017         .ops            = &clkops_null,
1018         .parent         = &mpu_ck,
1019         .init           = &omap2_init_clksel_parent,
1020         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1021         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1022         .clksel         = arm_fck_clksel,
1023         .recalc         = &omap2_clksel_recalc,
1024 };
1025
1026 /* XXX What about neon_clkdm ? */
1027
1028 /*
1029  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1030  * although it is referenced - so this is a guess
1031  */
1032 static struct clk emu_mpu_alwon_ck = {
1033         .name           = "emu_mpu_alwon_ck",
1034         .ops            = &clkops_null,
1035         .parent         = &mpu_ck,
1036         .recalc         = &followparent_recalc,
1037 };
1038
1039 static struct clk dpll2_fck = {
1040         .name           = "dpll2_fck",
1041         .ops            = &clkops_null,
1042         .parent         = &core_ck,
1043         .init           = &omap2_init_clksel_parent,
1044         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1045         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1046         .clksel         = div4_core_clksel,
1047         .recalc         = &omap2_clksel_recalc,
1048 };
1049
1050 static struct clk iva2_ck = {
1051         .name           = "iva2_ck",
1052         .ops            = &clkops_omap2_dflt_wait,
1053         .parent         = &dpll2_m2_ck,
1054         .init           = &omap2_init_clksel_parent,
1055         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1056         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1057         .clkdm_name     = "iva2_clkdm",
1058         .recalc         = &followparent_recalc,
1059 };
1060
1061 /* Common interface clocks */
1062
1063 static const struct clksel div2_core_clksel[] = {
1064         { .parent = &core_ck, .rates = div2_rates },
1065         { .parent = NULL }
1066 };
1067
1068 static struct clk l3_ick = {
1069         .name           = "l3_ick",
1070         .ops            = &clkops_null,
1071         .parent         = &core_ck,
1072         .init           = &omap2_init_clksel_parent,
1073         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1074         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1075         .clksel         = div2_core_clksel,
1076         .clkdm_name     = "core_l3_clkdm",
1077         .recalc         = &omap2_clksel_recalc,
1078 };
1079
1080 static const struct clksel div2_l3_clksel[] = {
1081         { .parent = &l3_ick, .rates = div2_rates },
1082         { .parent = NULL }
1083 };
1084
1085 static struct clk l4_ick = {
1086         .name           = "l4_ick",
1087         .ops            = &clkops_null,
1088         .parent         = &l3_ick,
1089         .init           = &omap2_init_clksel_parent,
1090         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1091         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1092         .clksel         = div2_l3_clksel,
1093         .clkdm_name     = "core_l4_clkdm",
1094         .recalc         = &omap2_clksel_recalc,
1095
1096 };
1097
1098 static const struct clksel div2_l4_clksel[] = {
1099         { .parent = &l4_ick, .rates = div2_rates },
1100         { .parent = NULL }
1101 };
1102
1103 static struct clk rm_ick = {
1104         .name           = "rm_ick",
1105         .ops            = &clkops_null,
1106         .parent         = &l4_ick,
1107         .init           = &omap2_init_clksel_parent,
1108         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1109         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1110         .clksel         = div2_l4_clksel,
1111         .recalc         = &omap2_clksel_recalc,
1112 };
1113
1114 /* GFX power domain */
1115
1116 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1117
1118 static const struct clksel gfx_l3_clksel[] = {
1119         { .parent = &l3_ick, .rates = gfx_l3_rates },
1120         { .parent = NULL }
1121 };
1122
1123 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1124 static struct clk gfx_l3_ck = {
1125         .name           = "gfx_l3_ck",
1126         .ops            = &clkops_omap2_dflt_wait,
1127         .parent         = &l3_ick,
1128         .init           = &omap2_init_clksel_parent,
1129         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1130         .enable_bit     = OMAP_EN_GFX_SHIFT,
1131         .recalc         = &followparent_recalc,
1132 };
1133
1134 static struct clk gfx_l3_fck = {
1135         .name           = "gfx_l3_fck",
1136         .ops            = &clkops_null,
1137         .parent         = &gfx_l3_ck,
1138         .init           = &omap2_init_clksel_parent,
1139         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1140         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1141         .clksel         = gfx_l3_clksel,
1142         .clkdm_name     = "gfx_3430es1_clkdm",
1143         .recalc         = &omap2_clksel_recalc,
1144 };
1145
1146 static struct clk gfx_l3_ick = {
1147         .name           = "gfx_l3_ick",
1148         .ops            = &clkops_null,
1149         .parent         = &gfx_l3_ck,
1150         .clkdm_name     = "gfx_3430es1_clkdm",
1151         .recalc         = &followparent_recalc,
1152 };
1153
1154 static struct clk gfx_cg1_ck = {
1155         .name           = "gfx_cg1_ck",
1156         .ops            = &clkops_omap2_dflt_wait,
1157         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1158         .init           = &omap2_init_clk_clkdm,
1159         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1160         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1161         .clkdm_name     = "gfx_3430es1_clkdm",
1162         .recalc         = &followparent_recalc,
1163 };
1164
1165 static struct clk gfx_cg2_ck = {
1166         .name           = "gfx_cg2_ck",
1167         .ops            = &clkops_omap2_dflt_wait,
1168         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1169         .init           = &omap2_init_clk_clkdm,
1170         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1171         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1172         .clkdm_name     = "gfx_3430es1_clkdm",
1173         .recalc         = &followparent_recalc,
1174 };
1175
1176 /* SGX power domain - 3430ES2 only */
1177
1178 static const struct clksel_rate sgx_core_rates[] = {
1179         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1180         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1181         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1182         { .div = 0 },
1183 };
1184
1185 static const struct clksel_rate sgx_96m_rates[] = {
1186         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1187         { .div = 0 },
1188 };
1189
1190 static const struct clksel sgx_clksel[] = {
1191         { .parent = &core_ck,    .rates = sgx_core_rates },
1192         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1193         { .parent = NULL },
1194 };
1195
1196 static struct clk sgx_fck = {
1197         .name           = "sgx_fck",
1198         .ops            = &clkops_omap2_dflt_wait,
1199         .init           = &omap2_init_clksel_parent,
1200         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1201         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1202         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1203         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1204         .clksel         = sgx_clksel,
1205         .clkdm_name     = "sgx_clkdm",
1206         .recalc         = &omap2_clksel_recalc,
1207 };
1208
1209 static struct clk sgx_ick = {
1210         .name           = "sgx_ick",
1211         .ops            = &clkops_omap2_dflt_wait,
1212         .parent         = &l3_ick,
1213         .init           = &omap2_init_clk_clkdm,
1214         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1215         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1216         .clkdm_name     = "sgx_clkdm",
1217         .recalc         = &followparent_recalc,
1218 };
1219
1220 /* CORE power domain */
1221
1222 static struct clk d2d_26m_fck = {
1223         .name           = "d2d_26m_fck",
1224         .ops            = &clkops_omap2_dflt_wait,
1225         .parent         = &sys_ck,
1226         .init           = &omap2_init_clk_clkdm,
1227         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1228         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1229         .clkdm_name     = "d2d_clkdm",
1230         .recalc         = &followparent_recalc,
1231 };
1232
1233 static struct clk modem_fck = {
1234         .name           = "modem_fck",
1235         .ops            = &clkops_omap2_dflt_wait,
1236         .parent         = &sys_ck,
1237         .init           = &omap2_init_clk_clkdm,
1238         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1239         .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
1240         .clkdm_name     = "d2d_clkdm",
1241         .recalc         = &followparent_recalc,
1242 };
1243
1244 static struct clk sad2d_ick = {
1245         .name           = "sad2d_ick",
1246         .ops            = &clkops_omap2_dflt_wait,
1247         .parent         = &l3_ick,
1248         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1249         .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
1250         .clkdm_name     = "d2d_clkdm",
1251         .recalc         = &followparent_recalc,
1252 };
1253
1254 static struct clk mad2d_ick = {
1255         .name           = "mad2d_ick",
1256         .ops            = &clkops_omap2_dflt_wait,
1257         .parent         = &l3_ick,
1258         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1259         .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
1260         .clkdm_name     = "d2d_clkdm",
1261         .recalc         = &followparent_recalc,
1262 };
1263
1264 static const struct clksel omap343x_gpt_clksel[] = {
1265         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1266         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1267         { .parent = NULL}
1268 };
1269
1270 static struct clk gpt10_fck = {
1271         .name           = "gpt10_fck",
1272         .ops            = &clkops_omap2_dflt_wait,
1273         .parent         = &sys_ck,
1274         .init           = &omap2_init_clksel_parent,
1275         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1276         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1277         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1278         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1279         .clksel         = omap343x_gpt_clksel,
1280         .clkdm_name     = "core_l4_clkdm",
1281         .recalc         = &omap2_clksel_recalc,
1282 };
1283
1284 static struct clk gpt11_fck = {
1285         .name           = "gpt11_fck",
1286         .ops            = &clkops_omap2_dflt_wait,
1287         .parent         = &sys_ck,
1288         .init           = &omap2_init_clksel_parent,
1289         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1290         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1291         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1292         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1293         .clksel         = omap343x_gpt_clksel,
1294         .clkdm_name     = "core_l4_clkdm",
1295         .recalc         = &omap2_clksel_recalc,
1296 };
1297
1298 static struct clk cpefuse_fck = {
1299         .name           = "cpefuse_fck",
1300         .ops            = &clkops_omap2_dflt,
1301         .parent         = &sys_ck,
1302         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1303         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1304         .recalc         = &followparent_recalc,
1305 };
1306
1307 static struct clk ts_fck = {
1308         .name           = "ts_fck",
1309         .ops            = &clkops_omap2_dflt,
1310         .parent         = &omap_32k_fck,
1311         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1312         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1313         .recalc         = &followparent_recalc,
1314 };
1315
1316 static struct clk usbtll_fck = {
1317         .name           = "usbtll_fck",
1318         .ops            = &clkops_omap2_dflt,
1319         .parent         = &dpll5_m2_ck,
1320         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1321         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1322         .recalc         = &followparent_recalc,
1323 };
1324
1325 /* CORE 96M FCLK-derived clocks */
1326
1327 static struct clk core_96m_fck = {
1328         .name           = "core_96m_fck",
1329         .ops            = &clkops_null,
1330         .parent         = &omap_96m_fck,
1331         .clkdm_name     = "core_l4_clkdm",
1332         .recalc         = &followparent_recalc,
1333 };
1334
1335 static struct clk mmchs3_fck = {
1336         .name           = "mmchs_fck",
1337         .ops            = &clkops_omap2_dflt_wait,
1338         .id             = 2,
1339         .parent         = &core_96m_fck,
1340         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1341         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1342         .clkdm_name     = "core_l4_clkdm",
1343         .recalc         = &followparent_recalc,
1344 };
1345
1346 static struct clk mmchs2_fck = {
1347         .name           = "mmchs_fck",
1348         .ops            = &clkops_omap2_dflt_wait,
1349         .id             = 1,
1350         .parent         = &core_96m_fck,
1351         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1352         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1353         .clkdm_name     = "core_l4_clkdm",
1354         .recalc         = &followparent_recalc,
1355 };
1356
1357 static struct clk mspro_fck = {
1358         .name           = "mspro_fck",
1359         .ops            = &clkops_omap2_dflt_wait,
1360         .parent         = &core_96m_fck,
1361         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1362         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1363         .clkdm_name     = "core_l4_clkdm",
1364         .recalc         = &followparent_recalc,
1365 };
1366
1367 static struct clk mmchs1_fck = {
1368         .name           = "mmchs_fck",
1369         .ops            = &clkops_omap2_dflt_wait,
1370         .parent         = &core_96m_fck,
1371         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1372         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1373         .clkdm_name     = "core_l4_clkdm",
1374         .recalc         = &followparent_recalc,
1375 };
1376
1377 static struct clk i2c3_fck = {
1378         .name           = "i2c_fck",
1379         .ops            = &clkops_omap2_dflt_wait,
1380         .id             = 3,
1381         .parent         = &core_96m_fck,
1382         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1383         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1384         .clkdm_name     = "core_l4_clkdm",
1385         .recalc         = &followparent_recalc,
1386 };
1387
1388 static struct clk i2c2_fck = {
1389         .name           = "i2c_fck",
1390         .ops            = &clkops_omap2_dflt_wait,
1391         .id             = 2,
1392         .parent         = &core_96m_fck,
1393         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1394         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1395         .clkdm_name     = "core_l4_clkdm",
1396         .recalc         = &followparent_recalc,
1397 };
1398
1399 static struct clk i2c1_fck = {
1400         .name           = "i2c_fck",
1401         .ops            = &clkops_omap2_dflt_wait,
1402         .id             = 1,
1403         .parent         = &core_96m_fck,
1404         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1405         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1406         .clkdm_name     = "core_l4_clkdm",
1407         .recalc         = &followparent_recalc,
1408 };
1409
1410 /*
1411  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1412  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1413  */
1414 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1415         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1416         { .div = 0 }
1417 };
1418
1419 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1420         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1421         { .div = 0 }
1422 };
1423
1424 static const struct clksel mcbsp_15_clksel[] = {
1425         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1426         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1427         { .parent = NULL }
1428 };
1429
1430 static struct clk mcbsp5_fck = {
1431         .name           = "mcbsp_fck",
1432         .ops            = &clkops_omap2_dflt_wait,
1433         .id             = 5,
1434         .init           = &omap2_init_clksel_parent,
1435         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1436         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1437         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1438         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1439         .clksel         = mcbsp_15_clksel,
1440         .clkdm_name     = "core_l4_clkdm",
1441         .recalc         = &omap2_clksel_recalc,
1442 };
1443
1444 static struct clk mcbsp1_fck = {
1445         .name           = "mcbsp_fck",
1446         .ops            = &clkops_omap2_dflt_wait,
1447         .id             = 1,
1448         .init           = &omap2_init_clksel_parent,
1449         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1450         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1451         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1452         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1453         .clksel         = mcbsp_15_clksel,
1454         .clkdm_name     = "core_l4_clkdm",
1455         .recalc         = &omap2_clksel_recalc,
1456 };
1457
1458 /* CORE_48M_FCK-derived clocks */
1459
1460 static struct clk core_48m_fck = {
1461         .name           = "core_48m_fck",
1462         .ops            = &clkops_null,
1463         .parent         = &omap_48m_fck,
1464         .clkdm_name     = "core_l4_clkdm",
1465         .recalc         = &followparent_recalc,
1466 };
1467
1468 static struct clk mcspi4_fck = {
1469         .name           = "mcspi_fck",
1470         .ops            = &clkops_omap2_dflt_wait,
1471         .id             = 4,
1472         .parent         = &core_48m_fck,
1473         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1474         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1475         .recalc         = &followparent_recalc,
1476 };
1477
1478 static struct clk mcspi3_fck = {
1479         .name           = "mcspi_fck",
1480         .ops            = &clkops_omap2_dflt_wait,
1481         .id             = 3,
1482         .parent         = &core_48m_fck,
1483         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1484         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1485         .recalc         = &followparent_recalc,
1486 };
1487
1488 static struct clk mcspi2_fck = {
1489         .name           = "mcspi_fck",
1490         .ops            = &clkops_omap2_dflt_wait,
1491         .id             = 2,
1492         .parent         = &core_48m_fck,
1493         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1494         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1495         .recalc         = &followparent_recalc,
1496 };
1497
1498 static struct clk mcspi1_fck = {
1499         .name           = "mcspi_fck",
1500         .ops            = &clkops_omap2_dflt_wait,
1501         .id             = 1,
1502         .parent         = &core_48m_fck,
1503         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1504         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1505         .recalc         = &followparent_recalc,
1506 };
1507
1508 static struct clk uart2_fck = {
1509         .name           = "uart2_fck",
1510         .ops            = &clkops_omap2_dflt_wait,
1511         .parent         = &core_48m_fck,
1512         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1513         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1514         .recalc         = &followparent_recalc,
1515 };
1516
1517 static struct clk uart1_fck = {
1518         .name           = "uart1_fck",
1519         .ops            = &clkops_omap2_dflt_wait,
1520         .parent         = &core_48m_fck,
1521         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1522         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1523         .recalc         = &followparent_recalc,
1524 };
1525
1526 static struct clk fshostusb_fck = {
1527         .name           = "fshostusb_fck",
1528         .ops            = &clkops_omap2_dflt_wait,
1529         .parent         = &core_48m_fck,
1530         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1531         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1532         .recalc         = &followparent_recalc,
1533 };
1534
1535 /* CORE_12M_FCK based clocks */
1536
1537 static struct clk core_12m_fck = {
1538         .name           = "core_12m_fck",
1539         .ops            = &clkops_null,
1540         .parent         = &omap_12m_fck,
1541         .clkdm_name     = "core_l4_clkdm",
1542         .recalc         = &followparent_recalc,
1543 };
1544
1545 static struct clk hdq_fck = {
1546         .name           = "hdq_fck",
1547         .ops            = &clkops_omap2_dflt_wait,
1548         .parent         = &core_12m_fck,
1549         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1550         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1551         .recalc         = &followparent_recalc,
1552 };
1553
1554 /* DPLL3-derived clock */
1555
1556 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1557         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1558         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1559         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1560         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1561         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1562         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1563         { .div = 0 }
1564 };
1565
1566 static const struct clksel ssi_ssr_clksel[] = {
1567         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1568         { .parent = NULL }
1569 };
1570
1571 static struct clk ssi_ssr_fck = {
1572         .name           = "ssi_ssr_fck",
1573         .ops            = &clkops_omap2_dflt,
1574         .init           = &omap2_init_clksel_parent,
1575         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1576         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1577         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1578         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1579         .clksel         = ssi_ssr_clksel,
1580         .clkdm_name     = "core_l4_clkdm",
1581         .recalc         = &omap2_clksel_recalc,
1582 };
1583
1584 static struct clk ssi_sst_fck = {
1585         .name           = "ssi_sst_fck",
1586         .ops            = &clkops_null,
1587         .parent         = &ssi_ssr_fck,
1588         .fixed_div      = 2,
1589         .recalc         = &omap2_fixed_divisor_recalc,
1590 };
1591
1592
1593
1594 /* CORE_L3_ICK based clocks */
1595
1596 /*
1597  * XXX must add clk_enable/clk_disable for these if standard code won't
1598  * handle it
1599  */
1600 static struct clk core_l3_ick = {
1601         .name           = "core_l3_ick",
1602         .ops            = &clkops_null,
1603         .parent         = &l3_ick,
1604         .init           = &omap2_init_clk_clkdm,
1605         .clkdm_name     = "core_l3_clkdm",
1606         .recalc         = &followparent_recalc,
1607 };
1608
1609 static struct clk hsotgusb_ick = {
1610         .name           = "hsotgusb_ick",
1611         .ops            = &clkops_omap2_dflt_wait,
1612         .parent         = &core_l3_ick,
1613         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1614         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1615         .clkdm_name     = "core_l3_clkdm",
1616         .recalc         = &followparent_recalc,
1617 };
1618
1619 static struct clk sdrc_ick = {
1620         .name           = "sdrc_ick",
1621         .ops            = &clkops_omap2_dflt_wait,
1622         .parent         = &core_l3_ick,
1623         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1624         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1625         .flags          = ENABLE_ON_INIT,
1626         .clkdm_name     = "core_l3_clkdm",
1627         .recalc         = &followparent_recalc,
1628 };
1629
1630 static struct clk gpmc_fck = {
1631         .name           = "gpmc_fck",
1632         .ops            = &clkops_null,
1633         .parent         = &core_l3_ick,
1634         .flags          = ENABLE_ON_INIT, /* huh? */
1635         .clkdm_name     = "core_l3_clkdm",
1636         .recalc         = &followparent_recalc,
1637 };
1638
1639 /* SECURITY_L3_ICK based clocks */
1640
1641 static struct clk security_l3_ick = {
1642         .name           = "security_l3_ick",
1643         .ops            = &clkops_null,
1644         .parent         = &l3_ick,
1645         .recalc         = &followparent_recalc,
1646 };
1647
1648 static struct clk pka_ick = {
1649         .name           = "pka_ick",
1650         .ops            = &clkops_omap2_dflt_wait,
1651         .parent         = &security_l3_ick,
1652         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1653         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1654         .recalc         = &followparent_recalc,
1655 };
1656
1657 /* CORE_L4_ICK based clocks */
1658
1659 static struct clk core_l4_ick = {
1660         .name           = "core_l4_ick",
1661         .ops            = &clkops_null,
1662         .parent         = &l4_ick,
1663         .init           = &omap2_init_clk_clkdm,
1664         .clkdm_name     = "core_l4_clkdm",
1665         .recalc         = &followparent_recalc,
1666 };
1667
1668 static struct clk usbtll_ick = {
1669         .name           = "usbtll_ick",
1670         .ops            = &clkops_omap2_dflt_wait,
1671         .parent         = &core_l4_ick,
1672         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1673         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1674         .clkdm_name     = "core_l4_clkdm",
1675         .recalc         = &followparent_recalc,
1676 };
1677
1678 static struct clk mmchs3_ick = {
1679         .name           = "mmchs_ick",
1680         .ops            = &clkops_omap2_dflt_wait,
1681         .id             = 2,
1682         .parent         = &core_l4_ick,
1683         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1684         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1685         .clkdm_name     = "core_l4_clkdm",
1686         .recalc         = &followparent_recalc,
1687 };
1688
1689 /* Intersystem Communication Registers - chassis mode only */
1690 static struct clk icr_ick = {
1691         .name           = "icr_ick",
1692         .ops            = &clkops_omap2_dflt_wait,
1693         .parent         = &core_l4_ick,
1694         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1695         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1696         .clkdm_name     = "core_l4_clkdm",
1697         .recalc         = &followparent_recalc,
1698 };
1699
1700 static struct clk aes2_ick = {
1701         .name           = "aes2_ick",
1702         .ops            = &clkops_omap2_dflt_wait,
1703         .parent         = &core_l4_ick,
1704         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1705         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1706         .clkdm_name     = "core_l4_clkdm",
1707         .recalc         = &followparent_recalc,
1708 };
1709
1710 static struct clk sha12_ick = {
1711         .name           = "sha12_ick",
1712         .ops            = &clkops_omap2_dflt_wait,
1713         .parent         = &core_l4_ick,
1714         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1715         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1716         .clkdm_name     = "core_l4_clkdm",
1717         .recalc         = &followparent_recalc,
1718 };
1719
1720 static struct clk des2_ick = {
1721         .name           = "des2_ick",
1722         .ops            = &clkops_omap2_dflt_wait,
1723         .parent         = &core_l4_ick,
1724         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1725         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1726         .clkdm_name     = "core_l4_clkdm",
1727         .recalc         = &followparent_recalc,
1728 };
1729
1730 static struct clk mmchs2_ick = {
1731         .name           = "mmchs_ick",
1732         .ops            = &clkops_omap2_dflt_wait,
1733         .id             = 1,
1734         .parent         = &core_l4_ick,
1735         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1736         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1737         .clkdm_name     = "core_l4_clkdm",
1738         .recalc         = &followparent_recalc,
1739 };
1740
1741 static struct clk mmchs1_ick = {
1742         .name           = "mmchs_ick",
1743         .ops            = &clkops_omap2_dflt_wait,
1744         .parent         = &core_l4_ick,
1745         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1746         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1747         .clkdm_name     = "core_l4_clkdm",
1748         .recalc         = &followparent_recalc,
1749 };
1750
1751 static struct clk mspro_ick = {
1752         .name           = "mspro_ick",
1753         .ops            = &clkops_omap2_dflt_wait,
1754         .parent         = &core_l4_ick,
1755         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1756         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1757         .clkdm_name     = "core_l4_clkdm",
1758         .recalc         = &followparent_recalc,
1759 };
1760
1761 static struct clk hdq_ick = {
1762         .name           = "hdq_ick",
1763         .ops            = &clkops_omap2_dflt_wait,
1764         .parent         = &core_l4_ick,
1765         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1766         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1767         .clkdm_name     = "core_l4_clkdm",
1768         .recalc         = &followparent_recalc,
1769 };
1770
1771 static struct clk mcspi4_ick = {
1772         .name           = "mcspi_ick",
1773         .ops            = &clkops_omap2_dflt_wait,
1774         .id             = 4,
1775         .parent         = &core_l4_ick,
1776         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1777         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1778         .clkdm_name     = "core_l4_clkdm",
1779         .recalc         = &followparent_recalc,
1780 };
1781
1782 static struct clk mcspi3_ick = {
1783         .name           = "mcspi_ick",
1784         .ops            = &clkops_omap2_dflt_wait,
1785         .id             = 3,
1786         .parent         = &core_l4_ick,
1787         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1788         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1789         .clkdm_name     = "core_l4_clkdm",
1790         .recalc         = &followparent_recalc,
1791 };
1792
1793 static struct clk mcspi2_ick = {
1794         .name           = "mcspi_ick",
1795         .ops            = &clkops_omap2_dflt_wait,
1796         .id             = 2,
1797         .parent         = &core_l4_ick,
1798         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1799         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1800         .clkdm_name     = "core_l4_clkdm",
1801         .recalc         = &followparent_recalc,
1802 };
1803
1804 static struct clk mcspi1_ick = {
1805         .name           = "mcspi_ick",
1806         .ops            = &clkops_omap2_dflt_wait,
1807         .id             = 1,
1808         .parent         = &core_l4_ick,
1809         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1810         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1811         .clkdm_name     = "core_l4_clkdm",
1812         .recalc         = &followparent_recalc,
1813 };
1814
1815 static struct clk i2c3_ick = {
1816         .name           = "i2c_ick",
1817         .ops            = &clkops_omap2_dflt_wait,
1818         .id             = 3,
1819         .parent         = &core_l4_ick,
1820         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1821         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1822         .clkdm_name     = "core_l4_clkdm",
1823         .recalc         = &followparent_recalc,
1824 };
1825
1826 static struct clk i2c2_ick = {
1827         .name           = "i2c_ick",
1828         .ops            = &clkops_omap2_dflt_wait,
1829         .id             = 2,
1830         .parent         = &core_l4_ick,
1831         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1832         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1833         .clkdm_name     = "core_l4_clkdm",
1834         .recalc         = &followparent_recalc,
1835 };
1836
1837 static struct clk i2c1_ick = {
1838         .name           = "i2c_ick",
1839         .ops            = &clkops_omap2_dflt_wait,
1840         .id             = 1,
1841         .parent         = &core_l4_ick,
1842         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1843         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1844         .clkdm_name     = "core_l4_clkdm",
1845         .recalc         = &followparent_recalc,
1846 };
1847
1848 static struct clk uart2_ick = {
1849         .name           = "uart2_ick",
1850         .ops            = &clkops_omap2_dflt_wait,
1851         .parent         = &core_l4_ick,
1852         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1853         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1854         .clkdm_name     = "core_l4_clkdm",
1855         .recalc         = &followparent_recalc,
1856 };
1857
1858 static struct clk uart1_ick = {
1859         .name           = "uart1_ick",
1860         .ops            = &clkops_omap2_dflt_wait,
1861         .parent         = &core_l4_ick,
1862         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1863         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1864         .clkdm_name     = "core_l4_clkdm",
1865         .recalc         = &followparent_recalc,
1866 };
1867
1868 static struct clk gpt11_ick = {
1869         .name           = "gpt11_ick",
1870         .ops            = &clkops_omap2_dflt_wait,
1871         .parent         = &core_l4_ick,
1872         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1873         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1874         .clkdm_name     = "core_l4_clkdm",
1875         .recalc         = &followparent_recalc,
1876 };
1877
1878 static struct clk gpt10_ick = {
1879         .name           = "gpt10_ick",
1880         .ops            = &clkops_omap2_dflt_wait,
1881         .parent         = &core_l4_ick,
1882         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1883         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1884         .clkdm_name     = "core_l4_clkdm",
1885         .recalc         = &followparent_recalc,
1886 };
1887
1888 static struct clk mcbsp5_ick = {
1889         .name           = "mcbsp_ick",
1890         .ops            = &clkops_omap2_dflt_wait,
1891         .id             = 5,
1892         .parent         = &core_l4_ick,
1893         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1894         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1895         .clkdm_name     = "core_l4_clkdm",
1896         .recalc         = &followparent_recalc,
1897 };
1898
1899 static struct clk mcbsp1_ick = {
1900         .name           = "mcbsp_ick",
1901         .ops            = &clkops_omap2_dflt_wait,
1902         .id             = 1,
1903         .parent         = &core_l4_ick,
1904         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1905         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1906         .clkdm_name     = "core_l4_clkdm",
1907         .recalc         = &followparent_recalc,
1908 };
1909
1910 static struct clk fac_ick = {
1911         .name           = "fac_ick",
1912         .ops            = &clkops_omap2_dflt_wait,
1913         .parent         = &core_l4_ick,
1914         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1915         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1916         .clkdm_name     = "core_l4_clkdm",
1917         .recalc         = &followparent_recalc,
1918 };
1919
1920 static struct clk mailboxes_ick = {
1921         .name           = "mailboxes_ick",
1922         .ops            = &clkops_omap2_dflt_wait,
1923         .parent         = &core_l4_ick,
1924         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1925         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1926         .clkdm_name     = "core_l4_clkdm",
1927         .recalc         = &followparent_recalc,
1928 };
1929
1930 static struct clk omapctrl_ick = {
1931         .name           = "omapctrl_ick",
1932         .ops            = &clkops_omap2_dflt_wait,
1933         .parent         = &core_l4_ick,
1934         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1935         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
1936         .flags          = ENABLE_ON_INIT,
1937         .recalc         = &followparent_recalc,
1938 };
1939
1940 /* SSI_L4_ICK based clocks */
1941
1942 static struct clk ssi_l4_ick = {
1943         .name           = "ssi_l4_ick",
1944         .ops            = &clkops_null,
1945         .parent         = &l4_ick,
1946         .clkdm_name     = "core_l4_clkdm",
1947         .recalc         = &followparent_recalc,
1948 };
1949
1950 static struct clk ssi_ick = {
1951         .name           = "ssi_ick",
1952         .ops            = &clkops_omap2_dflt,
1953         .parent         = &ssi_l4_ick,
1954         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1955         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1956         .clkdm_name     = "core_l4_clkdm",
1957         .recalc         = &followparent_recalc,
1958 };
1959
1960 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1961  * but l4_ick makes more sense to me */
1962
1963 static const struct clksel usb_l4_clksel[] = {
1964         { .parent = &l4_ick, .rates = div2_rates },
1965         { .parent = NULL },
1966 };
1967
1968 static struct clk usb_l4_ick = {
1969         .name           = "usb_l4_ick",
1970         .ops            = &clkops_omap2_dflt_wait,
1971         .parent         = &l4_ick,
1972         .init           = &omap2_init_clksel_parent,
1973         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1974         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1975         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1976         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
1977         .clksel         = usb_l4_clksel,
1978         .recalc         = &omap2_clksel_recalc,
1979 };
1980
1981 /* SECURITY_L4_ICK2 based clocks */
1982
1983 static struct clk security_l4_ick2 = {
1984         .name           = "security_l4_ick2",
1985         .ops            = &clkops_null,
1986         .parent         = &l4_ick,
1987         .recalc         = &followparent_recalc,
1988 };
1989
1990 static struct clk aes1_ick = {
1991         .name           = "aes1_ick",
1992         .ops            = &clkops_omap2_dflt_wait,
1993         .parent         = &security_l4_ick2,
1994         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1995         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
1996         .recalc         = &followparent_recalc,
1997 };
1998
1999 static struct clk rng_ick = {
2000         .name           = "rng_ick",
2001         .ops            = &clkops_omap2_dflt_wait,
2002         .parent         = &security_l4_ick2,
2003         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2004         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2005         .recalc         = &followparent_recalc,
2006 };
2007
2008 static struct clk sha11_ick = {
2009         .name           = "sha11_ick",
2010         .ops            = &clkops_omap2_dflt_wait,
2011         .parent         = &security_l4_ick2,
2012         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2013         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2014         .recalc         = &followparent_recalc,
2015 };
2016
2017 static struct clk des1_ick = {
2018         .name           = "des1_ick",
2019         .ops            = &clkops_omap2_dflt_wait,
2020         .parent         = &security_l4_ick2,
2021         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2022         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2023         .recalc         = &followparent_recalc,
2024 };
2025
2026 /* DSS */
2027 static struct clk dss1_alwon_fck = {
2028         .name           = "dss1_alwon_fck",
2029         .ops            = &clkops_omap2_dflt,
2030         .parent         = &dpll4_m4x2_ck,
2031         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2032         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2033         .clkdm_name     = "dss_clkdm",
2034         .recalc         = &followparent_recalc,
2035 };
2036
2037 static struct clk dss_tv_fck = {
2038         .name           = "dss_tv_fck",
2039         .ops            = &clkops_omap2_dflt,
2040         .parent         = &omap_54m_fck,
2041         .init           = &omap2_init_clk_clkdm,
2042         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2043         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2044         .clkdm_name     = "dss_clkdm",
2045         .recalc         = &followparent_recalc,
2046 };
2047
2048 static struct clk dss_96m_fck = {
2049         .name           = "dss_96m_fck",
2050         .ops            = &clkops_omap2_dflt,
2051         .parent         = &omap_96m_fck,
2052         .init           = &omap2_init_clk_clkdm,
2053         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2054         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2055         .clkdm_name     = "dss_clkdm",
2056         .recalc         = &followparent_recalc,
2057 };
2058
2059 static struct clk dss2_alwon_fck = {
2060         .name           = "dss2_alwon_fck",
2061         .ops            = &clkops_omap2_dflt,
2062         .parent         = &sys_ck,
2063         .init           = &omap2_init_clk_clkdm,
2064         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2065         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2066         .clkdm_name     = "dss_clkdm",
2067         .recalc         = &followparent_recalc,
2068 };
2069
2070 static struct clk dss_ick = {
2071         /* Handles both L3 and L4 clocks */
2072         .name           = "dss_ick",
2073         .ops            = &clkops_omap2_dflt,
2074         .parent         = &l4_ick,
2075         .init           = &omap2_init_clk_clkdm,
2076         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2077         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2078         .clkdm_name     = "dss_clkdm",
2079         .recalc         = &followparent_recalc,
2080 };
2081
2082 /* CAM */
2083
2084 static struct clk cam_mclk = {
2085         .name           = "cam_mclk",
2086         .ops            = &clkops_omap2_dflt,
2087         .parent         = &dpll4_m5x2_ck,
2088         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2089         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2090         .clkdm_name     = "cam_clkdm",
2091         .recalc         = &followparent_recalc,
2092 };
2093
2094 static struct clk cam_ick = {
2095         /* Handles both L3 and L4 clocks */
2096         .name           = "cam_ick",
2097         .ops            = &clkops_omap2_dflt,
2098         .parent         = &l4_ick,
2099         .init           = &omap2_init_clk_clkdm,
2100         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2101         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2102         .clkdm_name     = "cam_clkdm",
2103         .recalc         = &followparent_recalc,
2104 };
2105
2106 static struct clk csi2_96m_fck = {
2107         .name           = "csi2_96m_fck",
2108         .ops            = &clkops_omap2_dflt,
2109         .parent         = &core_96m_fck,
2110         .init           = &omap2_init_clk_clkdm,
2111         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2112         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2113         .clkdm_name     = "cam_clkdm",
2114         .recalc         = &followparent_recalc,
2115 };
2116
2117 /* USBHOST - 3430ES2 only */
2118
2119 static struct clk usbhost_120m_fck = {
2120         .name           = "usbhost_120m_fck",
2121         .ops            = &clkops_omap2_dflt_wait,
2122         .parent         = &dpll5_m2_ck,
2123         .init           = &omap2_init_clk_clkdm,
2124         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2125         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2126         .clkdm_name     = "usbhost_clkdm",
2127         .recalc         = &followparent_recalc,
2128 };
2129
2130 static struct clk usbhost_48m_fck = {
2131         .name           = "usbhost_48m_fck",
2132         .ops            = &clkops_omap2_dflt_wait,
2133         .parent         = &omap_48m_fck,
2134         .init           = &omap2_init_clk_clkdm,
2135         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2136         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2137         .clkdm_name     = "usbhost_clkdm",
2138         .recalc         = &followparent_recalc,
2139 };
2140
2141 static struct clk usbhost_ick = {
2142         /* Handles both L3 and L4 clocks */
2143         .name           = "usbhost_ick",
2144         .ops            = &clkops_omap2_dflt_wait,
2145         .parent         = &l4_ick,
2146         .init           = &omap2_init_clk_clkdm,
2147         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2148         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2149         .clkdm_name     = "usbhost_clkdm",
2150         .recalc         = &followparent_recalc,
2151 };
2152
2153 /* WKUP */
2154
2155 static const struct clksel_rate usim_96m_rates[] = {
2156         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2157         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2158         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2159         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2160         { .div = 0 },
2161 };
2162
2163 static const struct clksel_rate usim_120m_rates[] = {
2164         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2165         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2166         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2167         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2168         { .div = 0 },
2169 };
2170
2171 static const struct clksel usim_clksel[] = {
2172         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2173         { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
2174         { .parent = &sys_ck,            .rates = div2_rates },
2175         { .parent = NULL },
2176 };
2177
2178 /* 3430ES2 only */
2179 static struct clk usim_fck = {
2180         .name           = "usim_fck",
2181         .ops            = &clkops_omap2_dflt_wait,
2182         .init           = &omap2_init_clksel_parent,
2183         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2184         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2185         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2186         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2187         .clksel         = usim_clksel,
2188         .recalc         = &omap2_clksel_recalc,
2189 };
2190
2191 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2192 static struct clk gpt1_fck = {
2193         .name           = "gpt1_fck",
2194         .ops            = &clkops_omap2_dflt_wait,
2195         .init           = &omap2_init_clksel_parent,
2196         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2197         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2198         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2199         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2200         .clksel         = omap343x_gpt_clksel,
2201         .clkdm_name     = "wkup_clkdm",
2202         .recalc         = &omap2_clksel_recalc,
2203 };
2204
2205 static struct clk wkup_32k_fck = {
2206         .name           = "wkup_32k_fck",
2207         .ops            = &clkops_null,
2208         .init           = &omap2_init_clk_clkdm,
2209         .parent         = &omap_32k_fck,
2210         .clkdm_name     = "wkup_clkdm",
2211         .recalc         = &followparent_recalc,
2212 };
2213
2214 static struct clk gpio1_dbck = {
2215         .name           = "gpio1_dbck",
2216         .ops            = &clkops_omap2_dflt,
2217         .parent         = &wkup_32k_fck,
2218         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2219         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2220         .clkdm_name     = "wkup_clkdm",
2221         .recalc         = &followparent_recalc,
2222 };
2223
2224 static struct clk wdt2_fck = {
2225         .name           = "wdt2_fck",
2226         .ops            = &clkops_omap2_dflt_wait,
2227         .parent         = &wkup_32k_fck,
2228         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2229         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2230         .clkdm_name     = "wkup_clkdm",
2231         .recalc         = &followparent_recalc,
2232 };
2233
2234 static struct clk wkup_l4_ick = {
2235         .name           = "wkup_l4_ick",
2236         .ops            = &clkops_null,
2237         .parent         = &sys_ck,
2238         .clkdm_name     = "wkup_clkdm",
2239         .recalc         = &followparent_recalc,
2240 };
2241
2242 /* 3430ES2 only */
2243 /* Never specifically named in the TRM, so we have to infer a likely name */
2244 static struct clk usim_ick = {
2245         .name           = "usim_ick",
2246         .ops            = &clkops_omap2_dflt_wait,
2247         .parent         = &wkup_l4_ick,
2248         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2249         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2250         .clkdm_name     = "wkup_clkdm",
2251         .recalc         = &followparent_recalc,
2252 };
2253
2254 static struct clk wdt2_ick = {
2255         .name           = "wdt2_ick",
2256         .ops            = &clkops_omap2_dflt_wait,
2257         .parent         = &wkup_l4_ick,
2258         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2259         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2260         .clkdm_name     = "wkup_clkdm",
2261         .recalc         = &followparent_recalc,
2262 };
2263
2264 static struct clk wdt1_ick = {
2265         .name           = "wdt1_ick",
2266         .ops            = &clkops_omap2_dflt_wait,
2267         .parent         = &wkup_l4_ick,
2268         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2269         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2270         .clkdm_name     = "wkup_clkdm",
2271         .recalc         = &followparent_recalc,
2272 };
2273
2274 static struct clk gpio1_ick = {
2275         .name           = "gpio1_ick",
2276         .ops            = &clkops_omap2_dflt_wait,
2277         .parent         = &wkup_l4_ick,
2278         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2279         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2280         .clkdm_name     = "wkup_clkdm",
2281         .recalc         = &followparent_recalc,
2282 };
2283
2284 static struct clk omap_32ksync_ick = {
2285         .name           = "omap_32ksync_ick",
2286         .ops            = &clkops_omap2_dflt_wait,
2287         .parent         = &wkup_l4_ick,
2288         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2289         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2290         .clkdm_name     = "wkup_clkdm",
2291         .recalc         = &followparent_recalc,
2292 };
2293
2294 /* XXX This clock no longer exists in 3430 TRM rev F */
2295 static struct clk gpt12_ick = {
2296         .name           = "gpt12_ick",
2297         .ops            = &clkops_omap2_dflt_wait,
2298         .parent         = &wkup_l4_ick,
2299         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2300         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2301         .clkdm_name     = "wkup_clkdm",
2302         .recalc         = &followparent_recalc,
2303 };
2304
2305 static struct clk gpt1_ick = {
2306         .name           = "gpt1_ick",
2307         .ops            = &clkops_omap2_dflt_wait,
2308         .parent         = &wkup_l4_ick,
2309         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2310         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2311         .clkdm_name     = "wkup_clkdm",
2312         .recalc         = &followparent_recalc,
2313 };
2314
2315
2316
2317 /* PER clock domain */
2318
2319 static struct clk per_96m_fck = {
2320         .name           = "per_96m_fck",
2321         .ops            = &clkops_null,
2322         .parent         = &omap_96m_alwon_fck,
2323         .init           = &omap2_init_clk_clkdm,
2324         .clkdm_name     = "per_clkdm",
2325         .recalc         = &followparent_recalc,
2326 };
2327
2328 static struct clk per_48m_fck = {
2329         .name           = "per_48m_fck",
2330         .ops            = &clkops_null,
2331         .parent         = &omap_48m_fck,
2332         .init           = &omap2_init_clk_clkdm,
2333         .clkdm_name     = "per_clkdm",
2334         .recalc         = &followparent_recalc,
2335 };
2336
2337 static struct clk uart3_fck = {
2338         .name           = "uart3_fck",
2339         .ops            = &clkops_omap2_dflt_wait,
2340         .parent         = &per_48m_fck,
2341         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2342         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2343         .clkdm_name     = "per_clkdm",
2344         .recalc         = &followparent_recalc,
2345 };
2346
2347 static struct clk gpt2_fck = {
2348         .name           = "gpt2_fck",
2349         .ops            = &clkops_omap2_dflt_wait,
2350         .init           = &omap2_init_clksel_parent,
2351         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2352         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2353         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2354         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2355         .clksel         = omap343x_gpt_clksel,
2356         .clkdm_name     = "per_clkdm",
2357         .recalc         = &omap2_clksel_recalc,
2358 };
2359
2360 static struct clk gpt3_fck = {
2361         .name           = "gpt3_fck",
2362         .ops            = &clkops_omap2_dflt_wait,
2363         .init           = &omap2_init_clksel_parent,
2364         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2365         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2366         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2367         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2368         .clksel         = omap343x_gpt_clksel,
2369         .clkdm_name     = "per_clkdm",
2370         .recalc         = &omap2_clksel_recalc,
2371 };
2372
2373 static struct clk gpt4_fck = {
2374         .name           = "gpt4_fck",
2375         .ops            = &clkops_omap2_dflt_wait,
2376         .init           = &omap2_init_clksel_parent,
2377         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2378         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2379         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2380         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2381         .clksel         = omap343x_gpt_clksel,
2382         .clkdm_name     = "per_clkdm",
2383         .recalc         = &omap2_clksel_recalc,
2384 };
2385
2386 static struct clk gpt5_fck = {
2387         .name           = "gpt5_fck",
2388         .ops            = &clkops_omap2_dflt_wait,
2389         .init           = &omap2_init_clksel_parent,
2390         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2391         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2392         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2393         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2394         .clksel         = omap343x_gpt_clksel,
2395         .clkdm_name     = "per_clkdm",
2396         .recalc         = &omap2_clksel_recalc,
2397 };
2398
2399 static struct clk gpt6_fck = {
2400         .name           = "gpt6_fck",
2401         .ops            = &clkops_omap2_dflt_wait,
2402         .init           = &omap2_init_clksel_parent,
2403         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2404         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2405         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2406         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2407         .clksel         = omap343x_gpt_clksel,
2408         .clkdm_name     = "per_clkdm",
2409         .recalc         = &omap2_clksel_recalc,
2410 };
2411
2412 static struct clk gpt7_fck = {
2413         .name           = "gpt7_fck",
2414         .ops            = &clkops_omap2_dflt_wait,
2415         .init           = &omap2_init_clksel_parent,
2416         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2417         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2418         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2419         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2420         .clksel         = omap343x_gpt_clksel,
2421         .clkdm_name     = "per_clkdm",
2422         .recalc         = &omap2_clksel_recalc,
2423 };
2424
2425 static struct clk gpt8_fck = {
2426         .name           = "gpt8_fck",
2427         .ops            = &clkops_omap2_dflt_wait,
2428         .init           = &omap2_init_clksel_parent,
2429         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2430         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2431         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2432         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2433         .clksel         = omap343x_gpt_clksel,
2434         .clkdm_name     = "per_clkdm",
2435         .recalc         = &omap2_clksel_recalc,
2436 };
2437
2438 static struct clk gpt9_fck = {
2439         .name           = "gpt9_fck",
2440         .ops            = &clkops_omap2_dflt_wait,
2441         .init           = &omap2_init_clksel_parent,
2442         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2443         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2444         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2445         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2446         .clksel         = omap343x_gpt_clksel,
2447         .clkdm_name     = "per_clkdm",
2448         .recalc         = &omap2_clksel_recalc,
2449 };
2450
2451 static struct clk per_32k_alwon_fck = {
2452         .name           = "per_32k_alwon_fck",
2453         .ops            = &clkops_null,
2454         .parent         = &omap_32k_fck,
2455         .clkdm_name     = "per_clkdm",
2456         .recalc         = &followparent_recalc,
2457 };
2458
2459 static struct clk gpio6_dbck = {
2460         .name           = "gpio6_dbck",
2461         .ops            = &clkops_omap2_dflt,
2462         .parent         = &per_32k_alwon_fck,
2463         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2464         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2465         .clkdm_name     = "per_clkdm",
2466         .recalc         = &followparent_recalc,
2467 };
2468
2469 static struct clk gpio5_dbck = {
2470         .name           = "gpio5_dbck",
2471         .ops            = &clkops_omap2_dflt,
2472         .parent         = &per_32k_alwon_fck,
2473         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2474         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2475         .clkdm_name     = "per_clkdm",
2476         .recalc         = &followparent_recalc,
2477 };
2478
2479 static struct clk gpio4_dbck = {
2480         .name           = "gpio4_dbck",
2481         .ops            = &clkops_omap2_dflt,
2482         .parent         = &per_32k_alwon_fck,
2483         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2484         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2485         .clkdm_name     = "per_clkdm",
2486         .recalc         = &followparent_recalc,
2487 };
2488
2489 static struct clk gpio3_dbck = {
2490         .name           = "gpio3_dbck",
2491         .ops            = &clkops_omap2_dflt,
2492         .parent         = &per_32k_alwon_fck,
2493         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2494         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2495         .clkdm_name     = "per_clkdm",
2496         .recalc         = &followparent_recalc,
2497 };
2498
2499 static struct clk gpio2_dbck = {
2500         .name           = "gpio2_dbck",
2501         .ops            = &clkops_omap2_dflt,
2502         .parent         = &per_32k_alwon_fck,
2503         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2504         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2505         .clkdm_name     = "per_clkdm",
2506         .recalc         = &followparent_recalc,
2507 };
2508
2509 static struct clk wdt3_fck = {
2510         .name           = "wdt3_fck",
2511         .ops            = &clkops_omap2_dflt_wait,
2512         .parent         = &per_32k_alwon_fck,
2513         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2514         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2515         .clkdm_name     = "per_clkdm",
2516         .recalc         = &followparent_recalc,
2517 };
2518
2519 static struct clk per_l4_ick = {
2520         .name           = "per_l4_ick",
2521         .ops            = &clkops_null,
2522         .parent         = &l4_ick,
2523         .clkdm_name     = "per_clkdm",
2524         .recalc         = &followparent_recalc,
2525 };
2526
2527 static struct clk gpio6_ick = {
2528         .name           = "gpio6_ick",
2529         .ops            = &clkops_omap2_dflt_wait,
2530         .parent         = &per_l4_ick,
2531         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2532         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2533         .clkdm_name     = "per_clkdm",
2534         .recalc         = &followparent_recalc,
2535 };
2536
2537 static struct clk gpio5_ick = {
2538         .name           = "gpio5_ick",
2539         .ops            = &clkops_omap2_dflt_wait,
2540         .parent         = &per_l4_ick,
2541         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2542         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2543         .clkdm_name     = "per_clkdm",
2544         .recalc         = &followparent_recalc,
2545 };
2546
2547 static struct clk gpio4_ick = {
2548         .name           = "gpio4_ick",
2549         .ops            = &clkops_omap2_dflt_wait,
2550         .parent         = &per_l4_ick,
2551         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2552         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2553         .clkdm_name     = "per_clkdm",
2554         .recalc         = &followparent_recalc,
2555 };
2556
2557 static struct clk gpio3_ick = {
2558         .name           = "gpio3_ick",
2559         .ops            = &clkops_omap2_dflt_wait,
2560         .parent         = &per_l4_ick,
2561         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2562         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2563         .clkdm_name     = "per_clkdm",
2564         .recalc         = &followparent_recalc,
2565 };
2566
2567 static struct clk gpio2_ick = {
2568         .name           = "gpio2_ick",
2569         .ops            = &clkops_omap2_dflt_wait,
2570         .parent         = &per_l4_ick,
2571         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2572         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2573         .clkdm_name     = "per_clkdm",
2574         .recalc         = &followparent_recalc,
2575 };
2576
2577 static struct clk wdt3_ick = {
2578         .name           = "wdt3_ick",
2579         .ops            = &clkops_omap2_dflt_wait,
2580         .parent         = &per_l4_ick,
2581         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2582         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2583         .clkdm_name     = "per_clkdm",
2584         .recalc         = &followparent_recalc,
2585 };
2586
2587 static struct clk uart3_ick = {
2588         .name           = "uart3_ick",
2589         .ops            = &clkops_omap2_dflt_wait,
2590         .parent         = &per_l4_ick,
2591         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2592         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2593         .clkdm_name     = "per_clkdm",
2594         .recalc         = &followparent_recalc,
2595 };
2596
2597 static struct clk gpt9_ick = {
2598         .name           = "gpt9_ick",
2599         .ops            = &clkops_omap2_dflt_wait,
2600         .parent         = &per_l4_ick,
2601         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2602         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2603         .clkdm_name     = "per_clkdm",
2604         .recalc         = &followparent_recalc,
2605 };
2606
2607 static struct clk gpt8_ick = {
2608         .name           = "gpt8_ick",
2609         .ops            = &clkops_omap2_dflt_wait,
2610         .parent         = &per_l4_ick,
2611         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2612         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2613         .clkdm_name     = "per_clkdm",
2614         .recalc         = &followparent_recalc,
2615 };
2616
2617 static struct clk gpt7_ick = {
2618         .name           = "gpt7_ick",
2619         .ops            = &clkops_omap2_dflt_wait,
2620         .parent         = &per_l4_ick,
2621         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2622         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2623         .clkdm_name     = "per_clkdm",
2624         .recalc         = &followparent_recalc,
2625 };
2626
2627 static struct clk gpt6_ick = {
2628         .name           = "gpt6_ick",
2629         .ops            = &clkops_omap2_dflt_wait,
2630         .parent         = &per_l4_ick,
2631         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2632         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2633         .clkdm_name     = "per_clkdm",
2634         .recalc         = &followparent_recalc,
2635 };
2636
2637 static struct clk gpt5_ick = {
2638         .name           = "gpt5_ick",
2639         .ops            = &clkops_omap2_dflt_wait,
2640         .parent         = &per_l4_ick,
2641         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2642         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2643         .clkdm_name     = "per_clkdm",
2644         .recalc         = &followparent_recalc,
2645 };
2646
2647 static struct clk gpt4_ick = {
2648         .name           = "gpt4_ick",
2649         .ops            = &clkops_omap2_dflt_wait,
2650         .parent         = &per_l4_ick,
2651         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2652         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2653         .clkdm_name     = "per_clkdm",
2654         .recalc         = &followparent_recalc,
2655 };
2656
2657 static struct clk gpt3_ick = {
2658         .name           = "gpt3_ick",
2659         .ops            = &clkops_omap2_dflt_wait,
2660         .parent         = &per_l4_ick,
2661         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2662         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2663         .clkdm_name     = "per_clkdm",
2664         .recalc         = &followparent_recalc,
2665 };
2666
2667 static struct clk gpt2_ick = {
2668         .name           = "gpt2_ick",
2669         .ops            = &clkops_omap2_dflt_wait,
2670         .parent         = &per_l4_ick,
2671         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2672         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2673         .clkdm_name     = "per_clkdm",
2674         .recalc         = &followparent_recalc,
2675 };
2676
2677 static struct clk mcbsp2_ick = {
2678         .name           = "mcbsp_ick",
2679         .ops            = &clkops_omap2_dflt_wait,
2680         .id             = 2,
2681         .parent         = &per_l4_ick,
2682         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2683         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2684         .clkdm_name     = "per_clkdm",
2685         .recalc         = &followparent_recalc,
2686 };
2687
2688 static struct clk mcbsp3_ick = {
2689         .name           = "mcbsp_ick",
2690         .ops            = &clkops_omap2_dflt_wait,
2691         .id             = 3,
2692         .parent         = &per_l4_ick,
2693         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2694         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2695         .clkdm_name     = "per_clkdm",
2696         .recalc         = &followparent_recalc,
2697 };
2698
2699 static struct clk mcbsp4_ick = {
2700         .name           = "mcbsp_ick",
2701         .ops            = &clkops_omap2_dflt_wait,
2702         .id             = 4,
2703         .parent         = &per_l4_ick,
2704         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2705         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2706         .clkdm_name     = "per_clkdm",
2707         .recalc         = &followparent_recalc,
2708 };
2709
2710 static const struct clksel mcbsp_234_clksel[] = {
2711         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2712         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2713         { .parent = NULL }
2714 };
2715
2716 static struct clk mcbsp2_fck = {
2717         .name           = "mcbsp_fck",
2718         .ops            = &clkops_omap2_dflt_wait,
2719         .id             = 2,
2720         .init           = &omap2_init_clksel_parent,
2721         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2722         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2723         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2724         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2725         .clksel         = mcbsp_234_clksel,
2726         .clkdm_name     = "per_clkdm",
2727         .recalc         = &omap2_clksel_recalc,
2728 };
2729
2730 static struct clk mcbsp3_fck = {
2731         .name           = "mcbsp_fck",
2732         .ops            = &clkops_omap2_dflt_wait,
2733         .id             = 3,
2734         .init           = &omap2_init_clksel_parent,
2735         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2736         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2737         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2738         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2739         .clksel         = mcbsp_234_clksel,
2740         .clkdm_name     = "per_clkdm",
2741         .recalc         = &omap2_clksel_recalc,
2742 };
2743
2744 static struct clk mcbsp4_fck = {
2745         .name           = "mcbsp_fck",
2746         .ops            = &clkops_omap2_dflt_wait,
2747         .id             = 4,
2748         .init           = &omap2_init_clksel_parent,
2749         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2750         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2751         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2752         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2753         .clksel         = mcbsp_234_clksel,
2754         .clkdm_name     = "per_clkdm",
2755         .recalc         = &omap2_clksel_recalc,
2756 };
2757
2758 /* EMU clocks */
2759
2760 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2761
2762 static const struct clksel_rate emu_src_sys_rates[] = {
2763         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2764         { .div = 0 },
2765 };
2766
2767 static const struct clksel_rate emu_src_core_rates[] = {
2768         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2769         { .div = 0 },
2770 };
2771
2772 static const struct clksel_rate emu_src_per_rates[] = {
2773         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2774         { .div = 0 },
2775 };
2776
2777 static const struct clksel_rate emu_src_mpu_rates[] = {
2778         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2779         { .div = 0 },
2780 };
2781
2782 static const struct clksel emu_src_clksel[] = {
2783         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2784         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2785         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2786         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2787         { .parent = NULL },
2788 };
2789
2790 /*
2791  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2792  * to switch the source of some of the EMU clocks.
2793  * XXX Are there CLKEN bits for these EMU clks?
2794  */
2795 static struct clk emu_src_ck = {
2796         .name           = "emu_src_ck",
2797         .ops            = &clkops_null,
2798         .init           = &omap2_init_clksel_parent,
2799         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2800         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2801         .clksel         = emu_src_clksel,
2802         .clkdm_name     = "emu_clkdm",
2803         .recalc         = &omap2_clksel_recalc,
2804 };
2805
2806 static const struct clksel_rate pclk_emu_rates[] = {
2807         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2808         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2809         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2810         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2811         { .div = 0 },
2812 };
2813
2814 static const struct clksel pclk_emu_clksel[] = {
2815         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2816         { .parent = NULL },
2817 };
2818
2819 static struct clk pclk_fck = {
2820         .name           = "pclk_fck",
2821         .ops            = &clkops_null,
2822         .init           = &omap2_init_clksel_parent,
2823         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2824         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2825         .clksel         = pclk_emu_clksel,
2826         .clkdm_name     = "emu_clkdm",
2827         .recalc         = &omap2_clksel_recalc,
2828 };
2829
2830 static const struct clksel_rate pclkx2_emu_rates[] = {
2831         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2832         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2833         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2834         { .div = 0 },
2835 };
2836
2837 static const struct clksel pclkx2_emu_clksel[] = {
2838         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2839         { .parent = NULL },
2840 };
2841
2842 static struct clk pclkx2_fck = {
2843         .name           = "pclkx2_fck",
2844         .ops            = &clkops_null,
2845         .init           = &omap2_init_clksel_parent,
2846         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2847         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2848         .clksel         = pclkx2_emu_clksel,
2849         .clkdm_name     = "emu_clkdm",
2850         .recalc         = &omap2_clksel_recalc,
2851 };
2852
2853 static const struct clksel atclk_emu_clksel[] = {
2854         { .parent = &emu_src_ck, .rates = div2_rates },
2855         { .parent = NULL },
2856 };
2857
2858 static struct clk atclk_fck = {
2859         .name           = "atclk_fck",
2860         .ops            = &clkops_null,
2861         .init           = &omap2_init_clksel_parent,
2862         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2863         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2864         .clksel         = atclk_emu_clksel,
2865         .clkdm_name     = "emu_clkdm",
2866         .recalc         = &omap2_clksel_recalc,
2867 };
2868
2869 static struct clk traceclk_src_fck = {
2870         .name           = "traceclk_src_fck",
2871         .ops            = &clkops_null,
2872         .init           = &omap2_init_clksel_parent,
2873         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2874         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2875         .clksel         = emu_src_clksel,
2876         .clkdm_name     = "emu_clkdm",
2877         .recalc         = &omap2_clksel_recalc,
2878 };
2879
2880 static const struct clksel_rate traceclk_rates[] = {
2881         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2882         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2883         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2884         { .div = 0 },
2885 };
2886
2887 static const struct clksel traceclk_clksel[] = {
2888         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2889         { .parent = NULL },
2890 };
2891
2892 static struct clk traceclk_fck = {
2893         .name           = "traceclk_fck",
2894         .ops            = &clkops_null,
2895         .init           = &omap2_init_clksel_parent,
2896         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2897         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2898         .clksel         = traceclk_clksel,
2899         .clkdm_name     = "emu_clkdm",
2900         .recalc         = &omap2_clksel_recalc,
2901 };
2902
2903 /* SR clocks */
2904
2905 /* SmartReflex fclk (VDD1) */
2906 static struct clk sr1_fck = {
2907         .name           = "sr1_fck",
2908         .ops            = &clkops_omap2_dflt_wait,
2909         .parent         = &sys_ck,
2910         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2911         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2912         .recalc         = &followparent_recalc,
2913 };
2914
2915 /* SmartReflex fclk (VDD2) */
2916 static struct clk sr2_fck = {
2917         .name           = "sr2_fck",
2918         .ops            = &clkops_omap2_dflt_wait,
2919         .parent         = &sys_ck,
2920         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2921         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
2922         .recalc         = &followparent_recalc,
2923 };
2924
2925 static struct clk sr_l4_ick = {
2926         .name           = "sr_l4_ick",
2927         .ops            = &clkops_null, /* RMK: missing? */
2928         .parent         = &l4_ick,
2929         .clkdm_name     = "core_l4_clkdm",
2930         .recalc         = &followparent_recalc,
2931 };
2932
2933 /* SECURE_32K_FCK clocks */
2934
2935 static struct clk gpt12_fck = {
2936         .name           = "gpt12_fck",
2937         .ops            = &clkops_null,
2938         .parent         = &secure_32k_fck,
2939         .recalc         = &followparent_recalc,
2940 };
2941
2942 static struct clk wdt1_fck = {
2943         .name           = "wdt1_fck",
2944         .ops            = &clkops_null,
2945         .parent         = &secure_32k_fck,
2946         .recalc         = &followparent_recalc,
2947 };
2948
2949 #endif