2 * OMAP3-specific clock framework functions
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>
22 #include <linux/list.h>
23 #include <linux/errno.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
27 #include <linux/limits.h>
29 #include <mach/clock.h>
30 #include <mach/sram.h>
31 #include <asm/div64.h>
32 #include <asm/bitops.h>
34 #include <mach/sdrc.h>
36 #include "clock34xx.h"
38 #include "prm-regbits-34xx.h"
40 #include "cm-regbits-34xx.h"
42 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
43 #define DPLL_AUTOIDLE_DISABLE 0x0
44 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
46 #define MAX_DPLL_WAIT_TRIES 1000000
49 * omap3_dpll_recalc - recalculate DPLL rate
50 * @clk: DPLL struct clk
52 * Recalculate and propagate the DPLL rate.
54 static void omap3_dpll_recalc(struct clk *clk)
56 clk->rate = omap2_get_dpll_rate(clk);
61 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
62 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
64 const struct dpll_data *dd;
69 v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
70 v &= ~dd->enable_mask;
71 v |= clken_bits << __ffs(dd->enable_mask);
72 cm_write_mod_reg(v, clk->prcm_mod, dd->control_reg);
75 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
76 static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
78 const struct dpll_data *dd;
84 state <<= __ffs(dd->idlest_mask);
86 while (((cm_read_mod_reg(clk->prcm_mod, dd->idlest_reg)
87 & dd->idlest_mask) != state) &&
88 i < MAX_DPLL_WAIT_TRIES) {
93 if (i == MAX_DPLL_WAIT_TRIES) {
94 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
95 clk->name, (state) ? "locked" : "bypassed");
97 pr_debug("clock: %s transition to '%s' in %d loops\n",
98 clk->name, (state) ? "locked" : "bypassed", i);
106 /* From 3430 TRM ES2 4.7.6.2 */
107 static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
112 fint = clk->parent->rate / (n + 1);
114 pr_debug("clock: fint is %lu\n", fint);
116 if (fint >= 750000 && fint <= 1000000)
118 else if (fint > 1000000 && fint <= 1250000)
120 else if (fint > 1250000 && fint <= 1500000)
122 else if (fint > 1500000 && fint <= 1750000)
124 else if (fint > 1750000 && fint <= 2100000)
126 else if (fint > 7500000 && fint <= 10000000)
128 else if (fint > 10000000 && fint <= 12500000)
130 else if (fint > 12500000 && fint <= 15000000)
132 else if (fint > 15000000 && fint <= 17500000)
134 else if (fint > 17500000 && fint <= 21000000)
137 pr_debug("clock: unknown freqsel setting for %d\n", n);
142 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
145 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
146 * @clk: pointer to a DPLL struct clk
148 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
149 * readiness before returning. Will save and restore the DPLL's
150 * autoidle state across the enable, per the CDP code. If the DPLL
151 * locked successfully, return 0; if the DPLL did not lock in the time
152 * allotted, or DPLL3 was passed in, return -EINVAL.
154 static int _omap3_noncore_dpll_lock(struct clk *clk)
159 if (clk == &dpll3_ck)
162 pr_debug("clock: locking DPLL %s\n", clk->name);
164 ai = omap3_dpll_autoidle_read(clk);
166 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
170 * If no downstream clocks are enabled, CM_IDLEST bit
171 * may never become active, so don't wait for DPLL to lock.
174 omap3_dpll_allow_idle(clk);
176 r = _omap3_wait_dpll_status(clk, 1);
177 omap3_dpll_deny_idle(clk);
184 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
185 * @clk: pointer to a DPLL struct clk
187 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
188 * bypass mode, the DPLL's rate is set equal to its parent clock's
189 * rate. Waits for the DPLL to report readiness before returning.
190 * Will save and restore the DPLL's autoidle state across the enable,
191 * per the CDP code. If the DPLL entered bypass mode successfully,
192 * return 0; if the DPLL did not enter bypass in the time allotted, or
193 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
196 static int _omap3_noncore_dpll_bypass(struct clk *clk)
201 if (clk == &dpll3_ck)
204 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
207 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
210 ai = omap3_dpll_autoidle_read(clk);
212 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
214 r = _omap3_wait_dpll_status(clk, 0);
217 omap3_dpll_allow_idle(clk);
219 omap3_dpll_deny_idle(clk);
225 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
226 * @clk: pointer to a DPLL struct clk
228 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
229 * restore the DPLL's autoidle state across the stop, per the CDP
230 * code. If DPLL3 was passed in, or the DPLL does not support
231 * low-power stop, return -EINVAL; otherwise, return 0.
233 static int _omap3_noncore_dpll_stop(struct clk *clk)
237 if (clk == &dpll3_ck)
240 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
243 pr_debug("clock: stopping DPLL %s\n", clk->name);
245 ai = omap3_dpll_autoidle_read(clk);
247 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
250 omap3_dpll_allow_idle(clk);
252 omap3_dpll_deny_idle(clk);
258 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
259 * @clk: pointer to a DPLL struct clk
261 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
262 * The choice of modes depends on the DPLL's programmed rate: if it is
263 * the same as the DPLL's parent clock, it will enter bypass;
264 * otherwise, it will enter lock. This code will wait for the DPLL to
265 * indicate readiness before returning, unless the DPLL takes too long
266 * to enter the target state. Intended to be used as the struct clk's
267 * enable function. If DPLL3 was passed in, or the DPLL does not
268 * support low-power stop, or if the DPLL took too long to enter
269 * bypass or lock, return -EINVAL; otherwise, return 0.
271 static int omap3_noncore_dpll_enable(struct clk *clk)
274 struct dpll_data *dd;
277 if (clk == &dpll3_ck)
284 rate = omap2_get_dpll_rate(clk);
286 if (dd->bypass_clk->rate == rate)
287 r = _omap3_noncore_dpll_bypass(clk);
289 r = _omap3_noncore_dpll_lock(clk);
292 clk->rate = omap2_get_dpll_rate(clk);
298 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
299 * @clk: pointer to a DPLL struct clk
301 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
302 * The choice of modes depends on the DPLL's programmed rate: if it is
303 * the same as the DPLL's parent clock, it will enter bypass;
304 * otherwise, it will enter lock. This code will wait for the DPLL to
305 * indicate readiness before returning, unless the DPLL takes too long
306 * to enter the target state. Intended to be used as the struct clk's
307 * enable function. If DPLL3 was passed in, or the DPLL does not
308 * support low-power stop, or if the DPLL took too long to enter
309 * bypass or lock, return -EINVAL; otherwise, return 0.
311 static void omap3_noncore_dpll_disable(struct clk *clk)
313 if (clk == &dpll3_ck)
316 _omap3_noncore_dpll_stop(clk);
320 /* Non-CORE DPLL rate set code */
323 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
324 * @clk: struct clk * of DPLL to set
325 * @m: DPLL multiplier to set
326 * @n: DPLL divider to set
327 * @freqsel: FREQSEL value to set
329 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
330 * lock.. Returns -EINVAL upon error, or 0 upon success.
332 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
334 struct dpll_data *dd;
345 * According to the 12-5 CDP code from TI, "Limitation 2.5"
346 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
349 if (system_rev == OMAP3430_REV_ES1_0 &&
350 !strcmp("dpll4_ck", clk->name)) {
351 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
352 "silicon 'Limitation 2.5' on 3430ES1.\n");
356 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
357 _omap3_noncore_dpll_bypass(clk);
359 /* Set jitter correction */
360 v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
361 v &= ~dd->freqsel_mask;
362 v |= freqsel << __ffs(dd->freqsel_mask);
363 cm_write_mod_reg(v, clk->prcm_mod, dd->control_reg);
365 /* Set DPLL multiplier, divider */
366 v = cm_read_mod_reg(clk->prcm_mod, dd->mult_div1_reg);
367 v &= ~(dd->mult_mask | dd->div1_mask);
368 v |= m << __ffs(dd->mult_mask);
369 v |= (n - 1) << __ffs(dd->div1_mask);
370 cm_write_mod_reg(v, clk->prcm_mod, dd->mult_div1_reg);
372 /* We let the clock framework set the other output dividers later */
374 /* REVISIT: Set ramp-up delay? */
376 _omap3_noncore_dpll_lock(clk);
382 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
383 * @clk: struct clk * of DPLL to set
384 * @rate: rounded target rate
386 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
387 * low-power bypass, and the target rate is the bypass source clock
388 * rate, then configure the DPLL for bypass. Otherwise, round the
389 * target rate if it hasn't been done already, then program and lock
390 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
392 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
395 struct dpll_data *dd;
405 if (rate == omap2_get_dpll_rate(clk))
408 if (dd->bypass_clk->rate == rate &&
409 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
411 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
413 ret = _omap3_noncore_dpll_bypass(clk);
419 if (dd->last_rounded_rate != rate)
420 omap2_dpll_round_rate(clk, rate);
422 if (dd->last_rounded_rate == 0)
425 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
429 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
432 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
433 dd->last_rounded_n, freqsel);
440 omap3_dpll_recalc(clk);
447 * CORE DPLL (DPLL3) rate programming functions
449 * These call into SRAM code to do the actual CM writes, since the SDRAM
450 * is clocked from DPLL3.
454 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
455 * @clk: struct clk * of DPLL to set
456 * @rate: rounded target rate
458 * Program the DPLL M2 divider with the rounded target rate. Returns
459 * -EINVAL upon error, or 0 upon success.
461 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
464 unsigned long validrate, sdrcrate;
465 struct omap_sdrc_params *sp;
470 if (clk != &dpll3_m2_ck)
473 if (rate == clk->rate)
476 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
477 if (validrate != rate)
480 sdrcrate = sdrc_ick.rate;
481 if (rate > clk->rate)
482 sdrcrate <<= ((rate / clk->rate) - 1);
484 sdrcrate >>= ((clk->rate / rate) - 1);
486 sp = omap2_sdrc_get_params(sdrcrate);
490 pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
492 pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
493 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
495 /* REVISIT: SRAM code doesn't support other M2 divisors yet */
496 WARN_ON(new_div != 1 && new_div != 2);
498 /* REVISIT: Add SDRC_MR changing to this code also */
500 omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
501 sp->actim_ctrlb, new_div);
504 omap2_clksel_recalc(clk);
510 /* DPLL autoidle read/set code */
514 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
515 * @clk: struct clk * of the DPLL to read
517 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
518 * -EINVAL if passed a null pointer or if the struct clk does not
519 * appear to refer to a DPLL.
521 static u32 omap3_dpll_autoidle_read(struct clk *clk)
523 const struct dpll_data *dd;
526 if (!clk || !clk->dpll_data)
531 v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg);
532 v &= dd->autoidle_mask;
533 v >>= __ffs(dd->autoidle_mask);
539 * omap3_dpll_allow_idle - enable DPLL autoidle bits
540 * @clk: struct clk * of the DPLL to operate on
542 * Enable DPLL automatic idle control. This automatic idle mode
543 * switching takes effect only when the DPLL is locked, at least on
544 * OMAP3430. The DPLL will enter low-power stop when its downstream
545 * clocks are gated. No return value.
547 static void omap3_dpll_allow_idle(struct clk *clk)
549 const struct dpll_data *dd;
552 if (!clk || !clk->dpll_data)
558 * REVISIT: CORE DPLL can optionally enter low-power bypass
559 * by writing 0x5 instead of 0x1. Add some mechanism to
560 * optionally enter this mode.
562 v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg);
563 v &= ~dd->autoidle_mask;
564 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
565 cm_write_mod_reg(v, clk->prcm_mod, dd->autoidle_reg);
569 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
570 * @clk: struct clk * of the DPLL to operate on
572 * Disable DPLL automatic idle control. No return value.
574 static void omap3_dpll_deny_idle(struct clk *clk)
576 const struct dpll_data *dd;
579 if (!clk || !clk->dpll_data)
584 v = cm_read_mod_reg(clk->prcm_mod, dd->autoidle_reg);
585 v &= ~dd->autoidle_mask;
586 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
587 cm_write_mod_reg(v, clk->prcm_mod, dd->autoidle_reg);
590 /* Clock control for DPLL outputs */
593 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
594 * @clk: DPLL output struct clk
596 * Using parent clock DPLL data, look up DPLL state. If locked, set our
597 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
599 static void omap3_clkoutx2_recalc(struct clk *clk)
601 const struct dpll_data *dd;
605 /* Walk up the parents of clk, looking for a DPLL */
607 while (pclk && !pclk->dpll_data)
610 /* clk does not have a DPLL as a parent? */
613 dd = pclk->dpll_data;
615 WARN_ON(!dd->idlest_reg || !dd->idlest_mask);
617 v = cm_read_mod_reg(pclk->prcm_mod, dd->idlest_reg) & dd->idlest_mask;
619 clk->rate = clk->parent->rate;
621 clk->rate = clk->parent->rate * 2;
623 if (clk->flags & RATE_PROPAGATES)
627 /* Common clock code */
630 * As it is structured now, this will prevent an OMAP2/3 multiboot
631 * kernel from compiling. This will need further attention.
633 #if defined(CONFIG_ARCH_OMAP3)
635 static struct clk_functions omap2_clk_functions = {
636 .clk_enable = omap2_clk_enable,
637 .clk_disable = omap2_clk_disable,
638 .clk_round_rate = omap2_clk_round_rate,
639 .clk_set_rate = omap2_clk_set_rate,
640 .clk_set_parent = omap2_clk_set_parent,
641 .clk_disable_unused = omap2_clk_disable_unused,
645 * Set clocks for bypass mode for reboot to work.
647 void omap2_clk_prepare_for_reboot(void)
649 /* REVISIT: Not ready for 343x */
653 if (vclk == NULL || sclk == NULL)
656 rate = clk_get_rate(sclk);
657 clk_set_rate(vclk, rate);
661 /* REVISIT: Move this init stuff out into clock.c */
664 * Switch the MPU rate if specified on cmdline.
665 * We cannot do this early until cmdline is parsed.
667 static int __init omap2_clk_arch_init(void)
672 /* REVISIT: not yet ready for 343x */
674 if (omap2_select_table_rate(&virt_prcm_set, mpurate))
675 printk(KERN_ERR "Could not find matching MPU rate\n");
678 recalculate_root_clocks();
680 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
681 "%ld.%01ld/%ld/%ld MHz\n",
682 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
683 (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
687 arch_initcall(omap2_clk_arch_init);
689 int __init omap2_clk_init(void)
691 /* struct prcm_config *prcm; */
696 /* REVISIT: Ultimately this will be used for multiboot */
698 if (cpu_is_omap242x()) {
699 cpu_mask = RATE_IN_242X;
700 cpu_clkflg = CLOCK_IN_OMAP242X;
701 clkp = onchip_24xx_clks;
702 } else if (cpu_is_omap2430()) {
703 cpu_mask = RATE_IN_243X;
704 cpu_clkflg = CLOCK_IN_OMAP243X;
705 clkp = onchip_24xx_clks;
708 if (cpu_is_omap34xx()) {
709 cpu_mask = RATE_IN_343X;
710 cpu_clkflg = CLOCK_IN_OMAP343X;
711 clkp = onchip_34xx_clks;
714 * Update this if there are further clock changes between ES2
715 * and production parts
717 if (system_rev == OMAP3430_REV_ES1_0) {
718 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
719 cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
721 cpu_mask |= RATE_IN_3430ES2;
722 cpu_clkflg |= CLOCK_IN_OMAP3430ES2;
726 clk_init(&omap2_clk_functions);
728 for (clkp = onchip_34xx_clks;
729 clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
731 if ((*clkp)->flags & cpu_clkflg) {
733 omap2_init_clk_clkdm(*clkp);
737 /* REVISIT: Not yet ready for OMAP3 */
739 /* Check the MPU rate set by bootloader */
740 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
741 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
742 if (!(prcm->flags & cpu_mask))
744 if (prcm->xtal_speed != sys_ck.rate)
746 if (prcm->dpll_speed <= clkrate)
749 curr_prcm_set = prcm;
752 recalculate_root_clocks();
754 printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
755 "%ld.%01ld/%ld/%ld MHz\n",
756 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
757 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
760 * Only enable those clocks we will need, let the drivers
761 * enable other clocks as necessary
763 clk_enable_init_clocks();
765 /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
766 /* REVISIT: not yet ready for 343x */
768 vclk = clk_get(NULL, "virt_prcm_set");
769 sclk = clk_get(NULL, "sys_ck");