arch/arm/mach-omap2/clock34xx.c

   1 /*
   2  * OMAP3-specific clock framework functions
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2009 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * Testing and integration fixes by Jouni Högander
   9  *
  10  * Parts of this code are based on code written by
  11  * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17 #undef DEBUG
  18
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/device.h>
  22 #include <linux/list.h>
  23 #include <linux/errno.h>
  24 #include <linux/delay.h>
  25 #include <linux/clk.h>
  26 #include <linux/io.h>
  27 #include <linux/limits.h>
  28 #include <linux/bitops.h>
  29
  30 #include <mach/clock.h>
  31 #include <mach/sram.h>
  32 #include <asm/div64.h>
  33 #include <asm/clkdev.h>
  34
  35 #include <mach/sdrc.h>
  36 #include "clock.h"
  37 #include "prm.h"
  38 #include "prm-regbits-34xx.h"
  39 #include "cm.h"
  40 #include "cm-regbits-34xx.h"
  41
  42 static const struct clkops clkops_noncore_dpll_ops;
  43
  44 static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
  45                                             void __iomem **idlest_reg,
  46                                             u8 *idlest_bit);
  47 static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
  48                                             void __iomem **idlest_reg,
  49                                             u8 *idlest_bit);
  50 static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
  51                                                     void __iomem **idlest_reg,
  52                                                     u8 *idlest_bit);
  53
  54 static const struct clkops clkops_omap3430es2_ssi_wait = {
  55         .enable         = omap2_dflt_clk_enable,
  56         .disable        = omap2_dflt_clk_disable,
  57         .find_idlest    = omap3430es2_clk_ssi_find_idlest,
  58         .find_companion = omap2_clk_dflt_find_companion,
  59 };
  60
  61 static const struct clkops clkops_omap3430es2_hsotgusb_wait = {
  62         .enable         = omap2_dflt_clk_enable,
  63         .disable        = omap2_dflt_clk_disable,
  64         .find_idlest    = omap3430es2_clk_hsotgusb_find_idlest,
  65         .find_companion = omap2_clk_dflt_find_companion,
  66 };
  67
  68 static const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
  69         .enable         = omap2_dflt_clk_enable,
  70         .disable        = omap2_dflt_clk_disable,
  71         .find_idlest    = omap3430es2_clk_dss_usbhost_find_idlest,
  72         .find_companion = omap2_clk_dflt_find_companion,
  73 };
  74
  75 #include "clock34xx.h"
  76
  77 struct omap_clk {
  78         u32             cpu;
  79         struct clk_lookup lk;
  80 };
  81
  82 #define CLK(dev, con, ck, cp)           \
  83         {                               \
  84                  .cpu = cp,             \
  85                 .lk = {                 \
  86                         .dev_id = dev,  \
  87                         .con_id = con,  \
  88                         .clk = ck,      \
  89                 },                      \
  90         }
  91
  92 #define CK_343X         (1 << 0)
  93 #define CK_3430ES1      (1 << 1)
  94 #define CK_3430ES2      (1 << 2)
  95
  96 static struct omap_clk omap34xx_clks[] = {
  97         CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_343X),
  98         CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_343X),
  99         CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_343X),
 100         CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
 101         CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
 102         CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_343X),
 103         CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
 104         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_343X),
 105         CLK(NULL,       "sys_ck",       &sys_ck,        CK_343X),
 106         CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_343X),
 107         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_343X),
 108         CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_343X),
 109         CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_343X),
 110         CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_343X),
 111         CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
 112         CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_343X),
 113         CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_343X),
 114         CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_343X),
 115         CLK(NULL,       "core_ck",      &core_ck,       CK_343X),
 116         CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_343X),
 117         CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_343X),
 118         CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
 119         CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_343X),
 120         CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
 121         CLK(NULL,       "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
 122         CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_343X),
 123         CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_343X),
 124         CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
 125         CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_343X),
 126         CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_343X),
 127         CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_343X),
 128         CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_343X),
 129         CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_343X),
 130         CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_343X),
 131         CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
 132         CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_343X),
 133         CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
 134         CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_343X),
 135         CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
 136         CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_343X),
 137         CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
 138         CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_343X),
 139         CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
 140         CLK(NULL,       "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
 141         CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2),
 142         CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2),
 143         CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_343X),
 144         CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_343X),
 145         CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_343X),
 146         CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_343X),
 147         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_343X),
 148         CLK(NULL,       "arm_fck",      &arm_fck,       CK_343X),
 149         CLK(NULL,       "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
 150         CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_343X),
 151         CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_343X),
 152         CLK(NULL,       "l3_ick",       &l3_ick,        CK_343X),
 153         CLK(NULL,       "l4_ick",       &l4_ick,        CK_343X),
 154         CLK(NULL,       "rm_ick",       &rm_ick,        CK_343X),
 155         CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
 156         CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
 157         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
 158         CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
 159         CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
 160         CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2),
 161         CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2),
 162         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
 163         CLK(NULL,       "modem_fck",    &modem_fck,     CK_343X),
 164         CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_343X),
 165         CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_343X),
 166         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_343X),
 167         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_343X),
 168         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2),
 169         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2),
 170         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2),
 171         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_343X),
 172         CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2),
 173         CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_343X),
 174         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_343X),
 175         CLK("mmci-omap-hs.0",   "fck",  &mmchs1_fck,    CK_343X),
 176         CLK("i2c_omap.3", "fck",        &i2c3_fck,      CK_343X),
 177         CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_343X),
 178         CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_343X),
 179         CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_343X),
 180         CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_343X),
 181         CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_343X),
 182         CLK("omap2_mcspi.4", "fck",     &mcspi4_fck,    CK_343X),
 183         CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_343X),
 184         CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_343X),
 185         CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_343X),
 186         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_343X),
 187         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_343X),
 188         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
 189         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_343X),
 190         CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_343X),
 191         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
 192         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2),
 193         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
 194         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2),
 195         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_343X),
 196         CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
 197         CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2),
 198         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_343X),
 199         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_343X),
 200         CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_343X),
 201         CLK(NULL,       "pka_ick",      &pka_ick,       CK_343X),
 202         CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_343X),
 203         CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2),
 204         CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2),
 205         CLK(NULL,       "icr_ick",      &icr_ick,       CK_343X),
 206         CLK(NULL,       "aes2_ick",     &aes2_ick,      CK_343X),
 207         CLK(NULL,       "sha12_ick",    &sha12_ick,     CK_343X),
 208         CLK(NULL,       "des2_ick",     &des2_ick,      CK_343X),
 209         CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_343X),
 210         CLK("mmci-omap-hs.0",   "ick",  &mmchs1_ick,    CK_343X),
 211         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_343X),
 212         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_343X),
 213         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_343X),
 214         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_343X),
 215         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_343X),
 216         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_343X),
 217         CLK("i2c_omap.3", "ick",        &i2c3_ick,      CK_343X),
 218         CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_343X),
 219         CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_343X),
 220         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_343X),
 221         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_343X),
 222         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_343X),
 223         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_343X),
 224         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_343X),
 225         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_343X),
 226         CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
 227         CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_343X),
 228         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_343X),
 229         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_343X),
 230         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
 231         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2),
 232         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
 233         CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_343X),
 234         CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_343X),
 235         CLK("omap_rng", "ick",          &rng_ick,       CK_343X),
 236         CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
 237         CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
 238         CLK("omapfb",   "dss1_fck",     &dss1_alwon_fck_3430es1, CK_3430ES1),
 239         CLK("omapfb",   "dss1_fck",     &dss1_alwon_fck_3430es2, CK_3430ES2),
 240         CLK("omapfb",   "tv_fck",       &dss_tv_fck,    CK_343X),
 241         CLK("omapfb",   "video_fck",    &dss_96m_fck,   CK_343X),
 242         CLK("omapfb",   "dss2_fck",     &dss2_alwon_fck, CK_343X),
 243         CLK("omapfb",   "ick",          &dss_ick_3430es1,       CK_3430ES1),
 244         CLK("omapfb",   "ick",          &dss_ick_3430es2,       CK_3430ES2),
 245         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
 246         CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
 247         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
 248         CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
 249         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
 250         CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2),
 251         CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2),
 252         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_343X),
 253         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_343X),
 254         CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_343X),
 255         CLK("omap_wdt", "fck",          &wdt2_fck,      CK_343X),
 256         CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_343X),
 257         CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2),
 258         CLK("omap_wdt", "ick",          &wdt2_ick,      CK_343X),
 259         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_343X),
 260         CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_343X),
 261         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
 262         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_343X),
 263         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_343X),
 264         CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_343X),
 265         CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_343X),
 266         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_343X),
 267         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_343X),
 268         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_343X),
 269         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_343X),
 270         CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_343X),
 271         CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_343X),
 272         CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_343X),
 273         CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_343X),
 274         CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_343X),
 275         CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
 276         CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_343X),
 277         CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_343X),
 278         CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_343X),
 279         CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_343X),
 280         CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_343X),
 281         CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_343X),
 282         CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_343X),
 283         CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_343X),
 284         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_343X),
 285         CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_343X),
 286         CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_343X),
 287         CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_343X),
 288         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_343X),
 289         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_343X),
 290         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_343X),
 291         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_343X),
 292         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_343X),
 293         CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_343X),
 294         CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_343X),
 295         CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_343X),
 296         CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_343X),
 297         CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_343X),
 298         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_343X),
 299         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_343X),
 300         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_343X),
 301         CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_343X),
 302         CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_343X),
 303         CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_343X),
 304         CLK(NULL,       "emu_src_ck",   &emu_src_ck,    CK_343X),
 305         CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_343X),
 306         CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_343X),
 307         CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_343X),
 308         CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_343X),
 309         CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_343X),
 310         CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_343X),
 311         CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_343X),
 312         CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_343X),
 313         CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_343X),
 314         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_343X),
 315         CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_343X),
 316 };
 317
 318 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
 319 #define DPLL_AUTOIDLE_DISABLE                   0x0
 320 #define DPLL_AUTOIDLE_LOW_POWER_STOP            0x1
 321
 322 #define MAX_DPLL_WAIT_TRIES             1000000
 323
 324 #define MIN_SDRC_DLL_LOCK_FREQ          83000000
 325
 326 #define CYCLES_PER_MHZ                  1000000
 327
 328 /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
 329 #define SDRC_MPURATE_SCALE              8
 330
 331 /* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
 332 #define SDRC_MPURATE_BASE_SHIFT         9
 333
 334 /*
 335  * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
 336  * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
 337  */
 338 #define SDRC_MPURATE_LOOPS              96
 339
 340 /**
 341  * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
 342  * @clk: struct clk * being enabled
 343  * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
 344  * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
 345  *
 346  * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
 347  * from the CM_{I,F}CLKEN bit.  Pass back the correct info via
 348  * @idlest_reg and @idlest_bit.  No return value.
 349  */
 350 static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
 351                                             void __iomem **idlest_reg,
 352                                             u8 *idlest_bit)
 353 {
 354         u32 r;
 355
 356         r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
 357         *idlest_reg = (__force void __iomem *)r;
 358         *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
 359 }
 360
 361 /**
 362  * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
 363  * @clk: struct clk * being enabled
 364  * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
 365  * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
 366  *
 367  * Some OMAP modules on OMAP3 ES2+ chips have both initiator and
 368  * target IDLEST bits.  For our purposes, we are concerned with the
 369  * target IDLEST bits, which exist at a different bit position than
 370  * the *CLKEN bit position for these modules (DSS and USBHOST) (The
 371  * default find_idlest code assumes that they are at the same
 372  * position.)  No return value.
 373  */
 374 static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
 375                                                     void __iomem **idlest_reg,
 376                                                     u8 *idlest_bit)
 377 {
 378         u32 r;
 379
 380         r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
 381         *idlest_reg = (__force void __iomem *)r;
 382         /* USBHOST_IDLE has same shift */
 383         *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
 384 }
 385
 386 /**
 387  * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
 388  * @clk: struct clk * being enabled
 389  * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
 390  * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
 391  *
 392  * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
 393  * shift from the CM_{I,F}CLKEN bit.  Pass back the correct info via
 394  * @idlest_reg and @idlest_bit.  No return value.
 395  */
 396 static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
 397                                                  void __iomem **idlest_reg,
 398                                                  u8 *idlest_bit)
 399 {
 400         u32 r;
 401
 402         r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
 403         *idlest_reg = (__force void __iomem *)r;
 404         *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
 405 }
 406
 407 /**
 408  * omap3_dpll_recalc - recalculate DPLL rate
 409  * @clk: DPLL struct clk
 410  *
 411  * Recalculate and propagate the DPLL rate.
 412  */
 413 static unsigned long omap3_dpll_recalc(struct clk *clk)
 414 {
 415         return omap2_get_dpll_rate(clk);
 416 }
 417
 418 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
 419 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
 420 {
 421         const struct dpll_data *dd;
 422         u32 v;
 423
 424         dd = clk->dpll_data;
 425
 426         v = __raw_readl(dd->control_reg);
 427         v &= ~dd->enable_mask;
 428         v |= clken_bits << __ffs(dd->enable_mask);
 429         __raw_writel(v, dd->control_reg);
 430 }
 431
 432 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
 433 static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
 434 {
 435         const struct dpll_data *dd;
 436         int i = 0;
 437         int ret = -EINVAL;
 438
 439         dd = clk->dpll_data;
 440
 441         state <<= __ffs(dd->idlest_mask);
 442
 443         while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
 444                i < MAX_DPLL_WAIT_TRIES) {
 445                 i++;
 446                 udelay(1);
 447         }
 448
 449         if (i == MAX_DPLL_WAIT_TRIES) {
 450                 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
 451                        clk->name, (state) ? "locked" : "bypassed");
 452         } else {
 453                 pr_debug("clock: %s transition to '%s' in %d loops\n",
 454                          clk->name, (state) ? "locked" : "bypassed", i);
 455
 456                 ret = 0;
 457         }
 458
 459         return ret;
 460 }
 461
 462 /* From 3430 TRM ES2 4.7.6.2 */
 463 static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
 464 {
 465         unsigned long fint;
 466         u16 f = 0;
 467
 468         fint = clk->dpll_data->clk_ref->rate / (n + 1);
 469
 470         pr_debug("clock: fint is %lu\n", fint);
 471
 472         if (fint >= 750000 && fint <= 1000000)
 473                 f = 0x3;
 474         else if (fint > 1000000 && fint <= 1250000)
 475                 f = 0x4;
 476         else if (fint > 1250000 && fint <= 1500000)
 477                 f = 0x5;
 478         else if (fint > 1500000 && fint <= 1750000)
 479                 f = 0x6;
 480         else if (fint > 1750000 && fint <= 2100000)
 481                 f = 0x7;
 482         else if (fint > 7500000 && fint <= 10000000)
 483                 f = 0xB;
 484         else if (fint > 10000000 && fint <= 12500000)
 485                 f = 0xC;
 486         else if (fint > 12500000 && fint <= 15000000)
 487                 f = 0xD;
 488         else if (fint > 15000000 && fint <= 17500000)
 489                 f = 0xE;
 490         else if (fint > 17500000 && fint <= 21000000)
 491                 f = 0xF;
 492         else
 493                 pr_debug("clock: unknown freqsel setting for %d\n", n);
 494
 495         return f;
 496 }
 497
 498 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
 499
 500 /*
 501  * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
 502  * @clk: pointer to a DPLL struct clk
 503  *
 504  * Instructs a non-CORE DPLL to lock.  Waits for the DPLL to report
 505  * readiness before returning.  Will save and restore the DPLL's
 506  * autoidle state across the enable, per the CDP code.  If the DPLL
 507  * locked successfully, return 0; if the DPLL did not lock in the time
 508  * allotted, or DPLL3 was passed in, return -EINVAL.
 509  */
 510 static int _omap3_noncore_dpll_lock(struct clk *clk)
 511 {
 512         u8 ai;
 513         int r;
 514
 515         if (clk == &dpll3_ck)
 516                 return -EINVAL;
 517
 518         pr_debug("clock: locking DPLL %s\n", clk->name);
 519
 520         ai = omap3_dpll_autoidle_read(clk);
 521
 522         omap3_dpll_deny_idle(clk);
 523
 524         _omap3_dpll_write_clken(clk, DPLL_LOCKED);
 525
 526         r = _omap3_wait_dpll_status(clk, 1);
 527
 528         if (ai)
 529                 omap3_dpll_allow_idle(clk);
 530
 531         return r;
 532 }
 533
 534 /*
 535  * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
 536  * @clk: pointer to a DPLL struct clk
 537  *
 538  * Instructs a non-CORE DPLL to enter low-power bypass mode.  In
 539  * bypass mode, the DPLL's rate is set equal to its parent clock's
 540  * rate.  Waits for the DPLL to report readiness before returning.
 541  * Will save and restore the DPLL's autoidle state across the enable,
 542  * per the CDP code.  If the DPLL entered bypass mode successfully,
 543  * return 0; if the DPLL did not enter bypass in the time allotted, or
 544  * DPLL3 was passed in, or the DPLL does not support low-power bypass,
 545  * return -EINVAL.
 546  */
 547 static int _omap3_noncore_dpll_bypass(struct clk *clk)
 548 {
 549         int r;
 550         u8 ai;
 551
 552         if (clk == &dpll3_ck)
 553                 return -EINVAL;
 554
 555         if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
 556                 return -EINVAL;
 557
 558         pr_debug("clock: configuring DPLL %s for low-power bypass\n",
 559                  clk->name);
 560
 561         ai = omap3_dpll_autoidle_read(clk);
 562
 563         _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
 564
 565         r = _omap3_wait_dpll_status(clk, 0);
 566
 567         if (ai)
 568                 omap3_dpll_allow_idle(clk);
 569         else
 570                 omap3_dpll_deny_idle(clk);
 571
 572         return r;
 573 }
 574
 575 /*
 576  * _omap3_noncore_dpll_stop - instruct a DPLL to stop
 577  * @clk: pointer to a DPLL struct clk
 578  *
 579  * Instructs a non-CORE DPLL to enter low-power stop. Will save and
 580  * restore the DPLL's autoidle state across the stop, per the CDP
 581  * code.  If DPLL3 was passed in, or the DPLL does not support
 582  * low-power stop, return -EINVAL; otherwise, return 0.
 583  */
 584 static int _omap3_noncore_dpll_stop(struct clk *clk)
 585 {
 586         u8 ai;
 587
 588         if (clk == &dpll3_ck)
 589                 return -EINVAL;
 590
 591         if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
 592                 return -EINVAL;
 593
 594         pr_debug("clock: stopping DPLL %s\n", clk->name);
 595
 596         ai = omap3_dpll_autoidle_read(clk);
 597
 598         _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
 599
 600         if (ai)
 601                 omap3_dpll_allow_idle(clk);
 602         else
 603                 omap3_dpll_deny_idle(clk);
 604
 605         return 0;
 606 }
 607
 608 /**
 609  * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
 610  * @clk: pointer to a DPLL struct clk
 611  *
 612  * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
 613  * The choice of modes depends on the DPLL's programmed rate: if it is
 614  * the same as the DPLL's parent clock, it will enter bypass;
 615  * otherwise, it will enter lock.  This code will wait for the DPLL to
 616  * indicate readiness before returning, unless the DPLL takes too long
 617  * to enter the target state.  Intended to be used as the struct clk's
 618  * enable function.  If DPLL3 was passed in, or the DPLL does not
 619  * support low-power stop, or if the DPLL took too long to enter
 620  * bypass or lock, return -EINVAL; otherwise, return 0.
 621  */
 622 static int omap3_noncore_dpll_enable(struct clk *clk)
 623 {
 624         int r;
 625         struct dpll_data *dd;
 626
 627         if (clk == &dpll3_ck)
 628                 return -EINVAL;
 629
 630         dd = clk->dpll_data;
 631         if (!dd)
 632                 return -EINVAL;
 633
 634         if (clk->rate == dd->clk_bypass->rate) {
 635                 WARN_ON(clk->parent != dd->clk_bypass);
 636                 r = _omap3_noncore_dpll_bypass(clk);
 637         } else {
 638                 WARN_ON(clk->parent != dd->clk_ref);
 639                 r = _omap3_noncore_dpll_lock(clk);
 640         }
 641         /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */
 642         if (!r)
 643                 clk->rate = omap2_get_dpll_rate(clk);
 644
 645         return r;
 646 }
 647
 648 /**
 649  * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
 650  * @clk: pointer to a DPLL struct clk
 651  *
 652  * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
 653  * The choice of modes depends on the DPLL's programmed rate: if it is
 654  * the same as the DPLL's parent clock, it will enter bypass;
 655  * otherwise, it will enter lock.  This code will wait for the DPLL to
 656  * indicate readiness before returning, unless the DPLL takes too long
 657  * to enter the target state.  Intended to be used as the struct clk's
 658  * enable function.  If DPLL3 was passed in, or the DPLL does not
 659  * support low-power stop, or if the DPLL took too long to enter
 660  * bypass or lock, return -EINVAL; otherwise, return 0.
 661  */
 662 static void omap3_noncore_dpll_disable(struct clk *clk)
 663 {
 664         if (clk == &dpll3_ck)
 665                 return;
 666
 667         _omap3_noncore_dpll_stop(clk);
 668 }
 669
 670
 671 /* Non-CORE DPLL rate set code */
 672
 673 /*
 674  * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
 675  * @clk: struct clk * of DPLL to set
 676  * @m: DPLL multiplier to set
 677  * @n: DPLL divider to set
 678  * @freqsel: FREQSEL value to set
 679  *
 680  * Program the DPLL with the supplied M, N values, and wait for the DPLL to
 681  * lock..  Returns -EINVAL upon error, or 0 upon success.
 682  */
 683 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
 684 {
 685         struct dpll_data *dd = clk->dpll_data;
 686         u32 v;
 687
 688         /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
 689         _omap3_noncore_dpll_bypass(clk);
 690
 691         /* Set jitter correction */
 692         v = __raw_readl(dd->control_reg);
 693         v &= ~dd->freqsel_mask;
 694         v |= freqsel << __ffs(dd->freqsel_mask);
 695         __raw_writel(v, dd->control_reg);
 696
 697         /* Set DPLL multiplier, divider */
 698         v = __raw_readl(dd->mult_div1_reg);
 699         v &= ~(dd->mult_mask | dd->div1_mask);
 700         v |= m << __ffs(dd->mult_mask);
 701         v |= (n - 1) << __ffs(dd->div1_mask);
 702         __raw_writel(v, dd->mult_div1_reg);
 703
 704         /* We let the clock framework set the other output dividers later */
 705
 706         /* REVISIT: Set ramp-up delay? */
 707
 708         _omap3_noncore_dpll_lock(clk);
 709
 710         return 0;
 711 }
 712
 713 /**
 714  * omap3_noncore_dpll_set_rate - set non-core DPLL rate
 715  * @clk: struct clk * of DPLL to set
 716  * @rate: rounded target rate
 717  *
 718  * Set the DPLL CLKOUT to the target rate.  If the DPLL can enter
 719  * low-power bypass, and the target rate is the bypass source clock
 720  * rate, then configure the DPLL for bypass.  Otherwise, round the
 721  * target rate if it hasn't been done already, then program and lock
 722  * the DPLL.  Returns -EINVAL upon error, or 0 upon success.
 723  */
 724 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 725 {
 726         struct clk *new_parent = NULL;
 727         u16 freqsel;
 728         struct dpll_data *dd;
 729         int ret;
 730
 731         if (!clk || !rate)
 732                 return -EINVAL;
 733
 734         dd = clk->dpll_data;
 735         if (!dd)
 736                 return -EINVAL;
 737
 738         if (rate == omap2_get_dpll_rate(clk))
 739                 return 0;
 740
 741         /*
 742          * Ensure both the bypass and ref clocks are enabled prior to
 743          * doing anything; we need the bypass clock running to reprogram
 744          * the DPLL.
 745          */
 746         omap2_clk_enable(dd->clk_bypass);
 747         omap2_clk_enable(dd->clk_ref);
 748
 749         if (dd->clk_bypass->rate == rate &&
 750             (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
 751                 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
 752
 753                 ret = _omap3_noncore_dpll_bypass(clk);
 754                 if (!ret)
 755                         new_parent = dd->clk_bypass;
 756         } else {
 757                 if (dd->last_rounded_rate != rate)
 758                         omap2_dpll_round_rate(clk, rate);
 759
 760                 if (dd->last_rounded_rate == 0)
 761                         return -EINVAL;
 762
 763                 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
 764                 if (!freqsel)
 765                         WARN_ON(1);
 766
 767                 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
 768                          clk->name, rate);
 769
 770                 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
 771                                                  dd->last_rounded_n, freqsel);
 772                 if (!ret)
 773                         new_parent = dd->clk_ref;
 774         }
 775         if (!ret) {
 776                 /*
 777                  * Switch the parent clock in the heirarchy, and make sure
 778                  * that the new parent's usecount is correct.  Note: we
 779                  * enable the new parent before disabling the old to avoid
 780                  * any unnecessary hardware disable->enable transitions.
 781                  */
 782                 if (clk->usecount) {
 783                         omap2_clk_enable(new_parent);
 784                         omap2_clk_disable(clk->parent);
 785                 }
 786                 clk_reparent(clk, new_parent);
 787                 clk->rate = rate;
 788         }
 789         omap2_clk_disable(dd->clk_ref);
 790         omap2_clk_disable(dd->clk_bypass);
 791
 792         return 0;
 793 }
 794
 795 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
 796 {
 797         /*
 798          * According to the 12-5 CDP code from TI, "Limitation 2.5"
 799          * on 3430ES1 prevents us from changing DPLL multipliers or dividers
 800          * on DPLL4.
 801          */
 802         if (omap_rev() == OMAP3430_REV_ES1_0) {
 803                 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
 804                        "silicon 'Limitation 2.5' on 3430ES1.\n");
 805                 return -EINVAL;
 806         }
 807         return omap3_noncore_dpll_set_rate(clk, rate);
 808 }
 809
 810
 811 /*
 812  * CORE DPLL (DPLL3) rate programming functions
 813  *
 814  * These call into SRAM code to do the actual CM writes, since the SDRAM
 815  * is clocked from DPLL3.
 816  */
 817
 818 /**
 819  * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
 820  * @clk: struct clk * of DPLL to set
 821  * @rate: rounded target rate
 822  *
 823  * Program the DPLL M2 divider with the rounded target rate.  Returns
 824  * -EINVAL upon error, or 0 upon success.
 825  */
 826 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 827 {
 828         u32 new_div = 0;
 829         u32 unlock_dll = 0;
 830         u32 c;
 831         unsigned long validrate, sdrcrate, mpurate;
 832         struct omap_sdrc_params *sdrc_cs0;
 833         struct omap_sdrc_params *sdrc_cs1;
 834         int ret;
 835
 836         if (!clk || !rate)
 837                 return -EINVAL;
 838
 839         if (clk != &dpll3_m2_ck)
 840                 return -EINVAL;
 841
 842         validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
 843         if (validrate != rate)
 844                 return -EINVAL;
 845
 846         sdrcrate = sdrc_ick.rate;
 847         if (rate > clk->rate)
 848                 sdrcrate <<= ((rate / clk->rate) >> 1);
 849         else
 850                 sdrcrate >>= ((clk->rate / rate) >> 1);
 851
 852         ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
 853         if (ret)
 854                 return -EINVAL;
 855
 856         if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
 857                 pr_debug("clock: will unlock SDRC DLL\n");
 858                 unlock_dll = 1;
 859         }
 860
 861         /*
 862          * XXX This only needs to be done when the CPU frequency changes
 863          */
 864         mpurate = arm_fck.rate / CYCLES_PER_MHZ;
 865         c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
 866         c += 1;  /* for safety */
 867         c *= SDRC_MPURATE_LOOPS;
 868         c >>= SDRC_MPURATE_SCALE;
 869         if (c == 0)
 870                 c = 1;
 871
 872         pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
 873                  validrate);
 874         pr_debug("clock: SDRC CS0 timing params used:"
 875                  " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
 876                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
 877                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
 878         if (sdrc_cs1)
 879                 pr_debug("clock: SDRC CS1 timing params used: "
 880                  " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
 881                  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
 882                  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
 883
 884         if (sdrc_cs1)
 885                 omap3_configure_core_dpll(
 886                                   new_div, unlock_dll, c, rate > clk->rate,
 887                                   sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
 888                                   sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
 889                                   sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
 890                                   sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
 891         else
 892                 omap3_configure_core_dpll(
 893                                   new_div, unlock_dll, c, rate > clk->rate,
 894                                   sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
 895                                   sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
 896                                   0, 0, 0, 0);
 897
 898         return 0;
 899 }
 900
 901
 902 static const struct clkops clkops_noncore_dpll_ops = {
 903         .enable         = &omap3_noncore_dpll_enable,
 904         .disable        = &omap3_noncore_dpll_disable,
 905 };
 906
 907 /* DPLL autoidle read/set code */
 908
 909
 910 /**
 911  * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
 912  * @clk: struct clk * of the DPLL to read
 913  *
 914  * Return the DPLL's autoidle bits, shifted down to bit 0.  Returns
 915  * -EINVAL if passed a null pointer or if the struct clk does not
 916  * appear to refer to a DPLL.
 917  */
 918 static u32 omap3_dpll_autoidle_read(struct clk *clk)
 919 {
 920         const struct dpll_data *dd;
 921         u32 v;
 922
 923         if (!clk || !clk->dpll_data)
 924                 return -EINVAL;
 925
 926         dd = clk->dpll_data;
 927
 928         v = __raw_readl(dd->autoidle_reg);
 929         v &= dd->autoidle_mask;
 930         v >>= __ffs(dd->autoidle_mask);
 931
 932         return v;
 933 }
 934
 935 /**
 936  * omap3_dpll_allow_idle - enable DPLL autoidle bits
 937  * @clk: struct clk * of the DPLL to operate on
 938  *
 939  * Enable DPLL automatic idle control.  This automatic idle mode
 940  * switching takes effect only when the DPLL is locked, at least on
 941  * OMAP3430.  The DPLL will enter low-power stop when its downstream
 942  * clocks are gated.  No return value.
 943  */
 944 static void omap3_dpll_allow_idle(struct clk *clk)
 945 {
 946         const struct dpll_data *dd;
 947         u32 v;
 948
 949         if (!clk || !clk->dpll_data)
 950                 return;
 951
 952         dd = clk->dpll_data;
 953
 954         /*
 955          * REVISIT: CORE DPLL can optionally enter low-power bypass
 956          * by writing 0x5 instead of 0x1.  Add some mechanism to
 957          * optionally enter this mode.
 958          */
 959         v = __raw_readl(dd->autoidle_reg);
 960         v &= ~dd->autoidle_mask;
 961         v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
 962         __raw_writel(v, dd->autoidle_reg);
 963 }
 964
 965 /**
 966  * omap3_dpll_deny_idle - prevent DPLL from automatically idling
 967  * @clk: struct clk * of the DPLL to operate on
 968  *
 969  * Disable DPLL automatic idle control.  No return value.
 970  */
 971 static void omap3_dpll_deny_idle(struct clk *clk)
 972 {
 973         const struct dpll_data *dd;
 974         u32 v;
 975
 976         if (!clk || !clk->dpll_data)
 977                 return;
 978
 979         dd = clk->dpll_data;
 980
 981         v = __raw_readl(dd->autoidle_reg);
 982         v &= ~dd->autoidle_mask;
 983         v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
 984         __raw_writel(v, dd->autoidle_reg);
 985 }
 986
 987 /* Clock control for DPLL outputs */
 988
 989 /**
 990  * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
 991  * @clk: DPLL output struct clk
 992  *
 993  * Using parent clock DPLL data, look up DPLL state.  If locked, set our
 994  * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
 995  */
 996 static unsigned long omap3_clkoutx2_recalc(struct clk *clk)
 997 {
 998         const struct dpll_data *dd;
 999         unsigned long rate;
1000         u32 v;
1001         struct clk *pclk;
1002
1003         /* Walk up the parents of clk, looking for a DPLL */
1004         pclk = clk->parent;
1005         while (pclk && !pclk->dpll_data)
1006                 pclk = pclk->parent;
1007
1008         /* clk does not have a DPLL as a parent? */
1009         WARN_ON(!pclk);
1010
1011         dd = pclk->dpll_data;
1012
1013         WARN_ON(!dd->enable_mask);
1014
1015         v = __raw_readl(dd->control_reg) & dd->enable_mask;
1016         v >>= __ffs(dd->enable_mask);
1017         if (v != OMAP3XXX_EN_DPLL_LOCKED)
1018                 rate = clk->parent->rate;
1019         else
1020                 rate = clk->parent->rate * 2;
1021         return rate;
1022 }
1023
1024 /* Common clock code */
1025
1026 /*
1027  * As it is structured now, this will prevent an OMAP2/3 multiboot
1028  * kernel from compiling.  This will need further attention.
1029  */
1030 #if defined(CONFIG_ARCH_OMAP3)
1031
1032 static struct clk_functions omap2_clk_functions = {
1033         .clk_enable             = omap2_clk_enable,
1034         .clk_disable            = omap2_clk_disable,
1035         .clk_round_rate         = omap2_clk_round_rate,
1036         .clk_set_rate           = omap2_clk_set_rate,
1037         .clk_set_parent         = omap2_clk_set_parent,
1038         .clk_disable_unused     = omap2_clk_disable_unused,
1039 };
1040
1041 /*
1042  * Set clocks for bypass mode for reboot to work.
1043  */
1044 void omap2_clk_prepare_for_reboot(void)
1045 {
1046         /* REVISIT: Not ready for 343x */
1047 #if 0
1048         u32 rate;
1049
1050         if (vclk == NULL || sclk == NULL)
1051                 return;
1052
1053         rate = clk_get_rate(sclk);
1054         clk_set_rate(vclk, rate);
1055 #endif
1056 }
1057
1058 /* REVISIT: Move this init stuff out into clock.c */
1059
1060 /*
1061  * Switch the MPU rate if specified on cmdline.
1062  * We cannot do this early until cmdline is parsed.
1063  */
1064 static int __init omap2_clk_arch_init(void)
1065 {
1066         if (!mpurate)
1067                 return -EINVAL;
1068
1069         /* REVISIT: not yet ready for 343x */
1070 #if 0
1071         if (clk_set_rate(&virt_prcm_set, mpurate))
1072                 printk(KERN_ERR "Could not find matching MPU rate\n");
1073 #endif
1074
1075         recalculate_root_clocks();
1076
1077         printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
1078                "%ld.%01ld/%ld/%ld MHz\n",
1079                (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
1080                (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
1081
1082         return 0;
1083 }
1084 arch_initcall(omap2_clk_arch_init);
1085
1086 int __init omap2_clk_init(void)
1087 {
1088         /* struct prcm_config *prcm; */
1089         struct omap_clk *c;
1090         /* u32 clkrate; */
1091         u32 cpu_clkflg;
1092
1093         if (cpu_is_omap34xx()) {
1094                 cpu_mask = RATE_IN_343X;
1095                 cpu_clkflg = CK_343X;
1096
1097                 /*
1098                  * Update this if there are further clock changes between ES2
1099                  * and production parts
1100                  */
1101                 if (omap_rev() == OMAP3430_REV_ES1_0) {
1102                         /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
1103                         cpu_clkflg |= CK_3430ES1;
1104                 } else {
1105                         cpu_mask |= RATE_IN_3430ES2;
1106                         cpu_clkflg |= CK_3430ES2;
1107                 }
1108         }
1109
1110         clk_init(&omap2_clk_functions);
1111
1112         for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
1113                 clk_preinit(c->lk.clk);
1114
1115         for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
1116                 if (c->cpu & cpu_clkflg) {
1117                         clkdev_add(&c->lk);
1118                         clk_register(c->lk.clk);
1119                         omap2_init_clk_clkdm(c->lk.clk);
1120                 }
1121
1122         /* REVISIT: Not yet ready for OMAP3 */
1123 #if 0
1124         /* Check the MPU rate set by bootloader */
1125         clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
1126         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1127                 if (!(prcm->flags & cpu_mask))
1128                         continue;
1129                 if (prcm->xtal_speed != sys_ck.rate)
1130                         continue;
1131                 if (prcm->dpll_speed <= clkrate)
1132                          break;
1133         }
1134         curr_prcm_set = prcm;
1135 #endif
1136
1137         recalculate_root_clocks();
1138
1139         printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
1140                "%ld.%01ld/%ld/%ld MHz\n",
1141                (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
1142                (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
1143
1144         /*
1145          * Only enable those clocks we will need, let the drivers
1146          * enable other clocks as necessary
1147          */
1148         clk_enable_init_clocks();
1149
1150         /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
1151         /* REVISIT: not yet ready for 343x */
1152 #if 0
1153         vclk = clk_get(NULL, "virt_prcm_set");
1154         sclk = clk_get(NULL, "sys_ck");
1155 #endif
1156         return 0;
1157 }
1158
1159 #endif