arch/arm/mach-omap2/clock34xx.c

   1 /*
   2  * OMAP3-specific clock framework functions
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * Testing and integration fixes by Jouni Högander
   9  *
  10  * Parts of this code are based on code written by
  11  * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17 #undef DEBUG
  18
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/device.h>
  22 #include <linux/list.h>
  23 #include <linux/errno.h>
  24 #include <linux/delay.h>
  25 #include <linux/clk.h>
  26 #include <linux/io.h>
  27 #include <linux/limits.h>
  28 #include <linux/bitops.h>
  29
  30 #include <mach/clock.h>
  31 #include <mach/sram.h>
  32 #include <asm/div64.h>
  33 #include <asm/clkdev.h>
  34
  35 #include <mach/sdrc.h>
  36 #include "clock.h"
  37 #include "prm.h"
  38 #include "prm-regbits-34xx.h"
  39 #include "cm.h"
  40 #include "cm-regbits-34xx.h"
  41
  42 static const struct clkops clkops_noncore_dpll_ops;
  43
  44 #include "clock34xx.h"
  45
  46 struct omap_clk {
  47         u32             cpu;
  48         struct clk_lookup lk;
  49 };
  50
  51 #define CLK(dev, con, ck, cp)           \
  52         {                               \
  53                  .cpu = cp,             \
  54                 .lk = {                 \
  55                         .dev_id = dev,  \
  56                         .con_id = con,  \
  57                         .clk = ck,      \
  58                 },                      \
  59         }
  60
  61 #define CK_343X         (1 << 0)
  62 #define CK_3430ES1      (1 << 1)
  63 #define CK_3430ES2      (1 << 2)
  64
  65 static struct omap_clk omap34xx_clks[] = {
  66         CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_343X),
  67         CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_343X),
  68         CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_343X),
  69         CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
  70         CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
  71         CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_343X),
  72         CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
  73         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_343X),
  74         CLK(NULL,       "sys_ck",       &sys_ck,        CK_343X),
  75         CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_343X),
  76         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_343X),
  77         CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_343X),
  78         CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_343X),
  79         CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_343X),
  80         CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
  81         CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_343X),
  82         CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_343X),
  83         CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_343X),
  84         CLK(NULL,       "core_ck",      &core_ck,       CK_343X),
  85         CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_343X),
  86         CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_343X),
  87         CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
  88         CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_343X),
  89         CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
  90         CLK(NULL,       "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
  91         CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_343X),
  92         CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_343X),
  93         CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
  94         CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_343X),
  95         CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_343X),
  96         CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_343X),
  97         CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_343X),
  98         CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_343X),
  99         CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_343X),
 100         CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
 101         CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_343X),
 102         CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
 103         CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_343X),
 104         CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
 105         CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_343X),
 106         CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
 107         CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_343X),
 108         CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
 109         CLK(NULL,       "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
 110         CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2),
 111         CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2),
 112         CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_343X),
 113         CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_343X),
 114         CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_343X),
 115         CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_343X),
 116         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_343X),
 117         CLK(NULL,       "arm_fck",      &arm_fck,       CK_343X),
 118         CLK(NULL,       "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
 119         CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_343X),
 120         CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_343X),
 121         CLK(NULL,       "l3_ick",       &l3_ick,        CK_343X),
 122         CLK(NULL,       "l4_ick",       &l4_ick,        CK_343X),
 123         CLK(NULL,       "rm_ick",       &rm_ick,        CK_343X),
 124         CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
 125         CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
 126         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
 127         CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
 128         CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
 129         CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2),
 130         CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2),
 131         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
 132         CLK(NULL,       "modem_fck",    &modem_fck,     CK_343X),
 133         CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_343X),
 134         CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_343X),
 135         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_343X),
 136         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_343X),
 137         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2),
 138         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2),
 139         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2),
 140         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_343X),
 141         CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2),
 142         CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_343X),
 143         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_343X),
 144         CLK("mmci-omap-hs.0",   "fck",  &mmchs1_fck,    CK_343X),
 145         CLK("i2c_omap.3", "fck",        &i2c3_fck,      CK_343X),
 146         CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_343X),
 147         CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_343X),
 148         CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_343X),
 149         CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_343X),
 150         CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_343X),
 151         CLK("omap2_mcspi.4", "fck",     &mcspi4_fck,    CK_343X),
 152         CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_343X),
 153         CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_343X),
 154         CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_343X),
 155         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_343X),
 156         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_343X),
 157         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
 158         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_343X),
 159         CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_343X),
 160         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck,   CK_343X),
 161         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck,   CK_343X),
 162         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_343X),
 163         CLK("musb_hdrc",        "ick",  &hsotgusb_ick,  CK_343X),
 164         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_343X),
 165         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_343X),
 166         CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_343X),
 167         CLK(NULL,       "pka_ick",      &pka_ick,       CK_343X),
 168         CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_343X),
 169         CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2),
 170         CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2),
 171         CLK(NULL,       "icr_ick",      &icr_ick,       CK_343X),
 172         CLK(NULL,       "aes2_ick",     &aes2_ick,      CK_343X),
 173         CLK(NULL,       "sha12_ick",    &sha12_ick,     CK_343X),
 174         CLK(NULL,       "des2_ick",     &des2_ick,      CK_343X),
 175         CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_343X),
 176         CLK("mmci-omap-hs.0",   "ick",  &mmchs1_ick,    CK_343X),
 177         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_343X),
 178         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_343X),
 179         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_343X),
 180         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_343X),
 181         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_343X),
 182         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_343X),
 183         CLK("i2c_omap.3", "ick",        &i2c3_ick,      CK_343X),
 184         CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_343X),
 185         CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_343X),
 186         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_343X),
 187         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_343X),
 188         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_343X),
 189         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_343X),
 190         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_343X),
 191         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_343X),
 192         CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
 193         CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_343X),
 194         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_343X),
 195         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_343X),
 196         CLK(NULL,       "ssi_ick",      &ssi_ick,       CK_343X),
 197         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
 198         CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_343X),
 199         CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_343X),
 200         CLK("omap_rng", "ick",          &rng_ick,       CK_343X),
 201         CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
 202         CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
 203         CLK("omapfb",   "dss1_fck",     &dss1_alwon_fck, CK_343X),
 204         CLK("omapfb",   "tv_fck",       &dss_tv_fck,    CK_343X),
 205         CLK("omapfb",   "video_fck",    &dss_96m_fck,   CK_343X),
 206         CLK("omapfb",   "dss2_fck",     &dss2_alwon_fck, CK_343X),
 207         CLK("omapfb",   "ick",          &dss_ick,       CK_343X),
 208         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
 209         CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
 210         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
 211         CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
 212         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
 213         CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2),
 214         CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2),
 215         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_343X),
 216         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_343X),
 217         CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_343X),
 218         CLK("omap_wdt", "fck",          &wdt2_fck,      CK_343X),
 219         CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_343X),
 220         CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2),
 221         CLK("omap_wdt", "ick",          &wdt2_ick,      CK_343X),
 222         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_343X),
 223         CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_343X),
 224         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
 225         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_343X),
 226         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_343X),
 227         CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_343X),
 228         CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_343X),
 229         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_343X),
 230         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_343X),
 231         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_343X),
 232         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_343X),
 233         CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_343X),
 234         CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_343X),
 235         CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_343X),
 236         CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_343X),
 237         CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_343X),
 238         CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
 239         CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_343X),
 240         CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_343X),
 241         CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_343X),
 242         CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_343X),
 243         CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_343X),
 244         CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_343X),
 245         CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_343X),
 246         CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_343X),
 247         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_343X),
 248         CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_343X),
 249         CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_343X),
 250         CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_343X),
 251         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_343X),
 252         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_343X),
 253         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_343X),
 254         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_343X),
 255         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_343X),
 256         CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_343X),
 257         CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_343X),
 258         CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_343X),
 259         CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_343X),
 260         CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_343X),
 261         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_343X),
 262         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_343X),
 263         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_343X),
 264         CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_343X),
 265         CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_343X),
 266         CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_343X),
 267         CLK(NULL,       "emu_src_ck",   &emu_src_ck,    CK_343X),
 268         CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_343X),
 269         CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_343X),
 270         CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_343X),
 271         CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_343X),
 272         CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_343X),
 273         CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_343X),
 274         CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_343X),
 275         CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_343X),
 276         CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_343X),
 277         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_343X),
 278         CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_343X),
 279 };
 280
 281 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
 282 #define DPLL_AUTOIDLE_DISABLE                   0x0
 283 #define DPLL_AUTOIDLE_LOW_POWER_STOP            0x1
 284
 285 #define MAX_DPLL_WAIT_TRIES             1000000
 286
 287 #define MIN_SDRC_DLL_LOCK_FREQ          83000000
 288
 289 /**
 290  * omap3_dpll_recalc - recalculate DPLL rate
 291  * @clk: DPLL struct clk
 292  *
 293  * Recalculate and propagate the DPLL rate.
 294  */
 295 static unsigned long omap3_dpll_recalc(struct clk *clk)
 296 {
 297         return omap2_get_dpll_rate(clk);
 298 }
 299
 300 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
 301 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
 302 {
 303         const struct dpll_data *dd;
 304         u32 v;
 305
 306         dd = clk->dpll_data;
 307
 308         v = __raw_readl(dd->control_reg);
 309         v &= ~dd->enable_mask;
 310         v |= clken_bits << __ffs(dd->enable_mask);
 311         __raw_writel(v, dd->control_reg);
 312 }
 313
 314 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
 315 static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
 316 {
 317         const struct dpll_data *dd;
 318         int i = 0;
 319         int ret = -EINVAL;
 320
 321         dd = clk->dpll_data;
 322
 323         state <<= __ffs(dd->idlest_mask);
 324
 325         while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
 326                i < MAX_DPLL_WAIT_TRIES) {
 327                 i++;
 328                 udelay(1);
 329         }
 330
 331         if (i == MAX_DPLL_WAIT_TRIES) {
 332                 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
 333                        clk->name, (state) ? "locked" : "bypassed");
 334         } else {
 335                 pr_debug("clock: %s transition to '%s' in %d loops\n",
 336                          clk->name, (state) ? "locked" : "bypassed", i);
 337
 338                 ret = 0;
 339         }
 340
 341         return ret;
 342 }
 343
 344 /* From 3430 TRM ES2 4.7.6.2 */
 345 static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
 346 {
 347         unsigned long fint;
 348         u16 f = 0;
 349
 350         fint = clk->dpll_data->clk_ref->rate / (n + 1);
 351
 352         pr_debug("clock: fint is %lu\n", fint);
 353
 354         if (fint >= 750000 && fint <= 1000000)
 355                 f = 0x3;
 356         else if (fint > 1000000 && fint <= 1250000)
 357                 f = 0x4;
 358         else if (fint > 1250000 && fint <= 1500000)
 359                 f = 0x5;
 360         else if (fint > 1500000 && fint <= 1750000)
 361                 f = 0x6;
 362         else if (fint > 1750000 && fint <= 2100000)
 363                 f = 0x7;
 364         else if (fint > 7500000 && fint <= 10000000)
 365                 f = 0xB;
 366         else if (fint > 10000000 && fint <= 12500000)
 367                 f = 0xC;
 368         else if (fint > 12500000 && fint <= 15000000)
 369                 f = 0xD;
 370         else if (fint > 15000000 && fint <= 17500000)
 371                 f = 0xE;
 372         else if (fint > 17500000 && fint <= 21000000)
 373                 f = 0xF;
 374         else
 375                 pr_debug("clock: unknown freqsel setting for %d\n", n);
 376
 377         return f;
 378 }
 379
 380 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
 381
 382 /*
 383  * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
 384  * @clk: pointer to a DPLL struct clk
 385  *
 386  * Instructs a non-CORE DPLL to lock.  Waits for the DPLL to report
 387  * readiness before returning.  Will save and restore the DPLL's
 388  * autoidle state across the enable, per the CDP code.  If the DPLL
 389  * locked successfully, return 0; if the DPLL did not lock in the time
 390  * allotted, or DPLL3 was passed in, return -EINVAL.
 391  */
 392 static int _omap3_noncore_dpll_lock(struct clk *clk)
 393 {
 394         u8 ai;
 395         int r;
 396
 397         if (clk == &dpll3_ck)
 398                 return -EINVAL;
 399
 400         pr_debug("clock: locking DPLL %s\n", clk->name);
 401
 402         ai = omap3_dpll_autoidle_read(clk);
 403
 404         omap3_dpll_deny_idle(clk);
 405
 406         _omap3_dpll_write_clken(clk, DPLL_LOCKED);
 407
 408         r = _omap3_wait_dpll_status(clk, 1);
 409
 410         if (ai)
 411                 omap3_dpll_allow_idle(clk);
 412
 413         return r;
 414 }
 415
 416 /*
 417  * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
 418  * @clk: pointer to a DPLL struct clk
 419  *
 420  * Instructs a non-CORE DPLL to enter low-power bypass mode.  In
 421  * bypass mode, the DPLL's rate is set equal to its parent clock's
 422  * rate.  Waits for the DPLL to report readiness before returning.
 423  * Will save and restore the DPLL's autoidle state across the enable,
 424  * per the CDP code.  If the DPLL entered bypass mode successfully,
 425  * return 0; if the DPLL did not enter bypass in the time allotted, or
 426  * DPLL3 was passed in, or the DPLL does not support low-power bypass,
 427  * return -EINVAL.
 428  */
 429 static int _omap3_noncore_dpll_bypass(struct clk *clk)
 430 {
 431         int r;
 432         u8 ai;
 433
 434         if (clk == &dpll3_ck)
 435                 return -EINVAL;
 436
 437         if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
 438                 return -EINVAL;
 439
 440         pr_debug("clock: configuring DPLL %s for low-power bypass\n",
 441                  clk->name);
 442
 443         ai = omap3_dpll_autoidle_read(clk);
 444
 445         _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
 446
 447         r = _omap3_wait_dpll_status(clk, 0);
 448
 449         if (ai)
 450                 omap3_dpll_allow_idle(clk);
 451         else
 452                 omap3_dpll_deny_idle(clk);
 453
 454         return r;
 455 }
 456
 457 /*
 458  * _omap3_noncore_dpll_stop - instruct a DPLL to stop
 459  * @clk: pointer to a DPLL struct clk
 460  *
 461  * Instructs a non-CORE DPLL to enter low-power stop. Will save and
 462  * restore the DPLL's autoidle state across the stop, per the CDP
 463  * code.  If DPLL3 was passed in, or the DPLL does not support
 464  * low-power stop, return -EINVAL; otherwise, return 0.
 465  */
 466 static int _omap3_noncore_dpll_stop(struct clk *clk)
 467 {
 468         u8 ai;
 469
 470         if (clk == &dpll3_ck)
 471                 return -EINVAL;
 472
 473         if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
 474                 return -EINVAL;
 475
 476         pr_debug("clock: stopping DPLL %s\n", clk->name);
 477
 478         ai = omap3_dpll_autoidle_read(clk);
 479
 480         _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
 481
 482         if (ai)
 483                 omap3_dpll_allow_idle(clk);
 484         else
 485                 omap3_dpll_deny_idle(clk);
 486
 487         return 0;
 488 }
 489
 490 /**
 491  * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
 492  * @clk: pointer to a DPLL struct clk
 493  *
 494  * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
 495  * The choice of modes depends on the DPLL's programmed rate: if it is
 496  * the same as the DPLL's parent clock, it will enter bypass;
 497  * otherwise, it will enter lock.  This code will wait for the DPLL to
 498  * indicate readiness before returning, unless the DPLL takes too long
 499  * to enter the target state.  Intended to be used as the struct clk's
 500  * enable function.  If DPLL3 was passed in, or the DPLL does not
 501  * support low-power stop, or if the DPLL took too long to enter
 502  * bypass or lock, return -EINVAL; otherwise, return 0.
 503  */
 504 static int omap3_noncore_dpll_enable(struct clk *clk)
 505 {
 506         int r;
 507         struct dpll_data *dd;
 508
 509         if (clk == &dpll3_ck)
 510                 return -EINVAL;
 511
 512         dd = clk->dpll_data;
 513         if (!dd)
 514                 return -EINVAL;
 515
 516         if (clk->rate == dd->clk_bypass->rate) {
 517                 WARN_ON(clk->parent != dd->clk_bypass);
 518                 r = _omap3_noncore_dpll_bypass(clk);
 519         } else {
 520                 WARN_ON(clk->parent != dd->clk_ref);
 521                 r = _omap3_noncore_dpll_lock(clk);
 522         }
 523         /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */
 524         if (!r)
 525                 clk->rate = omap2_get_dpll_rate(clk);
 526
 527         return r;
 528 }
 529
 530 /**
 531  * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
 532  * @clk: pointer to a DPLL struct clk
 533  *
 534  * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
 535  * The choice of modes depends on the DPLL's programmed rate: if it is
 536  * the same as the DPLL's parent clock, it will enter bypass;
 537  * otherwise, it will enter lock.  This code will wait for the DPLL to
 538  * indicate readiness before returning, unless the DPLL takes too long
 539  * to enter the target state.  Intended to be used as the struct clk's
 540  * enable function.  If DPLL3 was passed in, or the DPLL does not
 541  * support low-power stop, or if the DPLL took too long to enter
 542  * bypass or lock, return -EINVAL; otherwise, return 0.
 543  */
 544 static void omap3_noncore_dpll_disable(struct clk *clk)
 545 {
 546         if (clk == &dpll3_ck)
 547                 return;
 548
 549         _omap3_noncore_dpll_stop(clk);
 550 }
 551
 552
 553 /* Non-CORE DPLL rate set code */
 554
 555 /*
 556  * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
 557  * @clk: struct clk * of DPLL to set
 558  * @m: DPLL multiplier to set
 559  * @n: DPLL divider to set
 560  * @freqsel: FREQSEL value to set
 561  *
 562  * Program the DPLL with the supplied M, N values, and wait for the DPLL to
 563  * lock..  Returns -EINVAL upon error, or 0 upon success.
 564  */
 565 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
 566 {
 567         struct dpll_data *dd = clk->dpll_data;
 568         u32 v;
 569
 570         /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
 571         _omap3_noncore_dpll_bypass(clk);
 572
 573         /* Set jitter correction */
 574         v = __raw_readl(dd->control_reg);
 575         v &= ~dd->freqsel_mask;
 576         v |= freqsel << __ffs(dd->freqsel_mask);
 577         __raw_writel(v, dd->control_reg);
 578
 579         /* Set DPLL multiplier, divider */
 580         v = __raw_readl(dd->mult_div1_reg);
 581         v &= ~(dd->mult_mask | dd->div1_mask);
 582         v |= m << __ffs(dd->mult_mask);
 583         v |= (n - 1) << __ffs(dd->div1_mask);
 584         __raw_writel(v, dd->mult_div1_reg);
 585
 586         /* We let the clock framework set the other output dividers later */
 587
 588         /* REVISIT: Set ramp-up delay? */
 589
 590         _omap3_noncore_dpll_lock(clk);
 591
 592         return 0;
 593 }
 594
 595 /**
 596  * omap3_noncore_dpll_set_rate - set non-core DPLL rate
 597  * @clk: struct clk * of DPLL to set
 598  * @rate: rounded target rate
 599  *
 600  * Set the DPLL CLKOUT to the target rate.  If the DPLL can enter
 601  * low-power bypass, and the target rate is the bypass source clock
 602  * rate, then configure the DPLL for bypass.  Otherwise, round the
 603  * target rate if it hasn't been done already, then program and lock
 604  * the DPLL.  Returns -EINVAL upon error, or 0 upon success.
 605  */
 606 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 607 {
 608         struct clk *new_parent = NULL;
 609         u16 freqsel;
 610         struct dpll_data *dd;
 611         int ret;
 612
 613         if (!clk || !rate)
 614                 return -EINVAL;
 615
 616         dd = clk->dpll_data;
 617         if (!dd)
 618                 return -EINVAL;
 619
 620         if (rate == omap2_get_dpll_rate(clk))
 621                 return 0;
 622
 623         /*
 624          * Ensure both the bypass and ref clocks are enabled prior to
 625          * doing anything; we need the bypass clock running to reprogram
 626          * the DPLL.
 627          */
 628         omap2_clk_enable(dd->clk_bypass);
 629         omap2_clk_enable(dd->clk_ref);
 630
 631         if (dd->clk_bypass->rate == rate &&
 632             (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
 633                 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
 634
 635                 ret = _omap3_noncore_dpll_bypass(clk);
 636                 if (!ret)
 637                         new_parent = dd->clk_bypass;
 638         } else {
 639                 if (dd->last_rounded_rate != rate)
 640                         omap2_dpll_round_rate(clk, rate);
 641
 642                 if (dd->last_rounded_rate == 0)
 643                         return -EINVAL;
 644
 645                 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
 646                 if (!freqsel)
 647                         WARN_ON(1);
 648
 649                 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
 650                          clk->name, rate);
 651
 652                 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
 653                                                  dd->last_rounded_n, freqsel);
 654                 if (!ret)
 655                         new_parent = dd->clk_ref;
 656         }
 657         if (!ret) {
 658                 /*
 659                  * Switch the parent clock in the heirarchy, and make sure
 660                  * that the new parent's usecount is correct.  Note: we
 661                  * enable the new parent before disabling the old to avoid
 662                  * any unnecessary hardware disable->enable transitions.
 663                  */
 664                 if (clk->usecount) {
 665                         omap2_clk_enable(new_parent);
 666                         omap2_clk_disable(clk->parent);
 667                 }
 668                 clk_reparent(clk, new_parent);
 669                 clk->rate = rate;
 670         }
 671         omap2_clk_disable(dd->clk_ref);
 672         omap2_clk_disable(dd->clk_bypass);
 673
 674         return 0;
 675 }
 676
 677 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
 678 {
 679         /*
 680          * According to the 12-5 CDP code from TI, "Limitation 2.5"
 681          * on 3430ES1 prevents us from changing DPLL multipliers or dividers
 682          * on DPLL4.
 683          */
 684         if (omap_rev() == OMAP3430_REV_ES1_0) {
 685                 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
 686                        "silicon 'Limitation 2.5' on 3430ES1.\n");
 687                 return -EINVAL;
 688         }
 689         return omap3_noncore_dpll_set_rate(clk, rate);
 690 }
 691
 692
 693 /*
 694  * CORE DPLL (DPLL3) rate programming functions
 695  *
 696  * These call into SRAM code to do the actual CM writes, since the SDRAM
 697  * is clocked from DPLL3.
 698  */
 699
 700 /**
 701  * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
 702  * @clk: struct clk * of DPLL to set
 703  * @rate: rounded target rate
 704  *
 705  * Program the DPLL M2 divider with the rounded target rate.  Returns
 706  * -EINVAL upon error, or 0 upon success.
 707  */
 708 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 709 {
 710         u32 new_div = 0;
 711         u32 unlock_dll = 0;
 712         unsigned long validrate, sdrcrate;
 713         struct omap_sdrc_params *sp;
 714
 715         if (!clk || !rate)
 716                 return -EINVAL;
 717
 718         if (clk != &dpll3_m2_ck)
 719                 return -EINVAL;
 720
 721         if (rate == clk->rate)
 722                 return 0;
 723
 724         validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
 725         if (validrate != rate)
 726                 return -EINVAL;
 727
 728         sdrcrate = sdrc_ick.rate;
 729         if (rate > clk->rate)
 730                 sdrcrate <<= ((rate / clk->rate) - 1);
 731         else
 732                 sdrcrate >>= ((clk->rate / rate) - 1);
 733
 734         sp = omap2_sdrc_get_params(sdrcrate);
 735         if (!sp)
 736                 return -EINVAL;
 737
 738         if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
 739                 pr_debug("clock: will unlock SDRC DLL\n");
 740                 unlock_dll = 1;
 741         }
 742
 743         pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
 744                  validrate);
 745         pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
 746                  sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
 747
 748         /* REVISIT: SRAM code doesn't support other M2 divisors yet */
 749         WARN_ON(new_div != 1 && new_div != 2);
 750
 751         /* REVISIT: Add SDRC_MR changing to this code also */
 752         omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
 753                                   sp->actim_ctrlb, new_div, unlock_dll);
 754
 755         return 0;
 756 }
 757
 758
 759 static const struct clkops clkops_noncore_dpll_ops = {
 760         .enable         = &omap3_noncore_dpll_enable,
 761         .disable        = &omap3_noncore_dpll_disable,
 762 };
 763
 764 /* DPLL autoidle read/set code */
 765
 766
 767 /**
 768  * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
 769  * @clk: struct clk * of the DPLL to read
 770  *
 771  * Return the DPLL's autoidle bits, shifted down to bit 0.  Returns
 772  * -EINVAL if passed a null pointer or if the struct clk does not
 773  * appear to refer to a DPLL.
 774  */
 775 static u32 omap3_dpll_autoidle_read(struct clk *clk)
 776 {
 777         const struct dpll_data *dd;
 778         u32 v;
 779
 780         if (!clk || !clk->dpll_data)
 781                 return -EINVAL;
 782
 783         dd = clk->dpll_data;
 784
 785         v = __raw_readl(dd->autoidle_reg);
 786         v &= dd->autoidle_mask;
 787         v >>= __ffs(dd->autoidle_mask);
 788
 789         return v;
 790 }
 791
 792 /**
 793  * omap3_dpll_allow_idle - enable DPLL autoidle bits
 794  * @clk: struct clk * of the DPLL to operate on
 795  *
 796  * Enable DPLL automatic idle control.  This automatic idle mode
 797  * switching takes effect only when the DPLL is locked, at least on
 798  * OMAP3430.  The DPLL will enter low-power stop when its downstream
 799  * clocks are gated.  No return value.
 800  */
 801 static void omap3_dpll_allow_idle(struct clk *clk)
 802 {
 803         const struct dpll_data *dd;
 804         u32 v;
 805
 806         if (!clk || !clk->dpll_data)
 807                 return;
 808
 809         dd = clk->dpll_data;
 810
 811         /*
 812          * REVISIT: CORE DPLL can optionally enter low-power bypass
 813          * by writing 0x5 instead of 0x1.  Add some mechanism to
 814          * optionally enter this mode.
 815          */
 816         v = __raw_readl(dd->autoidle_reg);
 817         v &= ~dd->autoidle_mask;
 818         v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
 819         __raw_writel(v, dd->autoidle_reg);
 820 }
 821
 822 /**
 823  * omap3_dpll_deny_idle - prevent DPLL from automatically idling
 824  * @clk: struct clk * of the DPLL to operate on
 825  *
 826  * Disable DPLL automatic idle control.  No return value.
 827  */
 828 static void omap3_dpll_deny_idle(struct clk *clk)
 829 {
 830         const struct dpll_data *dd;
 831         u32 v;
 832
 833         if (!clk || !clk->dpll_data)
 834                 return;
 835
 836         dd = clk->dpll_data;
 837
 838         v = __raw_readl(dd->autoidle_reg);
 839         v &= ~dd->autoidle_mask;
 840         v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
 841         __raw_writel(v, dd->autoidle_reg);
 842 }
 843
 844 /* Clock control for DPLL outputs */
 845
 846 /**
 847  * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
 848  * @clk: DPLL output struct clk
 849  *
 850  * Using parent clock DPLL data, look up DPLL state.  If locked, set our
 851  * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
 852  */
 853 static unsigned long omap3_clkoutx2_recalc(struct clk *clk)
 854 {
 855         const struct dpll_data *dd;
 856         unsigned long rate;
 857         u32 v;
 858         struct clk *pclk;
 859
 860         /* Walk up the parents of clk, looking for a DPLL */
 861         pclk = clk->parent;
 862         while (pclk && !pclk->dpll_data)
 863                 pclk = pclk->parent;
 864
 865         /* clk does not have a DPLL as a parent? */
 866         WARN_ON(!pclk);
 867
 868         dd = pclk->dpll_data;
 869
 870         WARN_ON(!dd->enable_mask);
 871
 872         v = __raw_readl(dd->control_reg) & dd->enable_mask;
 873         v >>= __ffs(dd->enable_mask);
 874         if (v != OMAP3XXX_EN_DPLL_LOCKED)
 875                 rate = clk->parent->rate;
 876         else
 877                 rate = clk->parent->rate * 2;
 878         return rate;
 879 }
 880
 881 /* Common clock code */
 882
 883 /*
 884  * As it is structured now, this will prevent an OMAP2/3 multiboot
 885  * kernel from compiling.  This will need further attention.
 886  */
 887 #if defined(CONFIG_ARCH_OMAP3)
 888
 889 static struct clk_functions omap2_clk_functions = {
 890         .clk_enable             = omap2_clk_enable,
 891         .clk_disable            = omap2_clk_disable,
 892         .clk_round_rate         = omap2_clk_round_rate,
 893         .clk_set_rate           = omap2_clk_set_rate,
 894         .clk_set_parent         = omap2_clk_set_parent,
 895         .clk_disable_unused     = omap2_clk_disable_unused,
 896 };
 897
 898 /*
 899  * Set clocks for bypass mode for reboot to work.
 900  */
 901 void omap2_clk_prepare_for_reboot(void)
 902 {
 903         /* REVISIT: Not ready for 343x */
 904 #if 0
 905         u32 rate;
 906
 907         if (vclk == NULL || sclk == NULL)
 908                 return;
 909
 910         rate = clk_get_rate(sclk);
 911         clk_set_rate(vclk, rate);
 912 #endif
 913 }
 914
 915 /* REVISIT: Move this init stuff out into clock.c */
 916
 917 /*
 918  * Switch the MPU rate if specified on cmdline.
 919  * We cannot do this early until cmdline is parsed.
 920  */
 921 static int __init omap2_clk_arch_init(void)
 922 {
 923         if (!mpurate)
 924                 return -EINVAL;
 925
 926         /* REVISIT: not yet ready for 343x */
 927 #if 0
 928         if (clk_set_rate(&virt_prcm_set, mpurate))
 929                 printk(KERN_ERR "Could not find matching MPU rate\n");
 930 #endif
 931
 932         recalculate_root_clocks();
 933
 934         printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
 935                "%ld.%01ld/%ld/%ld MHz\n",
 936                (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
 937                (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
 938
 939         return 0;
 940 }
 941 arch_initcall(omap2_clk_arch_init);
 942
 943 int __init omap2_clk_init(void)
 944 {
 945         /* struct prcm_config *prcm; */
 946         struct omap_clk *c;
 947         /* u32 clkrate; */
 948         u32 cpu_clkflg;
 949
 950         if (cpu_is_omap34xx()) {
 951                 cpu_mask = RATE_IN_343X;
 952                 cpu_clkflg = CK_343X;
 953
 954                 /*
 955                  * Update this if there are further clock changes between ES2
 956                  * and production parts
 957                  */
 958                 if (omap_rev() == OMAP3430_REV_ES1_0) {
 959                         /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
 960                         cpu_clkflg |= CK_3430ES1;
 961                 } else {
 962                         cpu_mask |= RATE_IN_3430ES2;
 963                         cpu_clkflg |= CK_3430ES2;
 964                 }
 965         }
 966
 967         clk_init(&omap2_clk_functions);
 968
 969         for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
 970                 clk_preinit(c->lk.clk);
 971
 972         for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
 973                 if (c->cpu & cpu_clkflg) {
 974                         clkdev_add(&c->lk);
 975                         clk_register(c->lk.clk);
 976                         omap2_init_clk_clkdm(c->lk.clk);
 977                 }
 978
 979         /* REVISIT: Not yet ready for OMAP3 */
 980 #if 0
 981         /* Check the MPU rate set by bootloader */
 982         clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
 983         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 984                 if (!(prcm->flags & cpu_mask))
 985                         continue;
 986                 if (prcm->xtal_speed != sys_ck.rate)
 987                         continue;
 988                 if (prcm->dpll_speed <= clkrate)
 989                          break;
 990         }
 991         curr_prcm_set = prcm;
 992 #endif
 993
 994         recalculate_root_clocks();
 995
 996         printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
 997                "%ld.%01ld/%ld/%ld MHz\n",
 998                (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
 999                (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
1000
1001         /*
1002          * Only enable those clocks we will need, let the drivers
1003          * enable other clocks as necessary
1004          */
1005         clk_enable_init_clocks();
1006
1007         /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
1008         /* REVISIT: not yet ready for 343x */
1009 #if 0
1010         vclk = clk_get(NULL, "virt_prcm_set");
1011         sclk = clk_get(NULL, "sys_ck");
1012 #endif
1013         return 0;
1014 }
1015
1016 #endif