arch/arm/mach-omap2/clock24xx.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock24xx.h
   3  *
   4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2008 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  17 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
  18
  19 #include "clock.h"
  20
  21 #include "prm.h"
  22 #include "cm.h"
  23 #include "prm-regbits-24xx.h"
  24 #include "cm-regbits-24xx.h"
  25 #include "sdrc.h"
  26
  27 static void omap2_table_mpu_recalc(struct clk *clk);
  28 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
  29 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
  30 static void omap2_sys_clk_recalc(struct clk *clk);
  31 static void omap2_osc_clk_recalc(struct clk *clk);
  32 static void omap2_sys_clk_recalc(struct clk *clk);
  33 static void omap2_dpllcore_recalc(struct clk *clk);
  34 static int omap2_clk_fixed_enable(struct clk *clk);
  35 static void omap2_clk_fixed_disable(struct clk *clk);
  36 static int omap2_enable_osc_ck(struct clk *clk);
  37 static void omap2_disable_osc_ck(struct clk *clk);
  38 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
  39
  40 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  41  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  42  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  43  */
  44 struct prcm_config {
  45         unsigned long xtal_speed;       /* crystal rate */
  46         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  47         unsigned long mpu_speed;        /* speed of MPU */
  48         unsigned long cm_clksel_mpu;    /* mpu divider */
  49         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  50         unsigned long cm_clksel_gfx;    /* gfx dividers */
  51         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  52         unsigned long cm_clksel1_pll;   /* m,n */
  53         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  54         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  55         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  56         unsigned char flags;
  57 };
  58
  59 /*
  60  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  61  * These configurations are characterized by voltage and speed for clocks.
  62  * The device is only validated for certain combinations. One way to express
  63  * these combinations is via the 'ratio's' which the clocks operate with
  64  * respect to each other. These ratio sets are for a given voltage/DPLL
  65  * setting. All configurations can be described by a DPLL setting and a ratio
  66  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  67  *
  68  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  69  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  70  * 2430 (iva2.1, NOdsp, mdm)
  71  */
  72
  73 /* Core fields for cm_clksel, not ratio governed */
  74 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  75 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  76 #define RX_CLKSEL_SSI                   (0x5 << 20)
  77
  78 /*-------------------------------------------------------------------------
  79  * Voltage/DPLL ratios
  80  *-------------------------------------------------------------------------*/
  81
  82 /* 2430 Ratio's, 2430-Ratio Config 1 */
  83 #define R1_CLKSEL_L3                    (4 << 0)
  84 #define R1_CLKSEL_L4                    (2 << 5)
  85 #define R1_CLKSEL_USB                   (4 << 25)
  86 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  87                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
  88                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
  89 #define R1_CLKSEL_MPU                   (2 << 0)
  90 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
  91 #define R1_CLKSEL_DSP                   (2 << 0)
  92 #define R1_CLKSEL_DSP_IF                (2 << 5)
  93 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
  94 #define R1_CLKSEL_GFX                   (2 << 0)
  95 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
  96 #define R1_CLKSEL_MDM                   (4 << 0)
  97 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
  98
  99 /* 2430-Ratio Config 2 */
 100 #define R2_CLKSEL_L3                    (6 << 0)
 101 #define R2_CLKSEL_L4                    (2 << 5)
 102 #define R2_CLKSEL_USB                   (2 << 25)
 103 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 104                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 105                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 106 #define R2_CLKSEL_MPU                   (2 << 0)
 107 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 108 #define R2_CLKSEL_DSP                   (2 << 0)
 109 #define R2_CLKSEL_DSP_IF                (3 << 5)
 110 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 111 #define R2_CLKSEL_GFX                   (2 << 0)
 112 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 113 #define R2_CLKSEL_MDM                   (6 << 0)
 114 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 115
 116 /* 2430-Ratio Bootm (BYPASS) */
 117 #define RB_CLKSEL_L3                    (1 << 0)
 118 #define RB_CLKSEL_L4                    (1 << 5)
 119 #define RB_CLKSEL_USB                   (1 << 25)
 120 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 121                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 122                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 123 #define RB_CLKSEL_MPU                   (1 << 0)
 124 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 125 #define RB_CLKSEL_DSP                   (1 << 0)
 126 #define RB_CLKSEL_DSP_IF                (1 << 5)
 127 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 128 #define RB_CLKSEL_GFX                   (1 << 0)
 129 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 130 #define RB_CLKSEL_MDM                   (1 << 0)
 131 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 132
 133 /* 2420 Ratio Equivalents */
 134 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 135 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 136
 137 /* 2420-PRCM III 532MHz core */
 138 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 139 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 140 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 141 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 142                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 143                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 144                                         RIII_CLKSEL_L3
 145 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 146 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 147 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 148 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 149 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 150 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 151 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 152 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 153                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 154                                         RIII_CLKSEL_DSP
 155 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 156 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 157
 158 /* 2420-PRCM II 600MHz core */
 159 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 160 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 161 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 162 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 163                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 164                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 165                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 166 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 167 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 168 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 169 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 170 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 171 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 172 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 173 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 174                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 175                                         RII_CLKSEL_DSP
 176 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 177 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 178
 179 /* 2420-PRCM I 660MHz core */
 180 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 181 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 182 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 183 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 184                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 185                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 186                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 187 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 188 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 189 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 190 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 191 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 192 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 193 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 194 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 195                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 196                                         RI_CLKSEL_DSP
 197 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 198 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 199
 200 /* 2420-PRCM VII (boot) */
 201 #define RVII_CLKSEL_L3                  (1 << 0)
 202 #define RVII_CLKSEL_L4                  (1 << 5)
 203 #define RVII_CLKSEL_DSS1                (1 << 8)
 204 #define RVII_CLKSEL_DSS2                (0 << 13)
 205 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 206 #define RVII_CLKSEL_SSI                 (1 << 20)
 207 #define RVII_CLKSEL_USB                 (1 << 25)
 208
 209 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 210                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 211                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 212
 213 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 214 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 215
 216 #define RVII_CLKSEL_DSP                 (1 << 0)
 217 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 218 #define RVII_SYNC_DSP                   (0 << 7)
 219 #define RVII_CLKSEL_IVA                 (1 << 8)
 220 #define RVII_SYNC_IVA                   (0 << 13)
 221 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 222                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 223
 224 #define RVII_CLKSEL_GFX                 (1 << 0)
 225 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 226
 227 /*-------------------------------------------------------------------------
 228  * 2430 Target modes: Along with each configuration the CPU has several
 229  * modes which goes along with them. Modes mainly are the addition of
 230  * describe DPLL combinations to go along with a ratio.
 231  *-------------------------------------------------------------------------*/
 232
 233 /* Hardware governed */
 234 #define MX_48M_SRC                      (0 << 3)
 235 #define MX_54M_SRC                      (0 << 5)
 236 #define MX_APLLS_CLIKIN_12              (3 << 23)
 237 #define MX_APLLS_CLIKIN_13              (2 << 23)
 238 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 239
 240 /*
 241  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 242  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 243  */
 244 #define M5A_DPLL_MULT_12                (133 << 12)
 245 #define M5A_DPLL_DIV_12                 (5 << 8)
 246 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 247                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 248                                         MX_APLLS_CLIKIN_12
 249 #define M5A_DPLL_MULT_13                (61 << 12)
 250 #define M5A_DPLL_DIV_13                 (2 << 8)
 251 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 252                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 253                                         MX_APLLS_CLIKIN_13
 254 #define M5A_DPLL_MULT_19                (55 << 12)
 255 #define M5A_DPLL_DIV_19                 (3 << 8)
 256 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 257                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 258                                         MX_APLLS_CLIKIN_19_2
 259 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 260 #define M5B_DPLL_MULT_12                (50 << 12)
 261 #define M5B_DPLL_DIV_12                 (2 << 8)
 262 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 263                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 264                                         MX_APLLS_CLIKIN_12
 265 #define M5B_DPLL_MULT_13                (200 << 12)
 266 #define M5B_DPLL_DIV_13                 (12 << 8)
 267
 268 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 269                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 270                                         MX_APLLS_CLIKIN_13
 271 #define M5B_DPLL_MULT_19                (125 << 12)
 272 #define M5B_DPLL_DIV_19                 (31 << 8)
 273 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 274                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 275                                         MX_APLLS_CLIKIN_19_2
 276 /*
 277  * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
 278  */
 279 #define M4_DPLL_MULT_12                 (133 << 12)
 280 #define M4_DPLL_DIV_12                  (3 << 8)
 281 #define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 282                                         M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
 283                                         MX_APLLS_CLIKIN_12
 284
 285 #define M4_DPLL_MULT_13                 (399 << 12)
 286 #define M4_DPLL_DIV_13                  (12 << 8)
 287 #define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 288                                         M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
 289                                         MX_APLLS_CLIKIN_13
 290
 291 #define M4_DPLL_MULT_19                 (145 << 12)
 292 #define M4_DPLL_DIV_19                  (6 << 8)
 293 #define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 294                                         M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
 295                                         MX_APLLS_CLIKIN_19_2
 296
 297 /*
 298  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 299  */
 300 #define M3_DPLL_MULT_12                 (55 << 12)
 301 #define M3_DPLL_DIV_12                  (1 << 8)
 302 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 303                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 304                                         MX_APLLS_CLIKIN_12
 305 #define M3_DPLL_MULT_13                 (76 << 12)
 306 #define M3_DPLL_DIV_13                  (2 << 8)
 307 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 308                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 309                                         MX_APLLS_CLIKIN_13
 310 #define M3_DPLL_MULT_19                 (17 << 12)
 311 #define M3_DPLL_DIV_19                  (0 << 8)
 312 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 313                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 314                                         MX_APLLS_CLIKIN_19_2
 315
 316 /*
 317  * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
 318  */
 319 #define M2_DPLL_MULT_12                 (55 << 12)
 320 #define M2_DPLL_DIV_12                  (1 << 8)
 321 #define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 322                                         M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
 323                                         MX_APLLS_CLIKIN_12
 324
 325 /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
 326  * relock time issue */
 327 /* Core frequency changed from 330/165 to 329/164 MHz*/
 328 #define M2_DPLL_MULT_13                 (76 << 12)
 329 #define M2_DPLL_DIV_13                  (2 << 8)
 330 #define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 331                                         M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
 332                                         MX_APLLS_CLIKIN_13
 333
 334 #define M2_DPLL_MULT_19                 (17 << 12)
 335 #define M2_DPLL_DIV_19                  (0 << 8)
 336 #define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 337                                         M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
 338                                         MX_APLLS_CLIKIN_19_2
 339
 340 /* boot (boot) */
 341 #define MB_DPLL_MULT                    (1 << 12)
 342 #define MB_DPLL_DIV                     (0 << 8)
 343 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 344                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 345
 346 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 347                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 348
 349 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 350                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 351
 352 /*
 353  * 2430 - chassis (sedna)
 354  * 165 (ratio1) same as above #2
 355  * 150 (ratio1)
 356  * 133 (ratio2) same as above #4
 357  * 110 (ratio2) same as above #3
 358  * 104 (ratio2)
 359  * boot (boot)
 360  */
 361
 362 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 363 #define MI_DPLL_MULT_12                 (55 << 12)
 364 #define MI_DPLL_DIV_12                  (1 << 8)
 365 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 366                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 367                                         MX_APLLS_CLIKIN_12
 368
 369 /*
 370  * 2420 Equivalent - mode registers
 371  * PRCM II , target DPLL = 2*300MHz = 600MHz
 372  */
 373 #define MII_DPLL_MULT_12                (50 << 12)
 374 #define MII_DPLL_DIV_12                 (1 << 8)
 375 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 376                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 377                                         MX_APLLS_CLIKIN_12
 378 #define MII_DPLL_MULT_13                (300 << 12)
 379 #define MII_DPLL_DIV_13                 (12 << 8)
 380 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 381                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 382                                         MX_APLLS_CLIKIN_13
 383
 384 /* PRCM III target DPLL = 2*266 = 532MHz*/
 385 #define MIII_DPLL_MULT_12               (133 << 12)
 386 #define MIII_DPLL_DIV_12                (5 << 8)
 387 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 388                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 389                                         MX_APLLS_CLIKIN_12
 390 #define MIII_DPLL_MULT_13               (266 << 12)
 391 #define MIII_DPLL_DIV_13                (12 << 8)
 392 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 393                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 394                                         MX_APLLS_CLIKIN_13
 395
 396 /* PRCM VII (boot bypass) */
 397 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 398 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 399
 400 /* High and low operation value */
 401 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 402 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 403
 404 /* MPU speed defines */
 405 #define S12M    12000000
 406 #define S13M    13000000
 407 #define S19M    19200000
 408 #define S26M    26000000
 409 #define S100M   100000000
 410 #define S133M   133000000
 411 #define S150M   150000000
 412 #define S164M   164000000
 413 #define S165M   165000000
 414 #define S199M   199000000
 415 #define S200M   200000000
 416 #define S266M   266000000
 417 #define S300M   300000000
 418 #define S329M   329000000
 419 #define S330M   330000000
 420 #define S399M   399000000
 421 #define S400M   400000000
 422 #define S532M   532000000
 423 #define S600M   600000000
 424 #define S658M   658000000
 425 #define S660M   660000000
 426 #define S798M   798000000
 427
 428 /*-------------------------------------------------------------------------
 429  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 430  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 431  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 432  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 433  *
 434  * Filling in table based on H4 boards and 2430-SDPs variants available.
 435  * There are quite a few more rates combinations which could be defined.
 436  *
 437  * When multiple values are defined the start up will try and choose the
 438  * fastest one. If a 'fast' value is defined, then automatically, the /2
 439  * one should be included as it can be used.    Generally having more that
 440  * one fast set does not make sense, as static timings need to be changed
 441  * to change the set.    The exception is the bypass setting which is
 442  * availble for low power bypass.
 443  *
 444  * Note: This table needs to be sorted, fastest to slowest.
 445  *-------------------------------------------------------------------------*/
 446 static struct prcm_config rate_table[] = {
 447         /* PRCM I - FAST */
 448         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 449                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 450                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 451                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 452                 RATE_IN_242X},
 453
 454         /* PRCM II - FAST */
 455         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 456                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 457                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 458                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 459                 RATE_IN_242X},
 460
 461         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 462                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 463                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 464                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 465                 RATE_IN_242X},
 466
 467         /* PRCM III - FAST */
 468         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 469                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 470                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 471                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 472                 RATE_IN_242X},
 473
 474         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 475                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 476                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 477                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 478                 RATE_IN_242X},
 479
 480         /* PRCM II - SLOW */
 481         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 482                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 483                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 484                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 485                 RATE_IN_242X},
 486
 487         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 488                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 489                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 490                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 491                 RATE_IN_242X},
 492
 493         /* PRCM III - SLOW */
 494         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 495                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 496                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 497                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 498                 RATE_IN_242X},
 499
 500         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 501                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 502                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 503                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 504                 RATE_IN_242X},
 505
 506         /* PRCM-VII (boot-bypass) */
 507         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 508                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 509                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 510                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 511                 RATE_IN_242X},
 512
 513         /* PRCM-VII (boot-bypass) */
 514         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 515                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 516                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 517                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 518                 RATE_IN_242X},
 519
 520         /* PRCM #4 - ratio2 (ES2.1) - FAST */
 521         {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
 522                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 523                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 524                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 525                 SDRC_RFR_CTRL_133MHz,
 526                 RATE_IN_243X},
 527
 528         /* PRCM #2 - ratio1 (ES2) - FAST */
 529         {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 530                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 531                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 532                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 533                 SDRC_RFR_CTRL_165MHz,
 534                 RATE_IN_243X},
 535
 536         /* PRCM #5a - ratio1 - FAST */
 537         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 538                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 539                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 540                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 541                 SDRC_RFR_CTRL_133MHz,
 542                 RATE_IN_243X},
 543
 544         /* PRCM #5b - ratio1 - FAST */
 545         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 546                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 547                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 548                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 549                 SDRC_RFR_CTRL_100MHz,
 550                 RATE_IN_243X},
 551
 552         /* PRCM #4 - ratio1 (ES2.1) - SLOW */
 553         {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 554                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 555                 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
 556                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 557                 SDRC_RFR_CTRL_133MHz,
 558                 RATE_IN_243X},
 559
 560         /* PRCM #2 - ratio1 (ES2) - SLOW */
 561         {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 562                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 563                 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
 564                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 565                 SDRC_RFR_CTRL_165MHz,
 566                 RATE_IN_243X},
 567
 568         /* PRCM #5a - ratio1 - SLOW */
 569         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 570                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 571                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 572                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 573                 SDRC_RFR_CTRL_133MHz,
 574                 RATE_IN_243X},
 575
 576         /* PRCM #5b - ratio1 - SLOW*/
 577         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 578                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 579                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 580                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 581                 SDRC_RFR_CTRL_100MHz,
 582                 RATE_IN_243X},
 583
 584         /* PRCM-boot/bypass */
 585         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 586                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 587                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 588                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 589                 SDRC_RFR_CTRL_BYPASS,
 590                 RATE_IN_243X},
 591
 592         /* PRCM-boot/bypass */
 593         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 594                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 595                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 596                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 597                 SDRC_RFR_CTRL_BYPASS,
 598                 RATE_IN_243X},
 599
 600         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 601 };
 602
 603 /*-------------------------------------------------------------------------
 604  * 24xx clock tree.
 605  *
 606  * NOTE:In many cases here we are assigning a 'default' parent. In many
 607  *      cases the parent is selectable. The get/set parent calls will also
 608  *      switch sources.
 609  *
 610  *      Many some clocks say always_enabled, but they can be auto idled for
 611  *      power savings. They will always be available upon clock request.
 612  *
 613  *      Several sources are given initial rates which may be wrong, this will
 614  *      be fixed up in the init func.
 615  *
 616  *      Things are broadly separated below by clock domains. It is
 617  *      noteworthy that most periferals have dependencies on multiple clock
 618  *      domains. Many get their interface clocks from the L4 domain, but get
 619  *      functional clocks from fixed sources or other core domain derived
 620  *      clocks.
 621  *-------------------------------------------------------------------------*/
 622
 623 /* Base external input clocks */
 624 static struct clk func_32k_ck = {
 625         .name           = "func_32k_ck",
 626         .rate           = 32000,
 627         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 628                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 629         .recalc         = &propagate_rate,
 630 };
 631
 632 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 633 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 634         .name           = "osc_ck",
 635         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 636                                 RATE_PROPAGATES,
 637         .enable         = &omap2_enable_osc_ck,
 638         .disable        = &omap2_disable_osc_ck,
 639         .recalc         = &omap2_osc_clk_recalc,
 640 };
 641
 642 /* With out modem likely 12MHz, with modem likely 13MHz */
 643 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 644         .name           = "sys_ck",             /* ~ ref_clk also */
 645         .parent         = &osc_ck,
 646         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 647                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 648         .recalc         = &omap2_sys_clk_recalc,
 649 };
 650
 651 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 652         .name           = "alt_ck",
 653         .rate           = 54000000,
 654         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 655                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 656         .recalc         = &propagate_rate,
 657 };
 658
 659 /*
 660  * Analog domain root source clocks
 661  */
 662
 663 /* dpll_ck, is broken out in to special cases through clksel */
 664 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 665  * deal with this
 666  */
 667
 668 static struct dpll_data dpll_dd = {
 669         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 670         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 671         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 672         .max_multiplier         = 1024,
 673         .max_divider            = 16,
 674         .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 675 };
 676
 677 /*
 678  * XXX Cannot add round_rate here yet, as this is still a composite clock,
 679  * not just a DPLL
 680  */
 681 static struct clk dpll_ck = {
 682         .name           = "dpll_ck",
 683         .parent         = &sys_ck,              /* Can be func_32k also */
 684         .dpll_data      = &dpll_dd,
 685         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 686                                 RATE_PROPAGATES | ALWAYS_ENABLED,
 687         .recalc         = &omap2_dpllcore_recalc,
 688         .set_rate       = &omap2_reprogram_dpllcore,
 689 };
 690
 691 static struct clk apll96_ck = {
 692         .name           = "apll96_ck",
 693         .parent         = &sys_ck,
 694         .rate           = 96000000,
 695         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 696                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 697         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 698         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 699         .enable         = &omap2_clk_fixed_enable,
 700         .disable        = &omap2_clk_fixed_disable,
 701         .recalc         = &propagate_rate,
 702 };
 703
 704 static struct clk apll54_ck = {
 705         .name           = "apll54_ck",
 706         .parent         = &sys_ck,
 707         .rate           = 54000000,
 708         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 709                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 710         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 711         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 712         .enable         = &omap2_clk_fixed_enable,
 713         .disable        = &omap2_clk_fixed_disable,
 714         .recalc         = &propagate_rate,
 715 };
 716
 717 /*
 718  * PRCM digital base sources
 719  */
 720
 721 /* func_54m_ck */
 722
 723 static const struct clksel_rate func_54m_apll54_rates[] = {
 724         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 725         { .div = 0 },
 726 };
 727
 728 static const struct clksel_rate func_54m_alt_rates[] = {
 729         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 730         { .div = 0 },
 731 };
 732
 733 static const struct clksel func_54m_clksel[] = {
 734         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 735         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 736         { .parent = NULL },
 737 };
 738
 739 static struct clk func_54m_ck = {
 740         .name           = "func_54m_ck",
 741         .parent         = &apll54_ck,   /* can also be alt_clk */
 742         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 743                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 744         .init           = &omap2_init_clksel_parent,
 745         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 746         .clksel_mask    = OMAP24XX_54M_SOURCE,
 747         .clksel         = func_54m_clksel,
 748         .recalc         = &omap2_clksel_recalc,
 749 };
 750
 751 static struct clk core_ck = {
 752         .name           = "core_ck",
 753         .parent         = &dpll_ck,             /* can also be 32k */
 754         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 755                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 756         .recalc         = &followparent_recalc,
 757 };
 758
 759 /* func_96m_ck */
 760 static const struct clksel_rate func_96m_apll96_rates[] = {
 761         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 762         { .div = 0 },
 763 };
 764
 765 static const struct clksel_rate func_96m_alt_rates[] = {
 766         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 767         { .div = 0 },
 768 };
 769
 770 static const struct clksel func_96m_clksel[] = {
 771         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 772         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 773         { .parent = NULL }
 774 };
 775
 776 /* The parent of this clock is not selectable on 2420. */
 777 static struct clk func_96m_ck = {
 778         .name           = "func_96m_ck",
 779         .parent         = &apll96_ck,
 780         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 781                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 782         .init           = &omap2_init_clksel_parent,
 783         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 784         .clksel_mask    = OMAP2430_96M_SOURCE,
 785         .clksel         = func_96m_clksel,
 786         .recalc         = &omap2_clksel_recalc,
 787         .round_rate     = &omap2_clksel_round_rate,
 788         .set_rate       = &omap2_clksel_set_rate
 789 };
 790
 791 /* func_48m_ck */
 792
 793 static const struct clksel_rate func_48m_apll96_rates[] = {
 794         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 795         { .div = 0 },
 796 };
 797
 798 static const struct clksel_rate func_48m_alt_rates[] = {
 799         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 800         { .div = 0 },
 801 };
 802
 803 static const struct clksel func_48m_clksel[] = {
 804         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 805         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 806         { .parent = NULL }
 807 };
 808
 809 static struct clk func_48m_ck = {
 810         .name           = "func_48m_ck",
 811         .parent         = &apll96_ck,    /* 96M or Alt */
 812         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 813                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 814         .init           = &omap2_init_clksel_parent,
 815         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 816         .clksel_mask    = OMAP24XX_48M_SOURCE,
 817         .clksel         = func_48m_clksel,
 818         .recalc         = &omap2_clksel_recalc,
 819         .round_rate     = &omap2_clksel_round_rate,
 820         .set_rate       = &omap2_clksel_set_rate
 821 };
 822
 823 static struct clk func_12m_ck = {
 824         .name           = "func_12m_ck",
 825         .parent         = &func_48m_ck,
 826         .fixed_div      = 4,
 827         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 828                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 829         .recalc         = &omap2_fixed_divisor_recalc,
 830 };
 831
 832 /* Secure timer, only available in secure mode */
 833 static struct clk wdt1_osc_ck = {
 834         .name           = "ck_wdt1_osc",
 835         .parent         = &osc_ck,
 836         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 837         .recalc         = &followparent_recalc,
 838 };
 839
 840 /*
 841  * The common_clkout* clksel_rate structs are common to
 842  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 843  * sys_clkout2_* are 2420-only, so the
 844  * clksel_rate flags fields are inaccurate for those clocks. This is
 845  * harmless since access to those clocks are gated by the struct clk
 846  * flags fields, which mark them as 2420-only.
 847  */
 848 static const struct clksel_rate common_clkout_src_core_rates[] = {
 849         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 850         { .div = 0 }
 851 };
 852
 853 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 854         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 855         { .div = 0 }
 856 };
 857
 858 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 859         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 860         { .div = 0 }
 861 };
 862
 863 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 864         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 865         { .div = 0 }
 866 };
 867
 868 static const struct clksel common_clkout_src_clksel[] = {
 869         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 870         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 871         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 872         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 873         { .parent = NULL }
 874 };
 875
 876 static struct clk sys_clkout_src = {
 877         .name           = "sys_clkout_src",
 878         .parent         = &func_54m_ck,
 879         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 880                                 RATE_PROPAGATES,
 881         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 882         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 883         .init           = &omap2_init_clksel_parent,
 884         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 885         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 886         .clksel         = common_clkout_src_clksel,
 887         .recalc         = &omap2_clksel_recalc,
 888         .round_rate     = &omap2_clksel_round_rate,
 889         .set_rate       = &omap2_clksel_set_rate
 890 };
 891
 892 static const struct clksel_rate common_clkout_rates[] = {
 893         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 894         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 895         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 896         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 897         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 898         { .div = 0 },
 899 };
 900
 901 static const struct clksel sys_clkout_clksel[] = {
 902         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 903         { .parent = NULL }
 904 };
 905
 906 static struct clk sys_clkout = {
 907         .name           = "sys_clkout",
 908         .parent         = &sys_clkout_src,
 909         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 910                                 PARENT_CONTROLS_CLOCK,
 911         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 912         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 913         .clksel         = sys_clkout_clksel,
 914         .recalc         = &omap2_clksel_recalc,
 915         .round_rate     = &omap2_clksel_round_rate,
 916         .set_rate       = &omap2_clksel_set_rate
 917 };
 918
 919 /* In 2430, new in 2420 ES2 */
 920 static struct clk sys_clkout2_src = {
 921         .name           = "sys_clkout2_src",
 922         .parent         = &func_54m_ck,
 923         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
 924         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 925         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 926         .init           = &omap2_init_clksel_parent,
 927         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 928         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 929         .clksel         = common_clkout_src_clksel,
 930         .recalc         = &omap2_clksel_recalc,
 931         .round_rate     = &omap2_clksel_round_rate,
 932         .set_rate       = &omap2_clksel_set_rate
 933 };
 934
 935 static const struct clksel sys_clkout2_clksel[] = {
 936         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 937         { .parent = NULL }
 938 };
 939
 940 /* In 2430, new in 2420 ES2 */
 941 static struct clk sys_clkout2 = {
 942         .name           = "sys_clkout2",
 943         .parent         = &sys_clkout2_src,
 944         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
 945         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 946         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 947         .clksel         = sys_clkout2_clksel,
 948         .recalc         = &omap2_clksel_recalc,
 949         .round_rate     = &omap2_clksel_round_rate,
 950         .set_rate       = &omap2_clksel_set_rate
 951 };
 952
 953 static struct clk emul_ck = {
 954         .name           = "emul_ck",
 955         .parent         = &func_54m_ck,
 956         .flags          = CLOCK_IN_OMAP242X,
 957         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 958         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 959         .recalc         = &followparent_recalc,
 960
 961 };
 962
 963 /*
 964  * MPU clock domain
 965  *      Clocks:
 966  *              MPU_FCLK, MPU_ICLK
 967  *              INT_M_FCLK, INT_M_I_CLK
 968  *
 969  * - Individual clocks are hardware managed.
 970  * - Base divider comes from: CM_CLKSEL_MPU
 971  *
 972  */
 973 static const struct clksel_rate mpu_core_rates[] = {
 974         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 975         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 976         { .div = 4, .val = 4, .flags = RATE_IN_242X },
 977         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 978         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 979         { .div = 0 },
 980 };
 981
 982 static const struct clksel mpu_clksel[] = {
 983         { .parent = &core_ck, .rates = mpu_core_rates },
 984         { .parent = NULL }
 985 };
 986
 987 static struct clk mpu_ck = {    /* Control cpu */
 988         .name           = "mpu_ck",
 989         .parent         = &core_ck,
 990         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 991                                 ALWAYS_ENABLED | DELAYED_APP |
 992                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
 993         .init           = &omap2_init_clksel_parent,
 994         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
 995         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
 996         .clksel         = mpu_clksel,
 997         .recalc         = &omap2_clksel_recalc,
 998         .round_rate     = &omap2_clksel_round_rate,
 999         .set_rate       = &omap2_clksel_set_rate
1000 };
1001
1002 /*
1003  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
1004  * Clocks:
1005  *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
1006  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
1007  *
1008  * Won't be too specific here. The core clock comes into this block
1009  * it is divided then tee'ed. One branch goes directly to xyz enable
1010  * controls. The other branch gets further divided by 2 then possibly
1011  * routed into a synchronizer and out of clocks abc.
1012  */
1013 static const struct clksel_rate dsp_fck_core_rates[] = {
1014         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1015         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1016         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1017         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1018         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1019         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1020         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1021         { .div = 0 },
1022 };
1023
1024 static const struct clksel dsp_fck_clksel[] = {
1025         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1026         { .parent = NULL }
1027 };
1028
1029 static struct clk dsp_fck = {
1030         .name           = "dsp_fck",
1031         .parent         = &core_ck,
1032         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1033                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1034         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1035         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1036         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1037         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1038         .clksel         = dsp_fck_clksel,
1039         .recalc         = &omap2_clksel_recalc,
1040         .round_rate     = &omap2_clksel_round_rate,
1041         .set_rate       = &omap2_clksel_set_rate
1042 };
1043
1044 /* DSP interface clock */
1045 static const struct clksel_rate dsp_irate_ick_rates[] = {
1046         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1047         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1048         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1049         { .div = 0 },
1050 };
1051
1052 static const struct clksel dsp_irate_ick_clksel[] = {
1053         { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
1054         { .parent = NULL }
1055 };
1056
1057 /*
1058  * This clock does not exist as such in the TRM, but is added to
1059  * separate source selection from  XXX
1060  */
1061 static struct clk dsp_irate_ick = {
1062         .name           = "dsp_irate_ick",
1063         .parent         = &dsp_fck,
1064         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1065                                 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1066         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1067         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1068         .clksel         = dsp_irate_ick_clksel,
1069         .recalc         = &omap2_clksel_recalc,
1070         .round_rate     = &omap2_clksel_round_rate,
1071         .set_rate             = &omap2_clksel_set_rate
1072 };
1073
1074 /* 2420 only */
1075 static struct clk dsp_ick = {
1076         .name           = "dsp_ick",     /* apparently ipi and isp */
1077         .parent         = &dsp_irate_ick,
1078         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1079         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1080         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
1081 };
1082
1083 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1084 static struct clk iva2_1_ick = {
1085         .name           = "iva2_1_ick",
1086         .parent         = &dsp_irate_ick,
1087         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1088         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1089         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1090 };
1091
1092 static struct clk iva1_ifck = {
1093         .name           = "iva1_ifck",
1094         .parent         = &core_ck,
1095         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1096                                 RATE_PROPAGATES | DELAYED_APP,
1097         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1098         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1099         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1100         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1101         .clksel         = dsp_fck_clksel,
1102         .recalc         = &omap2_clksel_recalc,
1103         .round_rate     = &omap2_clksel_round_rate,
1104         .set_rate       = &omap2_clksel_set_rate
1105 };
1106
1107 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1108 static struct clk iva1_mpu_int_ifck = {
1109         .name           = "iva1_mpu_int_ifck",
1110         .parent         = &iva1_ifck,
1111         .flags          = CLOCK_IN_OMAP242X,
1112         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1113         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1114         .fixed_div      = 2,
1115         .recalc         = &omap2_fixed_divisor_recalc,
1116 };
1117
1118 /*
1119  * L3 clock domain
1120  * L3 clocks are used for both interface and functional clocks to
1121  * multiple entities. Some of these clocks are completely managed
1122  * by hardware, and some others allow software control. Hardware
1123  * managed ones general are based on directly CLK_REQ signals and
1124  * various auto idle settings. The functional spec sets many of these
1125  * as 'tie-high' for their enables.
1126  *
1127  * I-CLOCKS:
1128  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1129  *      CAM, HS-USB.
1130  * F-CLOCK
1131  *      SSI.
1132  *
1133  * GPMC memories and SDRC have timing and clock sensitive registers which
1134  * may very well need notification when the clock changes. Currently for low
1135  * operating points, these are taken care of in sleep.S.
1136  */
1137 static const struct clksel_rate core_l3_core_rates[] = {
1138         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1139         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1140         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1141         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1142         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1143         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1144         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1145         { .div = 0 }
1146 };
1147
1148 static const struct clksel core_l3_clksel[] = {
1149         { .parent = &core_ck, .rates = core_l3_core_rates },
1150         { .parent = NULL }
1151 };
1152
1153 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1154         .name           = "core_l3_ck",
1155         .parent         = &core_ck,
1156         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1157                                 ALWAYS_ENABLED | DELAYED_APP |
1158                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1159         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1160         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1161         .clksel         = core_l3_clksel,
1162         .recalc         = &omap2_clksel_recalc,
1163         .round_rate     = &omap2_clksel_round_rate,
1164         .set_rate       = &omap2_clksel_set_rate
1165 };
1166
1167 /* usb_l4_ick */
1168 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1169         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1170         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1171         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1172         { .div = 0 }
1173 };
1174
1175 static const struct clksel usb_l4_ick_clksel[] = {
1176         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1177         { .parent = NULL },
1178 };
1179
1180 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1181         .name           = "usb_l4_ick",
1182         .parent         = &core_l3_ck,
1183         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1184                                 DELAYED_APP | CONFIG_PARTICIPANT,
1185         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1186         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1187         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1188         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1189         .clksel         = usb_l4_ick_clksel,
1190         .recalc         = &omap2_clksel_recalc,
1191         .round_rate     = &omap2_clksel_round_rate,
1192         .set_rate       = &omap2_clksel_set_rate
1193 };
1194
1195 /*
1196  * SSI is in L3 management domain, its direct parent is core not l3,
1197  * many core power domain entities are grouped into the L3 clock
1198  * domain.
1199  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
1200  *
1201  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1202  */
1203 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1204         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1205         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1206         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1207         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1208         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1209         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1210         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1211         { .div = 0 }
1212 };
1213
1214 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1215         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1216         { .parent = NULL }
1217 };
1218
1219 static struct clk ssi_ssr_sst_fck = {
1220         .name           = "ssi_fck",
1221         .parent         = &core_ck,
1222         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1223                                 DELAYED_APP,
1224         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1225         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1226         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1227         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1228         .clksel         = ssi_ssr_sst_fck_clksel,
1229         .recalc         = &omap2_clksel_recalc,
1230         .round_rate     = &omap2_clksel_round_rate,
1231         .set_rate       = &omap2_clksel_set_rate
1232 };
1233
1234 /*
1235  * GFX clock domain
1236  *      Clocks:
1237  * GFX_FCLK, GFX_ICLK
1238  * GFX_CG1(2d), GFX_CG2(3d)
1239  *
1240  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1241  * The 2d and 3d clocks run at a hardware determined
1242  * divided value of fclk.
1243  *
1244  */
1245 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1246
1247 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1248 static const struct clksel gfx_fck_clksel[] = {
1249         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1250         { .parent = NULL },
1251 };
1252
1253 static struct clk gfx_3d_fck = {
1254         .name           = "gfx_3d_fck",
1255         .parent         = &core_l3_ck,
1256         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1257         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1258         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1259         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1260         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1261         .clksel         = gfx_fck_clksel,
1262         .recalc         = &omap2_clksel_recalc,
1263         .round_rate     = &omap2_clksel_round_rate,
1264         .set_rate       = &omap2_clksel_set_rate
1265 };
1266
1267 static struct clk gfx_2d_fck = {
1268         .name           = "gfx_2d_fck",
1269         .parent         = &core_l3_ck,
1270         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1271         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1272         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1273         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1274         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1275         .clksel         = gfx_fck_clksel,
1276         .recalc         = &omap2_clksel_recalc,
1277         .round_rate     = &omap2_clksel_round_rate,
1278         .set_rate       = &omap2_clksel_set_rate
1279 };
1280
1281 static struct clk gfx_ick = {
1282         .name           = "gfx_ick",            /* From l3 */
1283         .parent         = &core_l3_ck,
1284         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1285         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1286         .enable_bit     = OMAP_EN_GFX_SHIFT,
1287         .recalc         = &followparent_recalc,
1288 };
1289
1290 /*
1291  * Modem clock domain (2430)
1292  *      CLOCKS:
1293  *              MDM_OSC_CLK
1294  *              MDM_ICLK
1295  * These clocks are usable in chassis mode only.
1296  */
1297 static const struct clksel_rate mdm_ick_core_rates[] = {
1298         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1299         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1300         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1301         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1302         { .div = 0 }
1303 };
1304
1305 static const struct clksel mdm_ick_clksel[] = {
1306         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1307         { .parent = NULL }
1308 };
1309
1310 static struct clk mdm_ick = {           /* used both as a ick and fck */
1311         .name           = "mdm_ick",
1312         .parent         = &core_ck,
1313         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1314         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1315         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1316         .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1317         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1318         .clksel         = mdm_ick_clksel,
1319         .recalc         = &omap2_clksel_recalc,
1320         .round_rate     = &omap2_clksel_round_rate,
1321         .set_rate       = &omap2_clksel_set_rate
1322 };
1323
1324 static struct clk mdm_osc_ck = {
1325         .name           = "mdm_osc_ck",
1326         .parent         = &osc_ck,
1327         .flags          = CLOCK_IN_OMAP243X,
1328         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1329         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1330         .recalc         = &followparent_recalc,
1331 };
1332
1333 /*
1334  * L4 clock management domain
1335  *
1336  * This domain contains lots of interface clocks from the L4 interface, some
1337  * functional clocks.   Fixed APLL functional source clocks are managed in
1338  * this domain.
1339  */
1340 static const struct clksel_rate l4_core_l3_rates[] = {
1341         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1342         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1343         { .div = 0 }
1344 };
1345
1346 static const struct clksel l4_clksel[] = {
1347         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1348         { .parent = NULL }
1349 };
1350
1351 static struct clk l4_ck = {             /* used both as an ick and fck */
1352         .name           = "l4_ck",
1353         .parent         = &core_l3_ck,
1354         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1355                                 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1356         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1357         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1358         .clksel         = l4_clksel,
1359         .recalc         = &omap2_clksel_recalc,
1360         .round_rate     = &omap2_clksel_round_rate,
1361         .set_rate       = &omap2_clksel_set_rate
1362 };
1363
1364 static struct clk ssi_l4_ick = {
1365         .name           = "ssi_l4_ick",
1366         .parent         = &l4_ck,
1367         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1368         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1369         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1370         .recalc         = &followparent_recalc,
1371 };
1372
1373 /*
1374  * DSS clock domain
1375  * CLOCKs:
1376  * DSS_L4_ICLK, DSS_L3_ICLK,
1377  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1378  *
1379  * DSS is both initiator and target.
1380  */
1381 /* XXX Add RATE_NOT_VALIDATED */
1382
1383 static const struct clksel_rate dss1_fck_sys_rates[] = {
1384         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1385         { .div = 0 }
1386 };
1387
1388 static const struct clksel_rate dss1_fck_core_rates[] = {
1389         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1390         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1391         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1392         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1393         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1394         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1395         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1396         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1397         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1398         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1399         { .div = 0 }
1400 };
1401
1402 static const struct clksel dss1_fck_clksel[] = {
1403         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1404         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1405         { .parent = NULL },
1406 };
1407
1408 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1409         .name           = "dss_ick",
1410         .parent         = &l4_ck,       /* really both l3 and l4 */
1411         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1412         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1413         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1414         .recalc         = &followparent_recalc,
1415 };
1416
1417 static struct clk dss1_fck = {
1418         .name           = "dss1_fck",
1419         .parent         = &core_ck,             /* Core or sys */
1420         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1421                                 DELAYED_APP,
1422         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1423         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1424         .init           = &omap2_init_clksel_parent,
1425         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1426         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1427         .clksel         = dss1_fck_clksel,
1428         .recalc         = &omap2_clksel_recalc,
1429         .round_rate     = &omap2_clksel_round_rate,
1430         .set_rate       = &omap2_clksel_set_rate
1431 };
1432
1433 static const struct clksel_rate dss2_fck_sys_rates[] = {
1434         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1435         { .div = 0 }
1436 };
1437
1438 static const struct clksel_rate dss2_fck_48m_rates[] = {
1439         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1440         { .div = 0 }
1441 };
1442
1443 static const struct clksel dss2_fck_clksel[] = {
1444         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1445         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1446         { .parent = NULL }
1447 };
1448
1449 static struct clk dss2_fck = {          /* Alt clk used in power management */
1450         .name           = "dss2_fck",
1451         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1452         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1453                                 DELAYED_APP,
1454         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1455         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1456         .init           = &omap2_init_clksel_parent,
1457         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1458         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1459         .clksel         = dss2_fck_clksel,
1460         .recalc         = &followparent_recalc,
1461 };
1462
1463 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1464         .name           = "dss_54m_fck",        /* 54m tv clk */
1465         .parent         = &func_54m_ck,
1466         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1467         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1468         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1469         .recalc         = &followparent_recalc,
1470 };
1471
1472 /*
1473  * CORE power domain ICLK & FCLK defines.
1474  * Many of the these can have more than one possible parent. Entries
1475  * here will likely have an L4 interface parent, and may have multiple
1476  * functional clock parents.
1477  */
1478 static const struct clksel_rate gpt_alt_rates[] = {
1479         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1480         { .div = 0 }
1481 };
1482
1483 static const struct clksel omap24xx_gpt_clksel[] = {
1484         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1485         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1486         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1487         { .parent = NULL },
1488 };
1489
1490 static struct clk gpt1_ick = {
1491         .name           = "gpt1_ick",
1492         .parent         = &l4_ck,
1493         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1494         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1495         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1496         .recalc         = &followparent_recalc,
1497 };
1498
1499 static struct clk gpt1_fck = {
1500         .name           = "gpt1_fck",
1501         .parent         = &func_32k_ck,
1502         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1503         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1504         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1505         .init           = &omap2_init_clksel_parent,
1506         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
1507         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1508         .clksel         = omap24xx_gpt_clksel,
1509         .recalc         = &omap2_clksel_recalc,
1510         .round_rate     = &omap2_clksel_round_rate,
1511         .set_rate       = &omap2_clksel_set_rate
1512 };
1513
1514 static struct clk gpt2_ick = {
1515         .name           = "gpt2_ick",
1516         .parent         = &l4_ck,
1517         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1518         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1519         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1520         .recalc         = &followparent_recalc,
1521 };
1522
1523 static struct clk gpt2_fck = {
1524         .name           = "gpt2_fck",
1525         .parent         = &func_32k_ck,
1526         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1527         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1528         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1529         .init           = &omap2_init_clksel_parent,
1530         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1531         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1532         .clksel         = omap24xx_gpt_clksel,
1533         .recalc         = &omap2_clksel_recalc,
1534 };
1535
1536 static struct clk gpt3_ick = {
1537         .name           = "gpt3_ick",
1538         .parent         = &l4_ck,
1539         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1540         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1541         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1542         .recalc         = &followparent_recalc,
1543 };
1544
1545 static struct clk gpt3_fck = {
1546         .name           = "gpt3_fck",
1547         .parent         = &func_32k_ck,
1548         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1549         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1550         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1551         .init           = &omap2_init_clksel_parent,
1552         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1553         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1554         .clksel         = omap24xx_gpt_clksel,
1555         .recalc         = &omap2_clksel_recalc,
1556 };
1557
1558 static struct clk gpt4_ick = {
1559         .name           = "gpt4_ick",
1560         .parent         = &l4_ck,
1561         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1562         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1563         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1564         .recalc         = &followparent_recalc,
1565 };
1566
1567 static struct clk gpt4_fck = {
1568         .name           = "gpt4_fck",
1569         .parent         = &func_32k_ck,
1570         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1571         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1572         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1573         .init           = &omap2_init_clksel_parent,
1574         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1575         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1576         .clksel         = omap24xx_gpt_clksel,
1577         .recalc         = &omap2_clksel_recalc,
1578 };
1579
1580 static struct clk gpt5_ick = {
1581         .name           = "gpt5_ick",
1582         .parent         = &l4_ck,
1583         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1584         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1585         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1586         .recalc         = &followparent_recalc,
1587 };
1588
1589 static struct clk gpt5_fck = {
1590         .name           = "gpt5_fck",
1591         .parent         = &func_32k_ck,
1592         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1593         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1594         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1595         .init           = &omap2_init_clksel_parent,
1596         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1597         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1598         .clksel         = omap24xx_gpt_clksel,
1599         .recalc         = &omap2_clksel_recalc,
1600 };
1601
1602 static struct clk gpt6_ick = {
1603         .name           = "gpt6_ick",
1604         .parent         = &l4_ck,
1605         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1606         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1607         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1608         .recalc         = &followparent_recalc,
1609 };
1610
1611 static struct clk gpt6_fck = {
1612         .name           = "gpt6_fck",
1613         .parent         = &func_32k_ck,
1614         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1615         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1616         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1617         .init           = &omap2_init_clksel_parent,
1618         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1619         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1620         .clksel         = omap24xx_gpt_clksel,
1621         .recalc         = &omap2_clksel_recalc,
1622 };
1623
1624 static struct clk gpt7_ick = {
1625         .name           = "gpt7_ick",
1626         .parent         = &l4_ck,
1627         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1628         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1629         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1630         .recalc         = &followparent_recalc,
1631 };
1632
1633 static struct clk gpt7_fck = {
1634         .name           = "gpt7_fck",
1635         .parent         = &func_32k_ck,
1636         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1637         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1638         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1639         .init           = &omap2_init_clksel_parent,
1640         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1641         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1642         .clksel         = omap24xx_gpt_clksel,
1643         .recalc         = &omap2_clksel_recalc,
1644 };
1645
1646 static struct clk gpt8_ick = {
1647         .name           = "gpt8_ick",
1648         .parent         = &l4_ck,
1649         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1650         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1651         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1652         .recalc         = &followparent_recalc,
1653 };
1654
1655 static struct clk gpt8_fck = {
1656         .name           = "gpt8_fck",
1657         .parent         = &func_32k_ck,
1658         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1659         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1660         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1661         .init           = &omap2_init_clksel_parent,
1662         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1663         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1664         .clksel         = omap24xx_gpt_clksel,
1665         .recalc         = &omap2_clksel_recalc,
1666 };
1667
1668 static struct clk gpt9_ick = {
1669         .name           = "gpt9_ick",
1670         .parent         = &l4_ck,
1671         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1672         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1673         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1674         .recalc         = &followparent_recalc,
1675 };
1676
1677 static struct clk gpt9_fck = {
1678         .name           = "gpt9_fck",
1679         .parent         = &func_32k_ck,
1680         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1681         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1682         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1683         .init           = &omap2_init_clksel_parent,
1684         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1685         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1686         .clksel         = omap24xx_gpt_clksel,
1687         .recalc         = &omap2_clksel_recalc,
1688 };
1689
1690 static struct clk gpt10_ick = {
1691         .name           = "gpt10_ick",
1692         .parent         = &l4_ck,
1693         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1694         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1695         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1696         .recalc         = &followparent_recalc,
1697 };
1698
1699 static struct clk gpt10_fck = {
1700         .name           = "gpt10_fck",
1701         .parent         = &func_32k_ck,
1702         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1703         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1704         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1705         .init           = &omap2_init_clksel_parent,
1706         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1707         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1708         .clksel         = omap24xx_gpt_clksel,
1709         .recalc         = &omap2_clksel_recalc,
1710 };
1711
1712 static struct clk gpt11_ick = {
1713         .name           = "gpt11_ick",
1714         .parent         = &l4_ck,
1715         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1716         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1717         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1718         .recalc         = &followparent_recalc,
1719 };
1720
1721 static struct clk gpt11_fck = {
1722         .name           = "gpt11_fck",
1723         .parent         = &func_32k_ck,
1724         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1725         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1726         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1727         .init           = &omap2_init_clksel_parent,
1728         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1729         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1730         .clksel         = omap24xx_gpt_clksel,
1731         .recalc         = &omap2_clksel_recalc,
1732 };
1733
1734 static struct clk gpt12_ick = {
1735         .name           = "gpt12_ick",
1736         .parent         = &l4_ck,
1737         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1738         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1739         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1740         .recalc         = &followparent_recalc,
1741 };
1742
1743 static struct clk gpt12_fck = {
1744         .name           = "gpt12_fck",
1745         .parent         = &func_32k_ck,
1746         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1747         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1748         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1749         .init           = &omap2_init_clksel_parent,
1750         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1751         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1752         .clksel         = omap24xx_gpt_clksel,
1753         .recalc         = &omap2_clksel_recalc,
1754 };
1755
1756 static struct clk mcbsp1_ick = {
1757         .name           = "mcbsp_ick",
1758         .id             = 1,
1759         .parent         = &l4_ck,
1760         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1761         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1762         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1763         .recalc         = &followparent_recalc,
1764 };
1765
1766 static struct clk mcbsp1_fck = {
1767         .name           = "mcbsp_fck",
1768         .id             = 1,
1769         .parent         = &func_96m_ck,
1770         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1771         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1772         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1773         .recalc         = &followparent_recalc,
1774 };
1775
1776 static struct clk mcbsp2_ick = {
1777         .name           = "mcbsp_ick",
1778         .id             = 2,
1779         .parent         = &l4_ck,
1780         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1781         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1782         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1783         .recalc         = &followparent_recalc,
1784 };
1785
1786 static struct clk mcbsp2_fck = {
1787         .name           = "mcbsp_fck",
1788         .id             = 2,
1789         .parent         = &func_96m_ck,
1790         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1791         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1792         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1793         .recalc         = &followparent_recalc,
1794 };
1795
1796 static struct clk mcbsp3_ick = {
1797         .name           = "mcbsp_ick",
1798         .id             = 3,
1799         .parent         = &l4_ck,
1800         .flags          = CLOCK_IN_OMAP243X,
1801         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1802         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1803         .recalc         = &followparent_recalc,
1804 };
1805
1806 static struct clk mcbsp3_fck = {
1807         .name           = "mcbsp_fck",
1808         .id             = 3,
1809         .parent         = &func_96m_ck,
1810         .flags          = CLOCK_IN_OMAP243X,
1811         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1812         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1813         .recalc         = &followparent_recalc,
1814 };
1815
1816 static struct clk mcbsp4_ick = {
1817         .name           = "mcbsp_ick",
1818         .id             = 4,
1819         .parent         = &l4_ck,
1820         .flags          = CLOCK_IN_OMAP243X,
1821         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1822         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1823         .recalc         = &followparent_recalc,
1824 };
1825
1826 static struct clk mcbsp4_fck = {
1827         .name           = "mcbsp_fck",
1828         .id             = 4,
1829         .parent         = &func_96m_ck,
1830         .flags          = CLOCK_IN_OMAP243X,
1831         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1832         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1833         .recalc         = &followparent_recalc,
1834 };
1835
1836 static struct clk mcbsp5_ick = {
1837         .name           = "mcbsp_ick",
1838         .id             = 5,
1839         .parent         = &l4_ck,
1840         .flags          = CLOCK_IN_OMAP243X,
1841         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1842         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1843         .recalc         = &followparent_recalc,
1844 };
1845
1846 static struct clk mcbsp5_fck = {
1847         .name           = "mcbsp_fck",
1848         .id             = 5,
1849         .parent         = &func_96m_ck,
1850         .flags          = CLOCK_IN_OMAP243X,
1851         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1852         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1853         .recalc         = &followparent_recalc,
1854 };
1855
1856 static struct clk mcspi1_ick = {
1857         .name           = "mcspi_ick",
1858         .id             = 1,
1859         .parent         = &l4_ck,
1860         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1861         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1862         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1863         .recalc         = &followparent_recalc,
1864 };
1865
1866 static struct clk mcspi1_fck = {
1867         .name           = "mcspi_fck",
1868         .id             = 1,
1869         .parent         = &func_48m_ck,
1870         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1871         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1872         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1873         .recalc         = &followparent_recalc,
1874 };
1875
1876 static struct clk mcspi2_ick = {
1877         .name           = "mcspi_ick",
1878         .id             = 2,
1879         .parent         = &l4_ck,
1880         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1881         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1882         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1883         .recalc         = &followparent_recalc,
1884 };
1885
1886 static struct clk mcspi2_fck = {
1887         .name           = "mcspi_fck",
1888         .id             = 2,
1889         .parent         = &func_48m_ck,
1890         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1891         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1892         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1893         .recalc         = &followparent_recalc,
1894 };
1895
1896 static struct clk mcspi3_ick = {
1897         .name           = "mcspi_ick",
1898         .id             = 3,
1899         .parent         = &l4_ck,
1900         .flags          = CLOCK_IN_OMAP243X,
1901         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1902         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1903         .recalc         = &followparent_recalc,
1904 };
1905
1906 static struct clk mcspi3_fck = {
1907         .name           = "mcspi_fck",
1908         .id             = 3,
1909         .parent         = &func_48m_ck,
1910         .flags          = CLOCK_IN_OMAP243X,
1911         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1912         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1913         .recalc         = &followparent_recalc,
1914 };
1915
1916 static struct clk uart1_ick = {
1917         .name           = "uart1_ick",
1918         .parent         = &l4_ck,
1919         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1920         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1921         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1922         .recalc         = &followparent_recalc,
1923 };
1924
1925 static struct clk uart1_fck = {
1926         .name           = "uart1_fck",
1927         .parent         = &func_48m_ck,
1928         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1929         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1930         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1931         .recalc         = &followparent_recalc,
1932 };
1933
1934 static struct clk uart2_ick = {
1935         .name           = "uart2_ick",
1936         .parent         = &l4_ck,
1937         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1938         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1939         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1940         .recalc         = &followparent_recalc,
1941 };
1942
1943 static struct clk uart2_fck = {
1944         .name           = "uart2_fck",
1945         .parent         = &func_48m_ck,
1946         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1947         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1948         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1949         .recalc         = &followparent_recalc,
1950 };
1951
1952 static struct clk uart3_ick = {
1953         .name           = "uart3_ick",
1954         .parent         = &l4_ck,
1955         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1956         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1957         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1958         .recalc         = &followparent_recalc,
1959 };
1960
1961 static struct clk uart3_fck = {
1962         .name           = "uart3_fck",
1963         .parent         = &func_48m_ck,
1964         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1965         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1966         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1967         .recalc         = &followparent_recalc,
1968 };
1969
1970 static struct clk gpios_ick = {
1971         .name           = "gpios_ick",
1972         .parent         = &l4_ck,
1973         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1974         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1975         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1976         .recalc         = &followparent_recalc,
1977 };
1978
1979 static struct clk gpios_fck = {
1980         .name           = "gpios_fck",
1981         .parent         = &func_32k_ck,
1982         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1983         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1984         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1985         .recalc         = &followparent_recalc,
1986 };
1987
1988 static struct clk mpu_wdt_ick = {
1989         .name           = "mpu_wdt_ick",
1990         .parent         = &l4_ck,
1991         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1992         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1993         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1994         .recalc         = &followparent_recalc,
1995 };
1996
1997 static struct clk mpu_wdt_fck = {
1998         .name           = "mpu_wdt_fck",
1999         .parent         = &func_32k_ck,
2000         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2001         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2002         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2003         .recalc         = &followparent_recalc,
2004 };
2005
2006 static struct clk sync_32k_ick = {
2007         .name           = "sync_32k_ick",
2008         .parent         = &l4_ck,
2009         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2010         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2011         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2012         .recalc         = &followparent_recalc,
2013 };
2014 static struct clk wdt1_ick = {
2015         .name           = "wdt1_ick",
2016         .parent         = &l4_ck,
2017         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2018         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2019         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2020         .recalc         = &followparent_recalc,
2021 };
2022 static struct clk omapctrl_ick = {
2023         .name           = "omapctrl_ick",
2024         .parent         = &l4_ck,
2025         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2026         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2027         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2028         .recalc         = &followparent_recalc,
2029 };
2030 static struct clk icr_ick = {
2031         .name           = "icr_ick",
2032         .parent         = &l4_ck,
2033         .flags          = CLOCK_IN_OMAP243X,
2034         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2035         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2036         .recalc         = &followparent_recalc,
2037 };
2038
2039 static struct clk cam_ick = {
2040         .name           = "cam_ick",
2041         .parent         = &l4_ck,
2042         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2043         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2044         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2045         .recalc         = &followparent_recalc,
2046 };
2047
2048 static struct clk cam_fck = {
2049         .name           = "cam_fck",
2050         .parent         = &func_96m_ck,
2051         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2052         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2053         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2054         .recalc         = &followparent_recalc,
2055 };
2056
2057 static struct clk mailboxes_ick = {
2058         .name           = "mailboxes_ick",
2059         .parent         = &l4_ck,
2060         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2061         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2062         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2063         .recalc         = &followparent_recalc,
2064 };
2065
2066 static struct clk wdt4_ick = {
2067         .name           = "wdt4_ick",
2068         .parent         = &l4_ck,
2069         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2070         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2071         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2072         .recalc         = &followparent_recalc,
2073 };
2074
2075 static struct clk wdt4_fck = {
2076         .name           = "wdt4_fck",
2077         .parent         = &func_32k_ck,
2078         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2079         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2080         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2081         .recalc         = &followparent_recalc,
2082 };
2083
2084 static struct clk wdt3_ick = {
2085         .name           = "wdt3_ick",
2086         .parent         = &l4_ck,
2087         .flags          = CLOCK_IN_OMAP242X,
2088         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2089         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2090         .recalc         = &followparent_recalc,
2091 };
2092
2093 static struct clk wdt3_fck = {
2094         .name           = "wdt3_fck",
2095         .parent         = &func_32k_ck,
2096         .flags          = CLOCK_IN_OMAP242X,
2097         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2098         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2099         .recalc         = &followparent_recalc,
2100 };
2101
2102 static struct clk mspro_ick = {
2103         .name           = "mspro_ick",
2104         .parent         = &l4_ck,
2105         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2106         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2107         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2108         .recalc         = &followparent_recalc,
2109 };
2110
2111 static struct clk mspro_fck = {
2112         .name           = "mspro_fck",
2113         .parent         = &func_96m_ck,
2114         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2115         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2116         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2117         .recalc         = &followparent_recalc,
2118 };
2119
2120 static struct clk mmc_ick = {
2121         .name           = "mmc_ick",
2122         .parent         = &l4_ck,
2123         .flags          = CLOCK_IN_OMAP242X,
2124         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2125         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2126         .recalc         = &followparent_recalc,
2127 };
2128
2129 static struct clk mmc_fck = {
2130         .name           = "mmc_fck",
2131         .parent         = &func_96m_ck,
2132         .flags          = CLOCK_IN_OMAP242X,
2133         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2134         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2135         .recalc         = &followparent_recalc,
2136 };
2137
2138 static struct clk fac_ick = {
2139         .name           = "fac_ick",
2140         .parent         = &l4_ck,
2141         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2142         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2143         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2144         .recalc         = &followparent_recalc,
2145 };
2146
2147 static struct clk fac_fck = {
2148         .name           = "fac_fck",
2149         .parent         = &func_12m_ck,
2150         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2151         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2152         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2153         .recalc         = &followparent_recalc,
2154 };
2155
2156 static struct clk eac_ick = {
2157         .name           = "eac_ick",
2158         .parent         = &l4_ck,
2159         .flags          = CLOCK_IN_OMAP242X,
2160         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2161         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2162         .recalc         = &followparent_recalc,
2163 };
2164
2165 static struct clk eac_fck = {
2166         .name           = "eac_fck",
2167         .parent         = &func_96m_ck,
2168         .flags          = CLOCK_IN_OMAP242X,
2169         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2170         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2171         .recalc         = &followparent_recalc,
2172 };
2173
2174 static struct clk hdq_ick = {
2175         .name           = "hdq_ick",
2176         .parent         = &l4_ck,
2177         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2178         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2179         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2180         .recalc         = &followparent_recalc,
2181 };
2182
2183 static struct clk hdq_fck = {
2184         .name           = "hdq_fck",
2185         .parent         = &func_12m_ck,
2186         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2187         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2188         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2189         .recalc         = &followparent_recalc,
2190 };
2191
2192 static struct clk i2c2_ick = {
2193         .name           = "i2c_ick",
2194         .id             = 2,
2195         .parent         = &l4_ck,
2196         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2197         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2198         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2199         .recalc         = &followparent_recalc,
2200 };
2201
2202 static struct clk i2c2_fck = {
2203         .name           = "i2c_fck",
2204         .id             = 2,
2205         .parent         = &func_12m_ck,
2206         .flags          = CLOCK_IN_OMAP242X,
2207         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2208         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2209         .recalc         = &followparent_recalc,
2210 };
2211
2212 static struct clk i2chs2_fck = {
2213         .name           = "i2chs_fck",
2214         .id             = 2,
2215         .parent         = &func_96m_ck,
2216         .flags          = CLOCK_IN_OMAP243X,
2217         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2218         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2219         .recalc         = &followparent_recalc,
2220 };
2221
2222 static struct clk i2c1_ick = {
2223         .name           = "i2c_ick",
2224         .id             = 1,
2225         .parent         = &l4_ck,
2226         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2227         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2228         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2229         .recalc         = &followparent_recalc,
2230 };
2231
2232 static struct clk i2c1_fck = {
2233         .name           = "i2c_fck",
2234         .id             = 1,
2235         .parent         = &func_12m_ck,
2236         .flags          = CLOCK_IN_OMAP242X,
2237         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2238         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2239         .recalc         = &followparent_recalc,
2240 };
2241
2242 static struct clk i2chs1_fck = {
2243         .name           = "i2chs_fck",
2244         .id             = 1,
2245         .parent         = &func_96m_ck,
2246         .flags          = CLOCK_IN_OMAP243X,
2247         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2248         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2249         .recalc         = &followparent_recalc,
2250 };
2251
2252 static struct clk gpmc_fck = {
2253         .name           = "gpmc_fck",
2254         .parent         = &core_l3_ck,
2255         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2256         .recalc         = &followparent_recalc,
2257 };
2258
2259 static struct clk sdma_fck = {
2260         .name           = "sdma_fck",
2261         .parent         = &core_l3_ck,
2262         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2263         .recalc         = &followparent_recalc,
2264 };
2265
2266 static struct clk sdma_ick = {
2267         .name           = "sdma_ick",
2268         .parent         = &l4_ck,
2269         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2270         .recalc         = &followparent_recalc,
2271 };
2272
2273 static struct clk vlynq_ick = {
2274         .name           = "vlynq_ick",
2275         .parent         = &core_l3_ck,
2276         .flags          = CLOCK_IN_OMAP242X,
2277         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2278         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2279         .recalc         = &followparent_recalc,
2280 };
2281
2282 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2283         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2284         { .div = 0 }
2285 };
2286
2287 static const struct clksel_rate vlynq_fck_core_rates[] = {
2288         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2289         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2290         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2291         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2292         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2293         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2294         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2295         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2296         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2297         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2298         { .div = 0 }
2299 };
2300
2301 static const struct clksel vlynq_fck_clksel[] = {
2302         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2303         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2304         { .parent = NULL }
2305 };
2306
2307 static struct clk vlynq_fck = {
2308         .name           = "vlynq_fck",
2309         .parent         = &func_96m_ck,
2310         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
2311         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2312         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2313         .init           = &omap2_init_clksel_parent,
2314         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2315         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2316         .clksel         = vlynq_fck_clksel,
2317         .recalc         = &omap2_clksel_recalc,
2318         .round_rate     = &omap2_clksel_round_rate,
2319         .set_rate       = &omap2_clksel_set_rate
2320 };
2321
2322 static struct clk sdrc_ick = {
2323         .name           = "sdrc_ick",
2324         .parent         = &l4_ck,
2325         .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2326         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2327         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2328         .recalc         = &followparent_recalc,
2329 };
2330
2331 static struct clk des_ick = {
2332         .name           = "des_ick",
2333         .parent         = &l4_ck,
2334         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2335         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2336         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2337         .recalc         = &followparent_recalc,
2338 };
2339
2340 static struct clk sha_ick = {
2341         .name           = "sha_ick",
2342         .parent         = &l4_ck,
2343         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2344         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2345         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2346         .recalc         = &followparent_recalc,
2347 };
2348
2349 static struct clk rng_ick = {
2350         .name           = "rng_ick",
2351         .parent         = &l4_ck,
2352         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2353         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2354         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2355         .recalc         = &followparent_recalc,
2356 };
2357
2358 static struct clk aes_ick = {
2359         .name           = "aes_ick",
2360         .parent         = &l4_ck,
2361         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2362         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2363         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2364         .recalc         = &followparent_recalc,
2365 };
2366
2367 static struct clk pka_ick = {
2368         .name           = "pka_ick",
2369         .parent         = &l4_ck,
2370         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2371         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2372         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2373         .recalc         = &followparent_recalc,
2374 };
2375
2376 static struct clk usb_fck = {
2377         .name           = "usb_fck",
2378         .parent         = &func_48m_ck,
2379         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2380         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2381         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2382         .recalc         = &followparent_recalc,
2383 };
2384
2385 static struct clk usbhs_ick = {
2386         .name           = "usbhs_ick",
2387         .parent         = &core_l3_ck,
2388         .flags          = CLOCK_IN_OMAP243X,
2389         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2390         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2391         .recalc         = &followparent_recalc,
2392 };
2393
2394 static struct clk mmchs1_ick = {
2395         .name           = "mmchs_ick",
2396         .id             = 1,
2397         .parent         = &l4_ck,
2398         .flags          = CLOCK_IN_OMAP243X,
2399         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2400         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2401         .recalc         = &followparent_recalc,
2402 };
2403
2404 static struct clk mmchs1_fck = {
2405         .name           = "mmchs_fck",
2406         .id             = 1,
2407         .parent         = &func_96m_ck,
2408         .flags          = CLOCK_IN_OMAP243X,
2409         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2410         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2411         .recalc         = &followparent_recalc,
2412 };
2413
2414 static struct clk mmchs2_ick = {
2415         .name           = "mmchs_ick",
2416         .id             = 2,
2417         .parent         = &l4_ck,
2418         .flags          = CLOCK_IN_OMAP243X,
2419         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2420         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2421         .recalc         = &followparent_recalc,
2422 };
2423
2424 static struct clk mmchs2_fck = {
2425         .name           = "mmchs_fck",
2426         .id             = 2,
2427         .parent         = &func_96m_ck,
2428         .flags          = CLOCK_IN_OMAP243X,
2429         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2430         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2431         .recalc         = &followparent_recalc,
2432 };
2433
2434 static struct clk gpio5_ick = {
2435         .name           = "gpio5_ick",
2436         .parent         = &l4_ck,
2437         .flags          = CLOCK_IN_OMAP243X,
2438         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2439         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2440         .recalc         = &followparent_recalc,
2441 };
2442
2443 static struct clk gpio5_fck = {
2444         .name           = "gpio5_fck",
2445         .parent         = &func_32k_ck,
2446         .flags          = CLOCK_IN_OMAP243X,
2447         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2448         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2449         .recalc         = &followparent_recalc,
2450 };
2451
2452 static struct clk mdm_intc_ick = {
2453         .name           = "mdm_intc_ick",
2454         .parent         = &l4_ck,
2455         .flags          = CLOCK_IN_OMAP243X,
2456         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2457         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2458         .recalc         = &followparent_recalc,
2459 };
2460
2461 static struct clk mmchsdb1_fck = {
2462         .name           = "mmchsdb_fck",
2463         .id             = 1,
2464         .parent         = &func_32k_ck,
2465         .flags          = CLOCK_IN_OMAP243X,
2466         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2467         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2468         .recalc         = &followparent_recalc,
2469 };
2470
2471 static struct clk mmchsdb2_fck = {
2472         .name           = "mmchsdb_fck",
2473         .id             = 2,
2474         .parent         = &func_32k_ck,
2475         .flags          = CLOCK_IN_OMAP243X,
2476         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2477         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2478         .recalc         = &followparent_recalc,
2479 };
2480
2481 /*
2482  * This clock is a composite clock which does entire set changes then
2483  * forces a rebalance. It keys on the MPU speed, but it really could
2484  * be any key speed part of a set in the rate table.
2485  *
2486  * to really change a set, you need memory table sets which get changed
2487  * in sram, pre-notifiers & post notifiers, changing the top set, without
2488  * having low level display recalc's won't work... this is why dpm notifiers
2489  * work, isr's off, walk a list of clocks already _off_ and not messing with
2490  * the bus.
2491  *
2492  * This clock should have no parent. It embodies the entire upper level
2493  * active set. A parent will mess up some of the init also.
2494  */
2495 static struct clk virt_prcm_set = {
2496         .name           = "virt_prcm_set",
2497         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2498                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2499         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2500         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2501         .set_rate       = &omap2_select_table_rate,
2502         .round_rate     = &omap2_round_to_table_rate,
2503 };
2504
2505 static struct clk *onchip_24xx_clks[] __initdata = {
2506         /* external root sources */
2507         &func_32k_ck,
2508         &osc_ck,
2509         &sys_ck,
2510         &alt_ck,
2511         /* internal analog sources */
2512         &dpll_ck,
2513         &apll96_ck,
2514         &apll54_ck,
2515         /* internal prcm root sources */
2516         &func_54m_ck,
2517         &core_ck,
2518         &func_96m_ck,
2519         &func_48m_ck,
2520         &func_12m_ck,
2521         &wdt1_osc_ck,
2522         &sys_clkout_src,
2523         &sys_clkout,
2524         &sys_clkout2_src,
2525         &sys_clkout2,
2526         &emul_ck,
2527         /* mpu domain clocks */
2528         &mpu_ck,
2529         /* dsp domain clocks */
2530         &dsp_fck,
2531         &dsp_irate_ick,
2532         &dsp_ick,               /* 242x */
2533         &iva2_1_ick,            /* 243x */
2534         &iva1_ifck,             /* 242x */
2535         &iva1_mpu_int_ifck,     /* 242x */
2536         /* GFX domain clocks */
2537         &gfx_3d_fck,
2538         &gfx_2d_fck,
2539         &gfx_ick,
2540         /* Modem domain clocks */
2541         &mdm_ick,
2542         &mdm_osc_ck,
2543         /* DSS domain clocks */
2544         &dss_ick,
2545         &dss1_fck,
2546         &dss2_fck,
2547         &dss_54m_fck,
2548         /* L3 domain clocks */
2549         &core_l3_ck,
2550         &ssi_ssr_sst_fck,
2551         &usb_l4_ick,
2552         /* L4 domain clocks */
2553         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2554         &ssi_l4_ick,
2555         /* virtual meta-group clock */
2556         &virt_prcm_set,
2557         /* general l4 interface ck, multi-parent functional clk */
2558         &gpt1_ick,
2559         &gpt1_fck,
2560         &gpt2_ick,
2561         &gpt2_fck,
2562         &gpt3_ick,
2563         &gpt3_fck,
2564         &gpt4_ick,
2565         &gpt4_fck,
2566         &gpt5_ick,
2567         &gpt5_fck,
2568         &gpt6_ick,
2569         &gpt6_fck,
2570         &gpt7_ick,
2571         &gpt7_fck,
2572         &gpt8_ick,
2573         &gpt8_fck,
2574         &gpt9_ick,
2575         &gpt9_fck,
2576         &gpt10_ick,
2577         &gpt10_fck,
2578         &gpt11_ick,
2579         &gpt11_fck,
2580         &gpt12_ick,
2581         &gpt12_fck,
2582         &mcbsp1_ick,
2583         &mcbsp1_fck,
2584         &mcbsp2_ick,
2585         &mcbsp2_fck,
2586         &mcbsp3_ick,
2587         &mcbsp3_fck,
2588         &mcbsp4_ick,
2589         &mcbsp4_fck,
2590         &mcbsp5_ick,
2591         &mcbsp5_fck,
2592         &mcspi1_ick,
2593         &mcspi1_fck,
2594         &mcspi2_ick,
2595         &mcspi2_fck,
2596         &mcspi3_ick,
2597         &mcspi3_fck,
2598         &uart1_ick,
2599         &uart1_fck,
2600         &uart2_ick,
2601         &uart2_fck,
2602         &uart3_ick,
2603         &uart3_fck,
2604         &gpios_ick,
2605         &gpios_fck,
2606         &mpu_wdt_ick,
2607         &mpu_wdt_fck,
2608         &sync_32k_ick,
2609         &wdt1_ick,
2610         &omapctrl_ick,
2611         &icr_ick,
2612         &cam_fck,
2613         &cam_ick,
2614         &mailboxes_ick,
2615         &wdt4_ick,
2616         &wdt4_fck,
2617         &wdt3_ick,
2618         &wdt3_fck,
2619         &mspro_ick,
2620         &mspro_fck,
2621         &mmc_ick,
2622         &mmc_fck,
2623         &fac_ick,
2624         &fac_fck,
2625         &eac_ick,
2626         &eac_fck,
2627         &hdq_ick,
2628         &hdq_fck,
2629         &i2c1_ick,
2630         &i2c1_fck,
2631         &i2chs1_fck,
2632         &i2c2_ick,
2633         &i2c2_fck,
2634         &i2chs2_fck,
2635         &gpmc_fck,
2636         &sdma_fck,
2637         &sdma_ick,
2638         &vlynq_ick,
2639         &vlynq_fck,
2640         &sdrc_ick,
2641         &des_ick,
2642         &sha_ick,
2643         &rng_ick,
2644         &aes_ick,
2645         &pka_ick,
2646         &usb_fck,
2647         &usbhs_ick,
2648         &mmchs1_ick,
2649         &mmchs1_fck,
2650         &mmchs2_ick,
2651         &mmchs2_fck,
2652         &gpio5_ick,
2653         &gpio5_fck,
2654         &mdm_intc_ick,
2655         &mmchsdb1_fck,
2656         &mmchsdb2_fck,
2657 };
2658
2659 #endif
2660