arch/arm/mach-omap2/clkt34xx_dpll3m2.c

   1 /*
   2  * OMAP34xx M2 divider clock code
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Jouni Högander
   9  *
  10  * Parts of this code are based on code written by
  11  * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17 #undef DEBUG
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/clk.h>
  22 #include <linux/io.h>
  23
  24 #include <plat/clock.h>
  25 #include <plat/sram.h>
  26 #include <plat/sdrc.h>
  27
  28 #include "clock.h"
  29 #include "clock3xxx.h"
  30 #include "clock34xx.h"
  31 #include "sdrc.h"
  32
  33 #define CYCLES_PER_MHZ                  1000000
  34
  35 /*
  36  * CORE DPLL (DPLL3) M2 divider rate programming functions
  37  *
  38  * These call into SRAM code to do the actual CM writes, since the SDRAM
  39  * is clocked from DPLL3.
  40  */
  41
  42 /**
  43  * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
  44  * @clk: struct clk * of DPLL to set
  45  * @rate: rounded target rate
  46  *
  47  * Program the DPLL M2 divider with the rounded target rate.  Returns
  48  * -EINVAL upon error, or 0 upon success.
  49  */
  50 int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
  51 {
  52         u32 new_div = 0;
  53         u32 unlock_dll = 0;
  54         u32 c;
  55         unsigned long validrate, sdrcrate, _mpurate;
  56         struct omap_sdrc_params *sdrc_cs0;
  57         struct omap_sdrc_params *sdrc_cs1;
  58         u32 cm_clksel1_pll;
  59         struct dpll_data *dd;
  60         int ret;
  61
  62         if (!clk || !rate)
  63                 return -EINVAL;
  64
  65         if (!clk->parent || !clk->parent->dpll_data)
  66                 return -EINVAL;
  67
  68         dd = clk->parent->dpll_data;
  69         cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
  70
  71         validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
  72         if (validrate == rate) {
  73                 cm_clksel1_pll &= ~clk->clksel_mask;
  74                 cm_clksel1_pll |= new_div << __ffs(clk->clksel_mask);
  75         } else {
  76                 rate = omap2_dpll_round_rate(clk->parent, rate);
  77                 if (rate == ~0)
  78                         return -EINVAL;
  79
  80                 cm_clksel1_pll &= ~(dd->mult_mask | dd->div1_mask | clk->clksel_mask);
  81                 cm_clksel1_pll |= dd->last_rounded_m << __ffs(dd->mult_mask);
  82                 cm_clksel1_pll |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
  83                 cm_clksel1_pll |= 1 << __ffs(clk->clksel_mask);
  84
  85                 validrate = rate;
  86         }
  87
  88 #if 0
  89         sdrcrate = sdrc_ick_p->rate;
  90         if (rate > clk->rate)
  91                 sdrcrate <<= ((rate / clk->rate) >> 1);
  92         else
  93                 sdrcrate >>= ((clk->rate / rate) >> 1);
  94 #else
  95         /* HACK! */
  96         sdrcrate = rate / 2;
  97 #endif
  98
  99         ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
 100         if (ret)
 101                 return -EINVAL;
 102
 103         if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
 104                 pr_debug("clock: will unlock SDRC DLL\n");
 105                 unlock_dll = 1;
 106         }
 107
 108         /*
 109          * XXX This only needs to be done when the CPU frequency changes
 110          */
 111         _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
 112         c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
 113         c += 1;  /* for safety */
 114         c *= SDRC_MPURATE_LOOPS;
 115         c >>= SDRC_MPURATE_SCALE;
 116         if (c == 0)
 117                 c = 1;
 118
 119         pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
 120                  validrate);
 121         pr_debug("clock: SDRC CS0 timing params used:"
 122                  " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
 123                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
 124                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
 125         if (sdrc_cs1)
 126                 pr_debug("clock: SDRC CS1 timing params used: "
 127                  " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
 128                  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
 129                  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
 130
 131         if (sdrc_cs1)
 132                 omap3_configure_core_dpll(
 133                                   cm_clksel1_pll, unlock_dll, c, rate > clk->rate,
 134                                   sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
 135                                   sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
 136                                   sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
 137                                   sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
 138         else
 139                 omap3_configure_core_dpll(
 140                                   cm_clksel1_pll, unlock_dll, c, rate > clk->rate,
 141                                   sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
 142                                   sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
 143                                   0, 0, 0, 0);
 144         clk->rate = rate;
 145
 146         /* HACK */
 147         clk->parent->rate = clk->parent->recalc(clk->parent);
 148
 149         return 0;
 150 }
 151