arch/arm/mach-omap1/clock_data.c

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock_data.c
   3  *
   4  *  Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * To do:
  13  * - Clocks that are only available on some chips should be marked with the
  14  *   chips that they are present on.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/clk.h>
  19 #include <linux/cpufreq.h>
  20 #include <linux/delay.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/mach-types.h>  /* for machine_is_* */
  24
  25 #include <plat/clock.h>
  26 #include <plat/cpu.h>
  27 #include <plat/clkdev_omap.h>
  28 #include <plat/usb.h>   /* for OTG_BASE */
  29
  30 #include "clock.h"
  31
  32 /* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
  33 #define IDL_CLKOUT_ARM_SHIFT                    12
  34 #define IDLTIM_ARM_SHIFT                        9
  35 #define IDLAPI_ARM_SHIFT                        8
  36 #define IDLIF_ARM_SHIFT                         6
  37 #define IDLLB_ARM_SHIFT                         4       /* undocumented? */
  38 #define OMAP1510_IDLLCD_ARM_SHIFT               3       /* undocumented? */
  39 #define IDLPER_ARM_SHIFT                        2
  40 #define IDLXORP_ARM_SHIFT                       1
  41 #define IDLWDT_ARM_SHIFT                        0
  42
  43 /* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
  44 #define CONF_MOD_UART3_CLK_MODE_R               31
  45 #define CONF_MOD_UART2_CLK_MODE_R               30
  46 #define CONF_MOD_UART1_CLK_MODE_R               29
  47 #define CONF_MOD_MMC_SD_CLK_REQ_R               23
  48 #define CONF_MOD_MCBSP3_AUXON                   20
  49
  50 /* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
  51 #define CONF_MOD_SOSSI_CLK_EN_R                 16
  52
  53 /* Some OTG_SYSCON_2-specific bit fields */
  54 #define OTG_SYSCON_2_UHOST_EN_SHIFT             8
  55
  56 /* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
  57 #define SOFT_MMC2_DPLL_REQ_SHIFT        13
  58 #define SOFT_MMC_DPLL_REQ_SHIFT         12
  59 #define SOFT_UART3_DPLL_REQ_SHIFT       11
  60 #define SOFT_UART2_DPLL_REQ_SHIFT       10
  61 #define SOFT_UART1_DPLL_REQ_SHIFT       9
  62 #define SOFT_USB_OTG_DPLL_REQ_SHIFT     8
  63 #define SOFT_CAM_DPLL_REQ_SHIFT         7
  64 #define SOFT_COM_MCKO_REQ_SHIFT         6
  65 #define SOFT_PERIPH_REQ_SHIFT           5       /* sys_ck gate for UART2 ? */
  66 #define USB_REQ_EN_SHIFT                4
  67 #define SOFT_USB_REQ_SHIFT              3       /* sys_ck gate for USB host? */
  68 #define SOFT_SDW_REQ_SHIFT              2       /* sys_ck gate for Bluetooth? */
  69 #define SOFT_COM_REQ_SHIFT              1       /* sys_ck gate for com proc? */
  70 #define SOFT_DPLL_REQ_SHIFT             0
  71
  72 /*
  73  * Omap1 clocks
  74  */
  75
  76 static struct clk ck_ref = {
  77         .name           = "ck_ref",
  78         .ops            = &clkops_null,
  79         .rate           = 12000000,
  80 };
  81
  82 static struct clk ck_dpll1 = {
  83         .name           = "ck_dpll1",
  84         .ops            = &clkops_null,
  85         .parent         = &ck_ref,
  86 };
  87
  88 /*
  89  * FIXME: This clock seems to be necessary but no-one has asked for its
  90  * activation.  [ FIX: SoSSI, SSR ]
  91  */
  92 static struct arm_idlect1_clk ck_dpll1out = {
  93         .clk = {
  94                 .name           = "ck_dpll1out",
  95                 .ops            = &clkops_generic,
  96                 .parent         = &ck_dpll1,
  97                 .flags          = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
  98                                   ENABLE_ON_INIT,
  99                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 100                 .enable_bit     = EN_CKOUT_ARM,
 101                 .recalc         = &followparent_recalc,
 102         },
 103         .idlect_shift   = IDL_CLKOUT_ARM_SHIFT,
 104 };
 105
 106 static struct clk sossi_ck = {
 107         .name           = "ck_sossi",
 108         .ops            = &clkops_generic,
 109         .parent         = &ck_dpll1out.clk,
 110         .flags          = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
 111         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
 112         .enable_bit     = CONF_MOD_SOSSI_CLK_EN_R,
 113         .recalc         = &omap1_sossi_recalc,
 114         .set_rate       = &omap1_set_sossi_rate,
 115 };
 116
 117 static struct clk arm_ck = {
 118         .name           = "arm_ck",
 119         .ops            = &clkops_null,
 120         .parent         = &ck_dpll1,
 121         .rate_offset    = CKCTL_ARMDIV_OFFSET,
 122         .recalc         = &omap1_ckctl_recalc,
 123         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 124         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 125 };
 126
 127 static struct arm_idlect1_clk armper_ck = {
 128         .clk = {
 129                 .name           = "armper_ck",
 130                 .ops            = &clkops_generic,
 131                 .parent         = &ck_dpll1,
 132                 .flags          = CLOCK_IDLE_CONTROL,
 133                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 134                 .enable_bit     = EN_PERCK,
 135                 .rate_offset    = CKCTL_PERDIV_OFFSET,
 136                 .recalc         = &omap1_ckctl_recalc,
 137                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 138                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 139         },
 140         .idlect_shift   = IDLPER_ARM_SHIFT,
 141 };
 142
 143 /*
 144  * FIXME: This clock seems to be necessary but no-one has asked for its
 145  * activation.  [ GPIO code for 1510 ]
 146  */
 147 static struct clk arm_gpio_ck = {
 148         .name           = "ick",
 149         .ops            = &clkops_generic,
 150         .parent         = &ck_dpll1,
 151         .flags          = ENABLE_ON_INIT,
 152         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 153         .enable_bit     = EN_GPIOCK,
 154         .recalc         = &followparent_recalc,
 155 };
 156
 157 static struct arm_idlect1_clk armxor_ck = {
 158         .clk = {
 159                 .name           = "armxor_ck",
 160                 .ops            = &clkops_generic,
 161                 .parent         = &ck_ref,
 162                 .flags          = CLOCK_IDLE_CONTROL,
 163                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 164                 .enable_bit     = EN_XORPCK,
 165                 .recalc         = &followparent_recalc,
 166         },
 167         .idlect_shift   = IDLXORP_ARM_SHIFT,
 168 };
 169
 170 static struct arm_idlect1_clk armtim_ck = {
 171         .clk = {
 172                 .name           = "armtim_ck",
 173                 .ops            = &clkops_generic,
 174                 .parent         = &ck_ref,
 175                 .flags          = CLOCK_IDLE_CONTROL,
 176                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 177                 .enable_bit     = EN_TIMCK,
 178                 .recalc         = &followparent_recalc,
 179         },
 180         .idlect_shift   = IDLTIM_ARM_SHIFT,
 181 };
 182
 183 static struct arm_idlect1_clk armwdt_ck = {
 184         .clk = {
 185                 .name           = "armwdt_ck",
 186                 .ops            = &clkops_generic,
 187                 .parent         = &ck_ref,
 188                 .flags          = CLOCK_IDLE_CONTROL,
 189                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 190                 .enable_bit     = EN_WDTCK,
 191                 .fixed_div      = 14,
 192                 .recalc         = &omap_fixed_divisor_recalc,
 193         },
 194         .idlect_shift   = IDLWDT_ARM_SHIFT,
 195 };
 196
 197 static struct clk arminth_ck16xx = {
 198         .name           = "arminth_ck",
 199         .ops            = &clkops_null,
 200         .parent         = &arm_ck,
 201         .recalc         = &followparent_recalc,
 202         /* Note: On 16xx the frequency can be divided by 2 by programming
 203          * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
 204          *
 205          * 1510 version is in TC clocks.
 206          */
 207 };
 208
 209 static struct clk dsp_ck = {
 210         .name           = "dsp_ck",
 211         .ops            = &clkops_generic,
 212         .parent         = &ck_dpll1,
 213         .enable_reg     = OMAP1_IO_ADDRESS(ARM_CKCTL),
 214         .enable_bit     = EN_DSPCK,
 215         .rate_offset    = CKCTL_DSPDIV_OFFSET,
 216         .recalc         = &omap1_ckctl_recalc,
 217         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 218         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 219 };
 220
 221 static struct clk dspmmu_ck = {
 222         .name           = "dspmmu_ck",
 223         .ops            = &clkops_null,
 224         .parent         = &ck_dpll1,
 225         .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
 226         .recalc         = &omap1_ckctl_recalc,
 227         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 228         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 229 };
 230
 231 static struct clk dspper_ck = {
 232         .name           = "dspper_ck",
 233         .ops            = &clkops_dspck,
 234         .parent         = &ck_dpll1,
 235         .enable_reg     = DSP_IDLECT2,
 236         .enable_bit     = EN_PERCK,
 237         .rate_offset    = CKCTL_PERDIV_OFFSET,
 238         .recalc         = &omap1_ckctl_recalc_dsp_domain,
 239         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 240         .set_rate       = &omap1_clk_set_rate_dsp_domain,
 241 };
 242
 243 static struct clk dspxor_ck = {
 244         .name           = "dspxor_ck",
 245         .ops            = &clkops_dspck,
 246         .parent         = &ck_ref,
 247         .enable_reg     = DSP_IDLECT2,
 248         .enable_bit     = EN_XORPCK,
 249         .recalc         = &followparent_recalc,
 250 };
 251
 252 static struct clk dsptim_ck = {
 253         .name           = "dsptim_ck",
 254         .ops            = &clkops_dspck,
 255         .parent         = &ck_ref,
 256         .enable_reg     = DSP_IDLECT2,
 257         .enable_bit     = EN_DSPTIMCK,
 258         .recalc         = &followparent_recalc,
 259 };
 260
 261 static struct arm_idlect1_clk tc_ck = {
 262         .clk = {
 263                 .name           = "tc_ck",
 264                 .ops            = &clkops_null,
 265                 .parent         = &ck_dpll1,
 266                 .flags          = CLOCK_IDLE_CONTROL,
 267                 .rate_offset    = CKCTL_TCDIV_OFFSET,
 268                 .recalc         = &omap1_ckctl_recalc,
 269                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 270                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 271         },
 272         .idlect_shift   = IDLIF_ARM_SHIFT,
 273 };
 274
 275 static struct clk arminth_ck1510 = {
 276         .name           = "arminth_ck",
 277         .ops            = &clkops_null,
 278         .parent         = &tc_ck.clk,
 279         .recalc         = &followparent_recalc,
 280         /* Note: On 1510 the frequency follows TC_CK
 281          *
 282          * 16xx version is in MPU clocks.
 283          */
 284 };
 285
 286 static struct clk tipb_ck = {
 287         /* No-idle controlled by "tc_ck" */
 288         .name           = "tipb_ck",
 289         .ops            = &clkops_null,
 290         .parent         = &tc_ck.clk,
 291         .recalc         = &followparent_recalc,
 292 };
 293
 294 static struct clk l3_ocpi_ck = {
 295         /* No-idle controlled by "tc_ck" */
 296         .name           = "l3_ocpi_ck",
 297         .ops            = &clkops_generic,
 298         .parent         = &tc_ck.clk,
 299         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 300         .enable_bit     = EN_OCPI_CK,
 301         .recalc         = &followparent_recalc,
 302 };
 303
 304 static struct clk tc1_ck = {
 305         .name           = "tc1_ck",
 306         .ops            = &clkops_generic,
 307         .parent         = &tc_ck.clk,
 308         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 309         .enable_bit     = EN_TC1_CK,
 310         .recalc         = &followparent_recalc,
 311 };
 312
 313 /*
 314  * FIXME: This clock seems to be necessary but no-one has asked for its
 315  * activation.  [ pm.c (SRAM), CCP, Camera ]
 316  */
 317 static struct clk tc2_ck = {
 318         .name           = "tc2_ck",
 319         .ops            = &clkops_generic,
 320         .parent         = &tc_ck.clk,
 321         .flags          = ENABLE_ON_INIT,
 322         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 323         .enable_bit     = EN_TC2_CK,
 324         .recalc         = &followparent_recalc,
 325 };
 326
 327 static struct clk dma_ck = {
 328         /* No-idle controlled by "tc_ck" */
 329         .name           = "dma_ck",
 330         .ops            = &clkops_null,
 331         .parent         = &tc_ck.clk,
 332         .recalc         = &followparent_recalc,
 333 };
 334
 335 static struct clk dma_lcdfree_ck = {
 336         .name           = "dma_lcdfree_ck",
 337         .ops            = &clkops_null,
 338         .parent         = &tc_ck.clk,
 339         .recalc         = &followparent_recalc,
 340 };
 341
 342 static struct arm_idlect1_clk api_ck = {
 343         .clk = {
 344                 .name           = "api_ck",
 345                 .ops            = &clkops_generic,
 346                 .parent         = &tc_ck.clk,
 347                 .flags          = CLOCK_IDLE_CONTROL,
 348                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 349                 .enable_bit     = EN_APICK,
 350                 .recalc         = &followparent_recalc,
 351         },
 352         .idlect_shift   = IDLAPI_ARM_SHIFT,
 353 };
 354
 355 static struct arm_idlect1_clk lb_ck = {
 356         .clk = {
 357                 .name           = "lb_ck",
 358                 .ops            = &clkops_generic,
 359                 .parent         = &tc_ck.clk,
 360                 .flags          = CLOCK_IDLE_CONTROL,
 361                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 362                 .enable_bit     = EN_LBCK,
 363                 .recalc         = &followparent_recalc,
 364         },
 365         .idlect_shift   = IDLLB_ARM_SHIFT,
 366 };
 367
 368 static struct clk rhea1_ck = {
 369         .name           = "rhea1_ck",
 370         .ops            = &clkops_null,
 371         .parent         = &tc_ck.clk,
 372         .recalc         = &followparent_recalc,
 373 };
 374
 375 static struct clk rhea2_ck = {
 376         .name           = "rhea2_ck",
 377         .ops            = &clkops_null,
 378         .parent         = &tc_ck.clk,
 379         .recalc         = &followparent_recalc,
 380 };
 381
 382 static struct clk lcd_ck_16xx = {
 383         .name           = "lcd_ck",
 384         .ops            = &clkops_generic,
 385         .parent         = &ck_dpll1,
 386         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 387         .enable_bit     = EN_LCDCK,
 388         .rate_offset    = CKCTL_LCDDIV_OFFSET,
 389         .recalc         = &omap1_ckctl_recalc,
 390         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 391         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 392 };
 393
 394 static struct arm_idlect1_clk lcd_ck_1510 = {
 395         .clk = {
 396                 .name           = "lcd_ck",
 397                 .ops            = &clkops_generic,
 398                 .parent         = &ck_dpll1,
 399                 .flags          = CLOCK_IDLE_CONTROL,
 400                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 401                 .enable_bit     = EN_LCDCK,
 402                 .rate_offset    = CKCTL_LCDDIV_OFFSET,
 403                 .recalc         = &omap1_ckctl_recalc,
 404                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 405                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 406         },
 407         .idlect_shift   = OMAP1510_IDLLCD_ARM_SHIFT,
 408 };
 409
 410 /*
 411  * XXX The enable_bit here is misused - it simply switches between 12MHz
 412  * and 48MHz.  Reimplement with clksel.
 413  *
 414  * XXX does this need SYSC register handling?
 415  */
 416 static struct clk uart1_1510 = {
 417         .name           = "uart1_ck",
 418         .ops            = &clkops_null,
 419         /* Direct from ULPD, no real parent */
 420         .parent         = &armper_ck.clk,
 421         .rate           = 12000000,
 422         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 423         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 424         .enable_bit     = CONF_MOD_UART1_CLK_MODE_R,
 425         .set_rate       = &omap1_set_uart_rate,
 426         .recalc         = &omap1_uart_recalc,
 427 };
 428
 429 /*
 430  * XXX The enable_bit here is misused - it simply switches between 12MHz
 431  * and 48MHz.  Reimplement with clksel.
 432  *
 433  * XXX SYSC register handling does not belong in the clock framework
 434  */
 435 static struct uart_clk uart1_16xx = {
 436         .clk    = {
 437                 .name           = "uart1_ck",
 438                 .ops            = &clkops_uart_16xx,
 439                 /* Direct from ULPD, no real parent */
 440                 .parent         = &armper_ck.clk,
 441                 .rate           = 48000000,
 442                 .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 443                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 444                 .enable_bit     = CONF_MOD_UART1_CLK_MODE_R,
 445         },
 446         .sysc_addr      = 0xfffb0054,
 447 };
 448
 449 /*
 450  * XXX The enable_bit here is misused - it simply switches between 12MHz
 451  * and 48MHz.  Reimplement with clksel.
 452  *
 453  * XXX does this need SYSC register handling?
 454  */
 455 static struct clk uart2_ck = {
 456         .name           = "uart2_ck",
 457         .ops            = &clkops_null,
 458         /* Direct from ULPD, no real parent */
 459         .parent         = &armper_ck.clk,
 460         .rate           = 12000000,
 461         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 462         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 463         .enable_bit     = CONF_MOD_UART2_CLK_MODE_R,
 464         .set_rate       = &omap1_set_uart_rate,
 465         .recalc         = &omap1_uart_recalc,
 466 };
 467
 468 /*
 469  * XXX The enable_bit here is misused - it simply switches between 12MHz
 470  * and 48MHz.  Reimplement with clksel.
 471  *
 472  * XXX does this need SYSC register handling?
 473  */
 474 static struct clk uart3_1510 = {
 475         .name           = "uart3_ck",
 476         .ops            = &clkops_null,
 477         /* Direct from ULPD, no real parent */
 478         .parent         = &armper_ck.clk,
 479         .rate           = 12000000,
 480         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 481         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 482         .enable_bit     = CONF_MOD_UART3_CLK_MODE_R,
 483         .set_rate       = &omap1_set_uart_rate,
 484         .recalc         = &omap1_uart_recalc,
 485 };
 486
 487 /*
 488  * XXX The enable_bit here is misused - it simply switches between 12MHz
 489  * and 48MHz.  Reimplement with clksel.
 490  *
 491  * XXX SYSC register handling does not belong in the clock framework
 492  */
 493 static struct uart_clk uart3_16xx = {
 494         .clk    = {
 495                 .name           = "uart3_ck",
 496                 .ops            = &clkops_uart_16xx,
 497                 /* Direct from ULPD, no real parent */
 498                 .parent         = &armper_ck.clk,
 499                 .rate           = 48000000,
 500                 .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 501                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 502                 .enable_bit     = CONF_MOD_UART3_CLK_MODE_R,
 503         },
 504         .sysc_addr      = 0xfffb9854,
 505 };
 506
 507 static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
 508         .name           = "usb_clko",
 509         .ops            = &clkops_generic,
 510         /* Direct from ULPD, no parent */
 511         .rate           = 6000000,
 512         .flags          = ENABLE_REG_32BIT,
 513         .enable_reg     = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
 514         .enable_bit     = USB_MCLK_EN_BIT,
 515 };
 516
 517 static struct clk usb_hhc_ck1510 = {
 518         .name           = "usb_hhc_ck",
 519         .ops            = &clkops_generic,
 520         /* Direct from ULPD, no parent */
 521         .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
 522         .flags          = ENABLE_REG_32BIT,
 523         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 524         .enable_bit     = USB_HOST_HHC_UHOST_EN,
 525 };
 526
 527 static struct clk usb_hhc_ck16xx = {
 528         .name           = "usb_hhc_ck",
 529         .ops            = &clkops_generic,
 530         /* Direct from ULPD, no parent */
 531         .rate           = 48000000,
 532         /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
 533         .flags          = ENABLE_REG_32BIT,
 534         .enable_reg     = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
 535         .enable_bit     = OTG_SYSCON_2_UHOST_EN_SHIFT
 536 };
 537
 538 static struct clk usb_dc_ck = {
 539         .name           = "usb_dc_ck",
 540         .ops            = &clkops_generic,
 541         /* Direct from ULPD, no parent */
 542         .rate           = 48000000,
 543         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 544         .enable_bit     = USB_REQ_EN_SHIFT,
 545 };
 546
 547 static struct clk usb_dc_ck7xx = {
 548         .name           = "usb_dc_ck",
 549         .ops            = &clkops_generic,
 550         /* Direct from ULPD, no parent */
 551         .rate           = 48000000,
 552         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 553         .enable_bit     = SOFT_USB_OTG_DPLL_REQ_SHIFT,
 554 };
 555
 556 static struct clk uart1_7xx = {
 557         .name           = "uart1_ck",
 558         .ops            = &clkops_generic,
 559         /* Direct from ULPD, no parent */
 560         .rate           = 12000000,
 561         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 562         .enable_bit     = 9,
 563 };
 564
 565 static struct clk uart2_7xx = {
 566         .name           = "uart2_ck",
 567         .ops            = &clkops_generic,
 568         /* Direct from ULPD, no parent */
 569         .rate           = 12000000,
 570         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 571         .enable_bit     = 11,
 572 };
 573
 574 static struct clk mclk_1510 = {
 575         .name           = "mclk",
 576         .ops            = &clkops_generic,
 577         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 578         .rate           = 12000000,
 579         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 580         .enable_bit     = SOFT_COM_MCKO_REQ_SHIFT,
 581 };
 582
 583 static struct clk mclk_16xx = {
 584         .name           = "mclk",
 585         .ops            = &clkops_generic,
 586         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 587         .enable_reg     = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
 588         .enable_bit     = COM_ULPD_PLL_CLK_REQ,
 589         .set_rate       = &omap1_set_ext_clk_rate,
 590         .round_rate     = &omap1_round_ext_clk_rate,
 591         .init           = &omap1_init_ext_clk,
 592 };
 593
 594 static struct clk bclk_1510 = {
 595         .name           = "bclk",
 596         .ops            = &clkops_generic,
 597         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 598         .rate           = 12000000,
 599 };
 600
 601 static struct clk bclk_16xx = {
 602         .name           = "bclk",
 603         .ops            = &clkops_generic,
 604         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 605         .enable_reg     = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
 606         .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
 607         .set_rate       = &omap1_set_ext_clk_rate,
 608         .round_rate     = &omap1_round_ext_clk_rate,
 609         .init           = &omap1_init_ext_clk,
 610 };
 611
 612 static struct clk mmc1_ck = {
 613         .name           = "mmc1_ck",
 614         .ops            = &clkops_generic,
 615         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 616         .parent         = &armper_ck.clk,
 617         .rate           = 48000000,
 618         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 619         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 620         .enable_bit     = CONF_MOD_MMC_SD_CLK_REQ_R,
 621 };
 622
 623 /*
 624  * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
 625  * CONF_MOD_MCBSP3_AUXON ??
 626  */
 627 static struct clk mmc2_ck = {
 628         .name           = "mmc2_ck",
 629         .ops            = &clkops_generic,
 630         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 631         .parent         = &armper_ck.clk,
 632         .rate           = 48000000,
 633         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 634         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 635         .enable_bit     = 20,
 636 };
 637
 638 static struct clk mmc3_ck = {
 639         .name           = "mmc3_ck",
 640         .ops            = &clkops_generic,
 641         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 642         .parent         = &armper_ck.clk,
 643         .rate           = 48000000,
 644         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 645         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 646         .enable_bit     = SOFT_MMC_DPLL_REQ_SHIFT,
 647 };
 648
 649 static struct clk virtual_ck_mpu = {
 650         .name           = "mpu",
 651         .ops            = &clkops_null,
 652         .parent         = &arm_ck, /* Is smarter alias for */
 653         .recalc         = &followparent_recalc,
 654         .set_rate       = &omap1_select_table_rate,
 655         .round_rate     = &omap1_round_to_table_rate,
 656 };
 657
 658 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
 659 remains active during MPU idle whenever this is enabled */
 660 static struct clk i2c_fck = {
 661         .name           = "i2c_fck",
 662         .ops            = &clkops_null,
 663         .flags          = CLOCK_NO_IDLE_PARENT,
 664         .parent         = &armxor_ck.clk,
 665         .recalc         = &followparent_recalc,
 666 };
 667
 668 static struct clk i2c_ick = {
 669         .name           = "i2c_ick",
 670         .ops            = &clkops_null,
 671         .flags          = CLOCK_NO_IDLE_PARENT,
 672         .parent         = &armper_ck.clk,
 673         .recalc         = &followparent_recalc,
 674 };
 675
 676 /*
 677  * clkdev integration
 678  */
 679
 680 static struct omap_clk omap_clks[] = {
 681         /* non-ULPD clocks */
 682         CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310 | CK_7XX),
 683         CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310 | CK_7XX),
 684         /* CK_GEN1 clocks */
 685         CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
 686         CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
 687         CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
 688         CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 689         CLK("omap_gpio.0", "ick",       &arm_gpio_ck,   CK_1510 | CK_310),
 690         CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
 691         CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
 692         CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
 693         CLK("omap_wdt", "ick",          &armper_ck.clk, CK_16XX),
 694         CLK("omap_wdt", "ick",          &dummy_ck,      CK_1510 | CK_310),
 695         CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
 696         CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
 697         /* CK_GEN2 clocks */
 698         CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
 699         CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
 700         CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
 701         CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 702         CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
 703         /* CK_GEN3 clocks */
 704         CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_7XX),
 705         CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
 706         CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX | CK_7XX),
 707         CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
 708         CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
 709         CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
 710         CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
 711         CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310 | CK_7XX),
 712         CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
 713         CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
 714         CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
 715         CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_7XX),
 716         CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
 717         /* ULPD clocks */
 718         CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
 719         CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
 720         CLK(NULL,       "uart1_ck",     &uart1_7xx,     CK_7XX),
 721         CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
 722         CLK(NULL,       "uart2_ck",     &uart2_7xx,     CK_7XX),
 723         CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
 724         CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
 725         CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
 726         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
 727         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
 728         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
 729         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck7xx,  CK_7XX),
 730         CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
 731         CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
 732         CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
 733         CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
 734         CLK("mmci-omap.0", "fck",       &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
 735         CLK("mmci-omap.0", "fck",       &mmc3_ck,       CK_7XX),
 736         CLK("mmci-omap.0", "ick",       &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
 737         CLK("mmci-omap.1", "fck",       &mmc2_ck,       CK_16XX),
 738         CLK("mmci-omap.1", "ick",       &armper_ck.clk, CK_16XX),
 739         /* Virtual clocks */
 740         CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
 741         CLK("omap_i2c.1", "fck",        &i2c_fck,       CK_16XX | CK_1510 | CK_310 | CK_7XX),
 742         CLK("omap_i2c.1", "ick",        &i2c_ick,       CK_16XX),
 743         CLK("omap_i2c.1", "ick",        &dummy_ck,      CK_1510 | CK_310 | CK_7XX),
 744         CLK("omap1_spi100k.1", "fck",   &dummy_ck,      CK_7XX),
 745         CLK("omap1_spi100k.1", "ick",   &dummy_ck,      CK_7XX),
 746         CLK("omap1_spi100k.2", "fck",   &dummy_ck,      CK_7XX),
 747         CLK("omap1_spi100k.2", "ick",   &dummy_ck,      CK_7XX),
 748         CLK("omap_uwire", "fck",        &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
 749         CLK("omap-mcbsp.1", "ick",      &dspper_ck,     CK_16XX),
 750         CLK("omap-mcbsp.1", "ick",      &dummy_ck,      CK_1510 | CK_310),
 751         CLK("omap-mcbsp.2", "ick",      &armper_ck.clk, CK_16XX),
 752         CLK("omap-mcbsp.2", "ick",      &dummy_ck,      CK_1510 | CK_310),
 753         CLK("omap-mcbsp.3", "ick",      &dspper_ck,     CK_16XX),
 754         CLK("omap-mcbsp.3", "ick",      &dummy_ck,      CK_1510 | CK_310),
 755         CLK("omap-mcbsp.1", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 756         CLK("omap-mcbsp.2", "fck",      &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 757         CLK("omap-mcbsp.3", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 758 };
 759
 760 /*
 761  * init
 762  */
 763
 764 static struct clk_functions omap1_clk_functions = {
 765         .clk_enable             = omap1_clk_enable,
 766         .clk_disable            = omap1_clk_disable,
 767         .clk_round_rate         = omap1_clk_round_rate,
 768         .clk_set_rate           = omap1_clk_set_rate,
 769         .clk_disable_unused     = omap1_clk_disable_unused,
 770 };
 771
 772 static void __init omap1_show_rates(void)
 773 {
 774         pr_notice("Clocking rate (xtal/DPLL1/MPU): "
 775                         "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
 776                 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
 777                 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
 778                 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 779 }
 780
 781 int __init omap1_clk_init(void)
 782 {
 783         struct omap_clk *c;
 784         const struct omap_clock_config *info;
 785         int crystal_type = 0; /* Default 12 MHz */
 786         u32 reg, cpu_mask;
 787
 788 #ifdef CONFIG_DEBUG_LL
 789         /*
 790          * Resets some clocks that may be left on from bootloader,
 791          * but leaves serial clocks on.
 792          */
 793         omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
 794 #endif
 795
 796         /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
 797         reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
 798         omap_writew(reg, SOFT_REQ_REG);
 799         if (!cpu_is_omap15xx())
 800                 omap_writew(0, SOFT_REQ_REG2);
 801
 802         clk_init(&omap1_clk_functions);
 803
 804         /* By default all idlect1 clocks are allowed to idle */
 805         arm_idlect1_mask = ~0;
 806
 807         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 808                 clk_preinit(c->lk.clk);
 809
 810         cpu_mask = 0;
 811         if (cpu_is_omap16xx())
 812                 cpu_mask |= CK_16XX;
 813         if (cpu_is_omap1510())
 814                 cpu_mask |= CK_1510;
 815         if (cpu_is_omap7xx())
 816                 cpu_mask |= CK_7XX;
 817         if (cpu_is_omap310())
 818                 cpu_mask |= CK_310;
 819
 820         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 821                 if (c->cpu & cpu_mask) {
 822                         clkdev_add(&c->lk);
 823                         clk_register(c->lk.clk);
 824                 }
 825
 826         /* Pointers to these clocks are needed by code in clock.c */
 827         api_ck_p = clk_get(NULL, "api_ck");
 828         ck_dpll1_p = clk_get(NULL, "ck_dpll1");
 829         ck_ref_p = clk_get(NULL, "ck_ref");
 830
 831         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
 832         if (info != NULL) {
 833                 if (!cpu_is_omap15xx())
 834                         crystal_type = info->system_clock_type;
 835         }
 836
 837         if (cpu_is_omap7xx())
 838                 ck_ref.rate = 13000000;
 839         if (cpu_is_omap16xx() && crystal_type == 2)
 840                 ck_ref.rate = 19200000;
 841
 842         pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
 843                 "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
 844                 omap_readw(ARM_CKCTL));
 845
 846         /* We want to be in syncronous scalable mode */
 847         omap_writew(0x1000, ARM_SYSST);
 848
 849
 850         /*
 851          * Initially use the values set by bootloader. Determine PLL rate and
 852          * recalculate dependent clocks as if kernel had changed PLL or
 853          * divisors. See also omap1_clk_late_init() that can reprogram dpll1
 854          * after the SRAM is initialized.
 855          */
 856         {
 857                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
 858
 859                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
 860                 if (pll_ctl_val & 0x10) {
 861                         /* PLL enabled, apply multiplier and divisor */
 862                         if (pll_ctl_val & 0xf80)
 863                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
 864                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
 865                 } else {
 866                         /* PLL disabled, apply bypass divisor */
 867                         switch (pll_ctl_val & 0xc) {
 868                         case 0:
 869                                 break;
 870                         case 0x4:
 871                                 ck_dpll1.rate /= 2;
 872                                 break;
 873                         default:
 874                                 ck_dpll1.rate /= 4;
 875                                 break;
 876                         }
 877                 }
 878         }
 879         propagate_rate(&ck_dpll1);
 880         /* Cache rates for clocks connected to ck_ref (not dpll1) */
 881         propagate_rate(&ck_ref);
 882         omap1_show_rates();
 883         if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
 884                 /* Select slicer output as OMAP input clock */
 885                 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
 886                                 OMAP7XX_PCC_UPLD_CTRL);
 887         }
 888
 889         /* Amstrad Delta wants BCLK high when inactive */
 890         if (machine_is_ams_delta())
 891                 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
 892                                 (1 << SDW_MCLK_INV_BIT),
 893                                 ULPD_CLOCK_CTRL);
 894
 895         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
 896         /* (on 730, bit 13 must not be cleared) */
 897         if (cpu_is_omap7xx())
 898                 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
 899         else
 900                 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
 901
 902         /* Put DSP/MPUI into reset until needed */
 903         omap_writew(0, ARM_RSTCT1);
 904         omap_writew(1, ARM_RSTCT2);
 905         omap_writew(0x400, ARM_IDLECT1);
 906
 907         /*
 908          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
 909          * of the ARM_IDLECT2 register must be set to zero. The power-on
 910          * default value of this bit is one.
 911          */
 912         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
 913
 914         /*
 915          * Only enable those clocks we will need, let the drivers
 916          * enable other clocks as necessary
 917          */
 918         clk_enable(&armper_ck.clk);
 919         clk_enable(&armxor_ck.clk);
 920         clk_enable(&armtim_ck.clk); /* This should be done by timer code */
 921
 922         if (cpu_is_omap15xx())
 923                 clk_enable(&arm_gpio_ck);
 924
 925         return 0;
 926 }
 927
 928 #define OMAP1_DPLL1_SANE_VALUE  60000000
 929
 930 void __init omap1_clk_late_init(void)
 931 {
 932         unsigned long rate = ck_dpll1.rate;
 933
 934         if (rate >= OMAP1_DPLL1_SANE_VALUE)
 935                 return;
 936
 937         /* System booting at unusable rate, force reprogramming of DPLL1 */
 938         ck_dpll1_p->rate = 0;
 939
 940         /* Find the highest supported frequency and enable it */
 941         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
 942                 pr_err("System frequencies not set, using default. Check your config.\n");
 943                 omap_writew(0x2290, DPLL_CTL);
 944                 omap_writew(cpu_is_omap7xx() ? 0x2005 : 0x0005, ARM_CKCTL);
 945                 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
 946         }
 947         propagate_rate(&ck_dpll1);
 948         omap1_show_rates();
 949         loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate);
 950 }