arch/arm/mach-omap1/board-fsample.c

   1 /*
   2  * linux/arch/arm/mach-omap1/board-fsample.c
   3  *
   4  * Modified from board-perseus2.c
   5  *
   6  * Original OMAP730 support by Jean Pihet <j-pihet@ti.com>
   7  * Updated for 2.6 by Kevin Hilman <kjh@hilman.org>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/delay.h>
  18 #include <linux/mtd/mtd.h>
  19 #include <linux/mtd/nand.h>
  20 #include <linux/mtd/partitions.h>
  21 #include <linux/mtd/physmap.h>
  22 #include <linux/input.h>
  23 #include <linux/smc91x.h>
  24
  25 #include <mach/hardware.h>
  26 #include <asm/mach-types.h>
  27 #include <asm/mach/arch.h>
  28 #include <asm/mach/map.h>
  29
  30 #include <plat/tc.h>
  31 #include <mach/gpio.h>
  32 #include <plat/mux.h>
  33 #include <plat/flash.h>
  34 #include <plat/fpga.h>
  35 #include <plat/keypad.h>
  36 #include <plat/common.h>
  37 #include <plat/board.h>
  38
  39 /* fsample is pretty close to p2-sample */
  40
  41 #define fsample_cpld_read(reg) __raw_readb(reg)
  42 #define fsample_cpld_write(val, reg) __raw_writeb(val, reg)
  43
  44 #define FSAMPLE_CPLD_BASE    0xE8100000
  45 #define FSAMPLE_CPLD_SIZE    SZ_4K
  46 #define FSAMPLE_CPLD_START   0x05080000
  47
  48 #define FSAMPLE_CPLD_REG_A   (FSAMPLE_CPLD_BASE + 0x00)
  49 #define FSAMPLE_CPLD_SWITCH  (FSAMPLE_CPLD_BASE + 0x02)
  50 #define FSAMPLE_CPLD_UART    (FSAMPLE_CPLD_BASE + 0x02)
  51 #define FSAMPLE_CPLD_REG_B   (FSAMPLE_CPLD_BASE + 0x04)
  52 #define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06)
  53 #define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06)
  54
  55 #define FSAMPLE_CPLD_BIT_BT_RESET         0
  56 #define FSAMPLE_CPLD_BIT_LCD_RESET        1
  57 #define FSAMPLE_CPLD_BIT_CAM_PWDN         2
  58 #define FSAMPLE_CPLD_BIT_CHARGER_ENABLE   3
  59 #define FSAMPLE_CPLD_BIT_SD_MMC_EN        4
  60 #define FSAMPLE_CPLD_BIT_aGPS_PWREN       5
  61 #define FSAMPLE_CPLD_BIT_BACKLIGHT        6
  62 #define FSAMPLE_CPLD_BIT_aGPS_EN_RESET    7
  63 #define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N    8
  64 #define FSAMPLE_CPLD_BIT_OTG_RESET        9
  65
  66 #define fsample_cpld_set(bit) \
  67     fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR)
  68
  69 #define fsample_cpld_clear(bit) \
  70     fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
  71
  72 static int fsample_keymap[] = {
  73         KEY(0,0,KEY_UP),
  74         KEY(0,1,KEY_RIGHT),
  75         KEY(0,2,KEY_LEFT),
  76         KEY(0,3,KEY_DOWN),
  77         KEY(0,4,KEY_ENTER),
  78         KEY(1,0,KEY_F10),
  79         KEY(1,1,KEY_SEND),
  80         KEY(1,2,KEY_END),
  81         KEY(1,3,KEY_VOLUMEDOWN),
  82         KEY(1,4,KEY_VOLUMEUP),
  83         KEY(1,5,KEY_RECORD),
  84         KEY(2,0,KEY_F9),
  85         KEY(2,1,KEY_3),
  86         KEY(2,2,KEY_6),
  87         KEY(2,3,KEY_9),
  88         KEY(2,4,KEY_KPDOT),
  89         KEY(3,0,KEY_BACK),
  90         KEY(3,1,KEY_2),
  91         KEY(3,2,KEY_5),
  92         KEY(3,3,KEY_8),
  93         KEY(3,4,KEY_0),
  94         KEY(3,5,KEY_KPSLASH),
  95         KEY(4,0,KEY_HOME),
  96         KEY(4,1,KEY_1),
  97         KEY(4,2,KEY_4),
  98         KEY(4,3,KEY_7),
  99         KEY(4,4,KEY_KPASTERISK),
 100         KEY(4,5,KEY_POWER),
 101         0
 102 };
 103
 104 static struct smc91x_platdata smc91x_info = {
 105         .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
 106         .leda   = RPC_LED_100_10,
 107         .ledb   = RPC_LED_TX_RX,
 108 };
 109
 110 static struct resource smc91x_resources[] = {
 111         [0] = {
 112                 .start  = H2P2_DBG_FPGA_ETHR_START,     /* Physical */
 113                 .end    = H2P2_DBG_FPGA_ETHR_START + 0xf,
 114                 .flags  = IORESOURCE_MEM,
 115         },
 116         [1] = {
 117                 .start  = INT_7XX_MPU_EXT_NIRQ,
 118                 .end    = 0,
 119                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 120         },
 121 };
 122
 123 static struct mtd_partition nor_partitions[] = {
 124         /* bootloader (U-Boot, etc) in first sector */
 125         {
 126               .name             = "bootloader",
 127               .offset           = 0,
 128               .size             = SZ_128K,
 129               .mask_flags       = MTD_WRITEABLE, /* force read-only */
 130         },
 131         /* bootloader params in the next sector */
 132         {
 133               .name             = "params",
 134               .offset           = MTDPART_OFS_APPEND,
 135               .size             = SZ_128K,
 136               .mask_flags       = 0,
 137         },
 138         /* kernel */
 139         {
 140               .name             = "kernel",
 141               .offset           = MTDPART_OFS_APPEND,
 142               .size             = SZ_2M,
 143               .mask_flags       = 0
 144         },
 145         /* rest of flash is a file system */
 146         {
 147               .name             = "rootfs",
 148               .offset           = MTDPART_OFS_APPEND,
 149               .size             = MTDPART_SIZ_FULL,
 150               .mask_flags       = 0
 151         },
 152 };
 153
 154 static struct physmap_flash_data nor_data = {
 155         .width          = 2,
 156         .set_vpp        = omap1_set_vpp,
 157         .parts          = nor_partitions,
 158         .nr_parts       = ARRAY_SIZE(nor_partitions),
 159 };
 160
 161 static struct resource nor_resource = {
 162         .start          = OMAP_CS0_PHYS,
 163         .end            = OMAP_CS0_PHYS + SZ_32M - 1,
 164         .flags          = IORESOURCE_MEM,
 165 };
 166
 167 static struct platform_device nor_device = {
 168         .name           = "physmap-flash",
 169         .id             = 0,
 170         .dev            = {
 171                 .platform_data  = &nor_data,
 172         },
 173         .num_resources  = 1,
 174         .resource       = &nor_resource,
 175 };
 176
 177 static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 178 {
 179         struct nand_chip *this = mtd->priv;
 180         unsigned long mask;
 181
 182         if (cmd == NAND_CMD_NONE)
 183                 return;
 184
 185         mask = (ctrl & NAND_CLE) ? 0x02 : 0;
 186         if (ctrl & NAND_ALE)
 187                 mask |= 0x04;
 188         writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
 189 }
 190
 191 #define FSAMPLE_NAND_RB_GPIO_PIN        62
 192
 193 static int nand_dev_ready(struct mtd_info *mtd)
 194 {
 195         return gpio_get_value(FSAMPLE_NAND_RB_GPIO_PIN);
 196 }
 197
 198 static const char *part_probes[] = { "cmdlinepart", NULL };
 199
 200 static struct platform_nand_data nand_data = {
 201         .chip   = {
 202                 .nr_chips               = 1,
 203                 .chip_offset            = 0,
 204                 .options                = NAND_SAMSUNG_LP_OPTIONS,
 205                 .part_probe_types       = part_probes,
 206         },
 207         .ctrl   = {
 208                 .cmd_ctrl       = nand_cmd_ctl,
 209                 .dev_ready      = nand_dev_ready,
 210         },
 211 };
 212
 213 static struct resource nand_resource = {
 214         .start          = OMAP_CS3_PHYS,
 215         .end            = OMAP_CS3_PHYS + SZ_4K - 1,
 216         .flags          = IORESOURCE_MEM,
 217 };
 218
 219 static struct platform_device nand_device = {
 220         .name           = "gen_nand",
 221         .id             = 0,
 222         .dev            = {
 223                 .platform_data  = &nand_data,
 224         },
 225         .num_resources  = 1,
 226         .resource       = &nand_resource,
 227 };
 228
 229 static struct platform_device smc91x_device = {
 230         .name           = "smc91x",
 231         .id             = 0,
 232         .dev    = {
 233                 .platform_data  = &smc91x_info,
 234         },
 235         .num_resources  = ARRAY_SIZE(smc91x_resources),
 236         .resource       = smc91x_resources,
 237 };
 238
 239 static struct resource kp_resources[] = {
 240         [0] = {
 241                 .start  = INT_7XX_MPUIO_KEYPAD,
 242                 .end    = INT_7XX_MPUIO_KEYPAD,
 243                 .flags  = IORESOURCE_IRQ,
 244         },
 245 };
 246
 247 static struct omap_kp_platform_data kp_data = {
 248         .rows           = 8,
 249         .cols           = 8,
 250         .keymap         = fsample_keymap,
 251         .keymapsize     = ARRAY_SIZE(fsample_keymap),
 252         .delay          = 4,
 253 };
 254
 255 static struct platform_device kp_device = {
 256         .name           = "omap-keypad",
 257         .id             = -1,
 258         .dev            = {
 259                 .platform_data = &kp_data,
 260         },
 261         .num_resources  = ARRAY_SIZE(kp_resources),
 262         .resource       = kp_resources,
 263 };
 264
 265 static struct platform_device lcd_device = {
 266         .name           = "lcd_p2",
 267         .id             = -1,
 268 };
 269
 270 static struct platform_device *devices[] __initdata = {
 271         &nor_device,
 272         &nand_device,
 273         &smc91x_device,
 274         &kp_device,
 275         &lcd_device,
 276 };
 277
 278 static struct omap_lcd_config fsample_lcd_config __initdata = {
 279         .ctrl_name      = "internal",
 280 };
 281
 282 static struct omap_board_config_kernel fsample_config[] = {
 283         { OMAP_TAG_LCD,         &fsample_lcd_config },
 284 };
 285
 286 static void __init omap_fsample_init(void)
 287 {
 288         if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0)
 289                 BUG();
 290         gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN);
 291
 292         omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
 293         omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
 294
 295         /* Mux pins for keypad */
 296         omap_cfg_reg(E2_7XX_KBR0);
 297         omap_cfg_reg(J7_7XX_KBR1);
 298         omap_cfg_reg(E1_7XX_KBR2);
 299         omap_cfg_reg(F3_7XX_KBR3);
 300         omap_cfg_reg(D2_7XX_KBR4);
 301         omap_cfg_reg(C2_7XX_KBC0);
 302         omap_cfg_reg(D3_7XX_KBC1);
 303         omap_cfg_reg(E4_7XX_KBC2);
 304         omap_cfg_reg(F4_7XX_KBC3);
 305         omap_cfg_reg(E3_7XX_KBC4);
 306
 307         platform_add_devices(devices, ARRAY_SIZE(devices));
 308
 309         omap_board_config = fsample_config;
 310         omap_board_config_size = ARRAY_SIZE(fsample_config);
 311         omap_serial_init();
 312         omap_register_i2c_bus(1, 100, NULL, 0);
 313 }
 314
 315 static void __init fsample_init_smc91x(void)
 316 {
 317         fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
 318         mdelay(50);
 319         fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
 320                    H2P2_DBG_FPGA_LAN_RESET);
 321         mdelay(50);
 322 }
 323
 324 static void __init omap_fsample_init_irq(void)
 325 {
 326         omap1_init_common_hw();
 327         omap_init_irq();
 328         omap_gpio_init();
 329         fsample_init_smc91x();
 330 }
 331
 332 /* Only FPGA needs to be mapped here. All others are done with ioremap */
 333 static struct map_desc omap_fsample_io_desc[] __initdata = {
 334         {
 335                 .virtual        = H2P2_DBG_FPGA_BASE,
 336                 .pfn            = __phys_to_pfn(H2P2_DBG_FPGA_START),
 337                 .length         = H2P2_DBG_FPGA_SIZE,
 338                 .type           = MT_DEVICE
 339         },
 340         {
 341                 .virtual        = FSAMPLE_CPLD_BASE,
 342                 .pfn            = __phys_to_pfn(FSAMPLE_CPLD_START),
 343                 .length         = FSAMPLE_CPLD_SIZE,
 344                 .type           = MT_DEVICE
 345         }
 346 };
 347
 348 static void __init omap_fsample_map_io(void)
 349 {
 350         omap1_map_common_io();
 351         iotable_init(omap_fsample_io_desc,
 352                      ARRAY_SIZE(omap_fsample_io_desc));
 353
 354         /* Early, board-dependent init */
 355
 356         /*
 357          * Hold GSM Reset until needed
 358          */
 359         omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
 360
 361         /*
 362          * UARTs -> done automagically by 8250 driver
 363          */
 364
 365         /*
 366          * CSx timings, GPIO Mux ... setup
 367          */
 368
 369         /* Flash: CS0 timings setup */
 370         omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
 371         omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
 372
 373         /*
 374          * Ethernet support through the debug board
 375          * CS1 timings setup
 376          */
 377         omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
 378         omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
 379
 380         /*
 381          * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
 382          * It is used as the Ethernet controller interrupt
 383          */
 384         omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9);
 385 }
 386
 387 MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
 388 /* Maintainer: Brian Swetland <swetland@google.com> */
 389         .phys_io        = 0xfff00000,
 390         .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
 391         .boot_params    = 0x10000100,
 392         .map_io         = omap_fsample_map_io,
 393         .reserve        = omap_reserve,
 394         .init_irq       = omap_fsample_init_irq,
 395         .init_machine   = omap_fsample_init,
 396         .timer          = &omap_timer,
 397 MACHINE_END