arch/arm/mach-mx5/clock-mx51.c

   1 /*
   2  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/mm.h>
  14 #include <linux/delay.h>
  15 #include <linux/clk.h>
  16 #include <linux/io.h>
  17
  18 #include <asm/clkdev.h>
  19 #include <asm/div64.h>
  20
  21 #include <mach/hardware.h>
  22 #include <mach/common.h>
  23 #include <mach/clock.h>
  24
  25 #include "crm_regs.h"
  26
  27 /* External clock values passed-in by the board code */
  28 static unsigned long external_high_reference, external_low_reference;
  29 static unsigned long oscillator_reference, ckih2_reference;
  30
  31 static struct clk osc_clk;
  32 static struct clk pll1_main_clk;
  33 static struct clk pll1_sw_clk;
  34 static struct clk pll2_sw_clk;
  35 static struct clk pll3_sw_clk;
  36 static struct clk lp_apm_clk;
  37 static struct clk periph_apm_clk;
  38 static struct clk ahb_clk;
  39 static struct clk ipg_clk;
  40
  41 #define MAX_DPLL_WAIT_TRIES     1000 /* 1000 * udelay(1) = 1ms */
  42
  43 static int _clk_ccgr_enable(struct clk *clk)
  44 {
  45         u32 reg;
  46
  47         reg = __raw_readl(clk->enable_reg);
  48         reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift;
  49         __raw_writel(reg, clk->enable_reg);
  50
  51         return 0;
  52 }
  53
  54 static void _clk_ccgr_disable(struct clk *clk)
  55 {
  56         u32 reg;
  57         reg = __raw_readl(clk->enable_reg);
  58         reg &= ~(MXC_CCM_CCGRx_MOD_OFF << clk->enable_shift);
  59         __raw_writel(reg, clk->enable_reg);
  60
  61 }
  62
  63 static void _clk_ccgr_disable_inwait(struct clk *clk)
  64 {
  65         u32 reg;
  66
  67         reg = __raw_readl(clk->enable_reg);
  68         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
  69         reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift;
  70         __raw_writel(reg, clk->enable_reg);
  71 }
  72
  73 /*
  74  * For the 4-to-1 muxed input clock
  75  */
  76 static inline u32 _get_mux(struct clk *parent, struct clk *m0,
  77                            struct clk *m1, struct clk *m2, struct clk *m3)
  78 {
  79         if (parent == m0)
  80                 return 0;
  81         else if (parent == m1)
  82                 return 1;
  83         else if (parent == m2)
  84                 return 2;
  85         else if (parent == m3)
  86                 return 3;
  87         else
  88                 BUG();
  89
  90         return -EINVAL;
  91 }
  92
  93 static inline void __iomem *_get_pll_base(struct clk *pll)
  94 {
  95         if (pll == &pll1_main_clk)
  96                 return MX51_DPLL1_BASE;
  97         else if (pll == &pll2_sw_clk)
  98                 return MX51_DPLL2_BASE;
  99         else if (pll == &pll3_sw_clk)
 100                 return MX51_DPLL3_BASE;
 101         else
 102                 BUG();
 103
 104         return NULL;
 105 }
 106
 107 static unsigned long clk_pll_get_rate(struct clk *clk)
 108 {
 109         long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
 110         unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
 111         void __iomem *pllbase;
 112         s64 temp;
 113         unsigned long parent_rate;
 114
 115         parent_rate = clk_get_rate(clk->parent);
 116
 117         pllbase = _get_pll_base(clk);
 118
 119         dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
 120         pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
 121         dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
 122
 123         if (pll_hfsm == 0) {
 124                 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
 125                 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
 126                 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
 127         } else {
 128                 dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
 129                 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
 130                 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
 131         }
 132         pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
 133         mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
 134         mfi = (mfi <= 5) ? 5 : mfi;
 135         mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
 136         mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
 137         /* Sign extend to 32-bits */
 138         if (mfn >= 0x04000000) {
 139                 mfn |= 0xFC000000;
 140                 mfn_abs = -mfn;
 141         }
 142
 143         ref_clk = 2 * parent_rate;
 144         if (dbl != 0)
 145                 ref_clk *= 2;
 146
 147         ref_clk /= (pdf + 1);
 148         temp = (u64) ref_clk * mfn_abs;
 149         do_div(temp, mfd + 1);
 150         if (mfn < 0)
 151                 temp = -temp;
 152         temp = (ref_clk * mfi) + temp;
 153
 154         return temp;
 155 }
 156
 157 static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
 158 {
 159         u32 reg;
 160         void __iomem *pllbase;
 161
 162         long mfi, pdf, mfn, mfd = 999999;
 163         s64 temp64;
 164         unsigned long quad_parent_rate;
 165         unsigned long pll_hfsm, dp_ctl;
 166         unsigned long parent_rate;
 167
 168         parent_rate = clk_get_rate(clk->parent);
 169
 170         pllbase = _get_pll_base(clk);
 171
 172         quad_parent_rate = 4 * parent_rate;
 173         pdf = mfi = -1;
 174         while (++pdf < 16 && mfi < 5)
 175                 mfi = rate * (pdf+1) / quad_parent_rate;
 176         if (mfi > 15)
 177                 return -EINVAL;
 178         pdf--;
 179
 180         temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
 181         do_div(temp64, quad_parent_rate/1000000);
 182         mfn = (long)temp64;
 183
 184         dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
 185         /* use dpdck0_2 */
 186         __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
 187         pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
 188         if (pll_hfsm == 0) {
 189                 reg = mfi << 4 | pdf;
 190                 __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
 191                 __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
 192                 __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
 193         } else {
 194                 reg = mfi << 4 | pdf;
 195                 __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
 196                 __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
 197                 __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
 198         }
 199
 200         return 0;
 201 }
 202
 203 static int _clk_pll_enable(struct clk *clk)
 204 {
 205         u32 reg;
 206         void __iomem *pllbase;
 207         int i = 0;
 208
 209         pllbase = _get_pll_base(clk);
 210         reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
 211         __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
 212
 213         /* Wait for lock */
 214         do {
 215                 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
 216                 if (reg & MXC_PLL_DP_CTL_LRF)
 217                         break;
 218
 219                 udelay(1);
 220         } while (++i < MAX_DPLL_WAIT_TRIES);
 221
 222         if (i == MAX_DPLL_WAIT_TRIES) {
 223                 pr_err("MX5: pll locking failed\n");
 224                 return -EINVAL;
 225         }
 226
 227         return 0;
 228 }
 229
 230 static void _clk_pll_disable(struct clk *clk)
 231 {
 232         u32 reg;
 233         void __iomem *pllbase;
 234
 235         pllbase = _get_pll_base(clk);
 236         reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
 237         __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
 238 }
 239
 240 static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
 241 {
 242         u32 reg, step;
 243
 244         reg = __raw_readl(MXC_CCM_CCSR);
 245
 246         /* When switching from pll_main_clk to a bypass clock, first select a
 247          * multiplexed clock in 'step_sel', then shift the glitchless mux
 248          * 'pll1_sw_clk_sel'.
 249          *
 250          * When switching back, do it in reverse order
 251          */
 252         if (parent == &pll1_main_clk) {
 253                 /* Switch to pll1_main_clk */
 254                 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 255                 __raw_writel(reg, MXC_CCM_CCSR);
 256                 /* step_clk mux switched to lp_apm, to save power. */
 257                 reg = __raw_readl(MXC_CCM_CCSR);
 258                 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
 259                 reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM <<
 260                                 MXC_CCM_CCSR_STEP_SEL_OFFSET);
 261         } else {
 262                 if (parent == &lp_apm_clk) {
 263                         step = MXC_CCM_CCSR_STEP_SEL_LP_APM;
 264                 } else  if (parent == &pll2_sw_clk) {
 265                         step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED;
 266                 } else  if (parent == &pll3_sw_clk) {
 267                         step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED;
 268                 } else
 269                         return -EINVAL;
 270
 271                 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
 272                 reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET);
 273
 274                 __raw_writel(reg, MXC_CCM_CCSR);
 275                 /* Switch to step_clk */
 276                 reg = __raw_readl(MXC_CCM_CCSR);
 277                 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 278         }
 279         __raw_writel(reg, MXC_CCM_CCSR);
 280         return 0;
 281 }
 282
 283 static unsigned long clk_pll1_sw_get_rate(struct clk *clk)
 284 {
 285         u32 reg, div;
 286         unsigned long parent_rate;
 287
 288         parent_rate = clk_get_rate(clk->parent);
 289
 290         reg = __raw_readl(MXC_CCM_CCSR);
 291
 292         if (clk->parent == &pll2_sw_clk) {
 293                 div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
 294                        MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
 295         } else if (clk->parent == &pll3_sw_clk) {
 296                 div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
 297                        MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
 298         } else
 299                 div = 1;
 300         return parent_rate / div;
 301 }
 302
 303 static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
 304 {
 305         u32 reg;
 306
 307         reg = __raw_readl(MXC_CCM_CCSR);
 308
 309         if (parent == &pll2_sw_clk)
 310                 reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
 311         else
 312                 reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
 313
 314         __raw_writel(reg, MXC_CCM_CCSR);
 315         return 0;
 316 }
 317
 318 static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
 319 {
 320         u32 reg;
 321
 322         if (parent == &osc_clk)
 323                 reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
 324         else
 325                 return -EINVAL;
 326
 327         __raw_writel(reg, MXC_CCM_CCSR);
 328
 329         return 0;
 330 }
 331
 332 static unsigned long clk_arm_get_rate(struct clk *clk)
 333 {
 334         u32 cacrr, div;
 335         unsigned long parent_rate;
 336
 337         parent_rate = clk_get_rate(clk->parent);
 338         cacrr = __raw_readl(MXC_CCM_CACRR);
 339         div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
 340
 341         return parent_rate / div;
 342 }
 343
 344 static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
 345 {
 346         u32 reg, mux;
 347         int i = 0;
 348
 349         mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
 350
 351         reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
 352         reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
 353         __raw_writel(reg, MXC_CCM_CBCMR);
 354
 355         /* Wait for lock */
 356         do {
 357                 reg = __raw_readl(MXC_CCM_CDHIPR);
 358                 if (!(reg &  MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY))
 359                         break;
 360
 361                 udelay(1);
 362         } while (++i < MAX_DPLL_WAIT_TRIES);
 363
 364         if (i == MAX_DPLL_WAIT_TRIES) {
 365                 pr_err("MX5: Set parent for periph_apm clock failed\n");
 366                 return -EINVAL;
 367         }
 368
 369         return 0;
 370 }
 371
 372 static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
 373 {
 374         u32 reg;
 375
 376         reg = __raw_readl(MXC_CCM_CBCDR);
 377
 378         if (parent == &pll2_sw_clk)
 379                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
 380         else if (parent == &periph_apm_clk)
 381                 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
 382         else
 383                 return -EINVAL;
 384
 385         __raw_writel(reg, MXC_CCM_CBCDR);
 386
 387         return 0;
 388 }
 389
 390 static struct clk main_bus_clk = {
 391         .parent = &pll2_sw_clk,
 392         .set_parent = _clk_main_bus_set_parent,
 393 };
 394
 395 static unsigned long clk_ahb_get_rate(struct clk *clk)
 396 {
 397         u32 reg, div;
 398         unsigned long parent_rate;
 399
 400         parent_rate = clk_get_rate(clk->parent);
 401
 402         reg = __raw_readl(MXC_CCM_CBCDR);
 403         div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
 404                MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
 405         return parent_rate / div;
 406 }
 407
 408
 409 static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
 410 {
 411         u32 reg, div;
 412         unsigned long parent_rate;
 413         int i = 0;
 414
 415         parent_rate = clk_get_rate(clk->parent);
 416
 417         div = parent_rate / rate;
 418         if (div > 8 || div < 1 || ((parent_rate / div) != rate))
 419                 return -EINVAL;
 420
 421         reg = __raw_readl(MXC_CCM_CBCDR);
 422         reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
 423         reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
 424         __raw_writel(reg, MXC_CCM_CBCDR);
 425
 426         /* Wait for lock */
 427         do {
 428                 reg = __raw_readl(MXC_CCM_CDHIPR);
 429                 if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY))
 430                         break;
 431
 432                 udelay(1);
 433         } while (++i < MAX_DPLL_WAIT_TRIES);
 434
 435         if (i == MAX_DPLL_WAIT_TRIES) {
 436                 pr_err("MX5: clk_ahb_set_rate failed\n");
 437                 return -EINVAL;
 438         }
 439
 440         return 0;
 441 }
 442
 443 static unsigned long _clk_ahb_round_rate(struct clk *clk,
 444                                                 unsigned long rate)
 445 {
 446         u32 div;
 447         unsigned long parent_rate;
 448
 449         parent_rate = clk_get_rate(clk->parent);
 450
 451         div = parent_rate / rate;
 452         if (div > 8)
 453                 div = 8;
 454         else if (div == 0)
 455                 div++;
 456         return parent_rate / div;
 457 }
 458
 459
 460 static int _clk_max_enable(struct clk *clk)
 461 {
 462         u32 reg;
 463
 464         _clk_ccgr_enable(clk);
 465
 466         /* Handshake with MAX when LPM is entered. */
 467         reg = __raw_readl(MXC_CCM_CLPCR);
 468         reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
 469         __raw_writel(reg, MXC_CCM_CLPCR);
 470
 471         return 0;
 472 }
 473
 474 static void _clk_max_disable(struct clk *clk)
 475 {
 476         u32 reg;
 477
 478         _clk_ccgr_disable_inwait(clk);
 479
 480         /* No Handshake with MAX when LPM is entered as its disabled. */
 481         reg = __raw_readl(MXC_CCM_CLPCR);
 482         reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
 483         __raw_writel(reg, MXC_CCM_CLPCR);
 484 }
 485
 486 static unsigned long clk_ipg_get_rate(struct clk *clk)
 487 {
 488         u32 reg, div;
 489         unsigned long parent_rate;
 490
 491         parent_rate = clk_get_rate(clk->parent);
 492
 493         reg = __raw_readl(MXC_CCM_CBCDR);
 494         div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
 495                MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
 496
 497         return parent_rate / div;
 498 }
 499
 500 static unsigned long clk_ipg_per_get_rate(struct clk *clk)
 501 {
 502         u32 reg, prediv1, prediv2, podf;
 503         unsigned long parent_rate;
 504
 505         parent_rate = clk_get_rate(clk->parent);
 506
 507         if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
 508                 /* the main_bus_clk is the one before the DVFS engine */
 509                 reg = __raw_readl(MXC_CCM_CBCDR);
 510                 prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
 511                            MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
 512                 prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
 513                            MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
 514                 podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
 515                         MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
 516                 return parent_rate / (prediv1 * prediv2 * podf);
 517         } else if (clk->parent == &ipg_clk)
 518                 return parent_rate;
 519         else
 520                 BUG();
 521 }
 522
 523 static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
 524 {
 525         u32 reg;
 526
 527         reg = __raw_readl(MXC_CCM_CBCMR);
 528
 529         reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
 530         reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
 531
 532         if (parent == &ipg_clk)
 533                 reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
 534         else if (parent == &lp_apm_clk)
 535                 reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
 536         else if (parent != &main_bus_clk)
 537                 return -EINVAL;
 538
 539         __raw_writel(reg, MXC_CCM_CBCMR);
 540
 541         return 0;
 542 }
 543
 544 static unsigned long clk_uart_get_rate(struct clk *clk)
 545 {
 546         u32 reg, prediv, podf;
 547         unsigned long parent_rate;
 548
 549         parent_rate = clk_get_rate(clk->parent);
 550
 551         reg = __raw_readl(MXC_CCM_CSCDR1);
 552         prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
 553                   MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
 554         podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
 555                 MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
 556
 557         return parent_rate / (prediv * podf);
 558 }
 559
 560 static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
 561 {
 562         u32 reg, mux;
 563
 564         mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
 565                        &lp_apm_clk);
 566         reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK;
 567         reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
 568         __raw_writel(reg, MXC_CCM_CSCMR1);
 569
 570         return 0;
 571 }
 572
 573 static unsigned long get_high_reference_clock_rate(struct clk *clk)
 574 {
 575         return external_high_reference;
 576 }
 577
 578 static unsigned long get_low_reference_clock_rate(struct clk *clk)
 579 {
 580         return external_low_reference;
 581 }
 582
 583 static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
 584 {
 585         return oscillator_reference;
 586 }
 587
 588 static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
 589 {
 590         return ckih2_reference;
 591 }
 592
 593 /* External high frequency clock */
 594 static struct clk ckih_clk = {
 595         .get_rate = get_high_reference_clock_rate,
 596 };
 597
 598 static struct clk ckih2_clk = {
 599         .get_rate = get_ckih2_reference_clock_rate,
 600 };
 601
 602 static struct clk osc_clk = {
 603         .get_rate = get_oscillator_reference_clock_rate,
 604 };
 605
 606 /* External low frequency (32kHz) clock */
 607 static struct clk ckil_clk = {
 608         .get_rate = get_low_reference_clock_rate,
 609 };
 610
 611 static struct clk pll1_main_clk = {
 612         .parent = &osc_clk,
 613         .get_rate = clk_pll_get_rate,
 614         .enable = _clk_pll_enable,
 615         .disable = _clk_pll_disable,
 616 };
 617
 618 /* Clock tree block diagram (WIP):
 619  *      CCM: Clock Controller Module
 620  *
 621  * PLL output -> |
 622  *               | CCM Switcher -> CCM_CLK_ROOT_GEN ->
 623  * PLL bypass -> |
 624  *
 625  */
 626
 627 /* PLL1 SW supplies to ARM core */
 628 static struct clk pll1_sw_clk = {
 629         .parent = &pll1_main_clk,
 630         .set_parent = _clk_pll1_sw_set_parent,
 631         .get_rate = clk_pll1_sw_get_rate,
 632 };
 633
 634 /* PLL2 SW supplies to AXI/AHB/IP buses */
 635 static struct clk pll2_sw_clk = {
 636         .parent = &osc_clk,
 637         .get_rate = clk_pll_get_rate,
 638         .set_rate = _clk_pll_set_rate,
 639         .set_parent = _clk_pll2_sw_set_parent,
 640         .enable = _clk_pll_enable,
 641         .disable = _clk_pll_disable,
 642 };
 643
 644 /* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
 645 static struct clk pll3_sw_clk = {
 646         .parent = &osc_clk,
 647         .set_rate = _clk_pll_set_rate,
 648         .get_rate = clk_pll_get_rate,
 649         .enable = _clk_pll_enable,
 650         .disable = _clk_pll_disable,
 651 };
 652
 653 /* Low-power Audio Playback Mode clock */
 654 static struct clk lp_apm_clk = {
 655         .parent = &osc_clk,
 656         .set_parent = _clk_lp_apm_set_parent,
 657 };
 658
 659 static struct clk periph_apm_clk = {
 660         .parent = &pll1_sw_clk,
 661         .set_parent = _clk_periph_apm_set_parent,
 662 };
 663
 664 static struct clk cpu_clk = {
 665         .parent = &pll1_sw_clk,
 666         .get_rate = clk_arm_get_rate,
 667 };
 668
 669 static struct clk ahb_clk = {
 670         .parent = &main_bus_clk,
 671         .get_rate = clk_ahb_get_rate,
 672         .set_rate = _clk_ahb_set_rate,
 673         .round_rate = _clk_ahb_round_rate,
 674 };
 675
 676 /* Main IP interface clock for access to registers */
 677 static struct clk ipg_clk = {
 678         .parent = &ahb_clk,
 679         .get_rate = clk_ipg_get_rate,
 680 };
 681
 682 static struct clk ipg_perclk = {
 683         .parent = &lp_apm_clk,
 684         .get_rate = clk_ipg_per_get_rate,
 685         .set_parent = _clk_ipg_per_set_parent,
 686 };
 687
 688 static struct clk uart_root_clk = {
 689         .parent = &pll2_sw_clk,
 690         .get_rate = clk_uart_get_rate,
 691         .set_parent = _clk_uart_set_parent,
 692 };
 693
 694 static struct clk ahb_max_clk = {
 695         .parent = &ahb_clk,
 696         .enable_reg = MXC_CCM_CCGR0,
 697         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
 698         .enable = _clk_max_enable,
 699         .disable = _clk_max_disable,
 700 };
 701
 702 static struct clk aips_tz1_clk = {
 703         .parent = &ahb_clk,
 704         .secondary = &ahb_max_clk,
 705         .enable_reg = MXC_CCM_CCGR0,
 706         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
 707         .enable = _clk_ccgr_enable,
 708         .disable = _clk_ccgr_disable_inwait,
 709 };
 710
 711 static struct clk aips_tz2_clk = {
 712         .parent = &ahb_clk,
 713         .secondary = &ahb_max_clk,
 714         .enable_reg = MXC_CCM_CCGR0,
 715         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
 716         .enable = _clk_ccgr_enable,
 717         .disable = _clk_ccgr_disable_inwait,
 718 };
 719
 720 static struct clk gpt_32k_clk = {
 721         .id = 0,
 722         .parent = &ckil_clk,
 723 };
 724
 725 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)     \
 726         static struct clk name = {                      \
 727                 .id             = i,                    \
 728                 .enable_reg     = er,                   \
 729                 .enable_shift   = es,                   \
 730                 .get_rate       = gr,                   \
 731                 .set_rate       = sr,                   \
 732                 .enable         = _clk_ccgr_enable,     \
 733                 .disable        = _clk_ccgr_disable,    \
 734                 .parent         = p,                    \
 735                 .secondary      = s,                    \
 736         }
 737
 738 /* DEFINE_CLOCK(name, id, enable_reg, enable_shift,
 739    get_rate, set_rate, parent, secondary); */
 740
 741 /* Shared peripheral bus arbiter */
 742 DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
 743         NULL,  NULL, &ipg_clk, NULL);
 744
 745 /* UART */
 746 DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
 747         NULL,  NULL, &uart_root_clk, NULL);
 748 DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
 749         NULL,  NULL, &uart_root_clk, NULL);
 750 DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
 751         NULL,  NULL, &uart_root_clk, NULL);
 752 DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
 753         NULL,  NULL, &ipg_clk, &aips_tz1_clk);
 754 DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
 755         NULL,  NULL, &ipg_clk, &aips_tz1_clk);
 756 DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
 757         NULL,  NULL, &ipg_clk, &spba_clk);
 758
 759 /* GPT */
 760 DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
 761         NULL,  NULL, &ipg_clk, NULL);
 762 DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
 763         NULL,  NULL, &ipg_clk, NULL);
 764
 765 /* FEC */
 766 DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
 767         NULL,  NULL, &ipg_clk, NULL);
 768
 769 #define _REGISTER_CLOCK(d, n, c) \
 770        { \
 771                 .dev_id = d, \
 772                 .con_id = n, \
 773                 .clk = &c,   \
 774        },
 775
 776 static struct clk_lookup lookups[] = {
 777         _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
 778         _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
 779         _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
 780         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
 781         _REGISTER_CLOCK("fec.0", NULL, fec_clk)
 782 };
 783
 784 static void clk_tree_init(void)
 785 {
 786         u32 reg;
 787
 788         ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
 789
 790         /*
 791          * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
 792          * 8MHz, its derived from lp_apm.
 793          *
 794          * FIXME: Verify if true for all boards
 795          */
 796         reg = __raw_readl(MXC_CCM_CBCDR);
 797         reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
 798         reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
 799         reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
 800         reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
 801         __raw_writel(reg, MXC_CCM_CBCDR);
 802 }
 803
 804 int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
 805                         unsigned long ckih1, unsigned long ckih2)
 806 {
 807         int i;
 808
 809         external_low_reference = ckil;
 810         external_high_reference = ckih1;
 811         ckih2_reference = ckih2;
 812         oscillator_reference = osc;
 813
 814         for (i = 0; i < ARRAY_SIZE(lookups); i++)
 815                 clkdev_add(&lookups[i]);
 816
 817         clk_tree_init();
 818
 819         clk_enable(&cpu_clk);
 820         clk_enable(&main_bus_clk);
 821
 822         /* System timer */
 823         mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
 824                 MX51_MXC_INT_GPT);
 825         return 0;
 826 }