arch/arm/mach-mx5/clock-mx51-mx53.c

   1 /*
   2  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/mm.h>
  14 #include <linux/delay.h>
  15 #include <linux/clk.h>
  16 #include <linux/io.h>
  17 #include <linux/clkdev.h>
  18
  19 #include <asm/div64.h>
  20
  21 #include <mach/hardware.h>
  22 #include <mach/common.h>
  23 #include <mach/clock.h>
  24
  25 #include "crm_regs.h"
  26
  27 /* External clock values passed-in by the board code */
  28 static unsigned long external_high_reference, external_low_reference;
  29 static unsigned long oscillator_reference, ckih2_reference;
  30
  31 static struct clk osc_clk;
  32 static struct clk pll1_main_clk;
  33 static struct clk pll1_sw_clk;
  34 static struct clk pll2_sw_clk;
  35 static struct clk pll3_sw_clk;
  36 static struct clk mx53_pll4_sw_clk;
  37 static struct clk lp_apm_clk;
  38 static struct clk periph_apm_clk;
  39 static struct clk ahb_clk;
  40 static struct clk ipg_clk;
  41 static struct clk usboh3_clk;
  42 static struct clk emi_fast_clk;
  43 static struct clk ipu_clk;
  44 static struct clk mipi_hsc1_clk;
  45 static struct clk esdhc1_clk;
  46 static struct clk esdhc2_clk;
  47 static struct clk esdhc3_mx53_clk;
  48
  49 #define MAX_DPLL_WAIT_TRIES     1000 /* 1000 * udelay(1) = 1ms */
  50
  51 /* calculate best pre and post dividers to get the required divider */
  52 static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post,
  53         u32 max_pre, u32 max_post)
  54 {
  55         if (div >= max_pre * max_post) {
  56                 *pre = max_pre;
  57                 *post = max_post;
  58         } else if (div >= max_pre) {
  59                 u32 min_pre, temp_pre, old_err, err;
  60                 min_pre = DIV_ROUND_UP(div, max_post);
  61                 old_err = max_pre;
  62                 for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) {
  63                         err = div % temp_pre;
  64                         if (err == 0) {
  65                                 *pre = temp_pre;
  66                                 break;
  67                         }
  68                         err = temp_pre - err;
  69                         if (err < old_err) {
  70                                 old_err = err;
  71                                 *pre = temp_pre;
  72                         }
  73                 }
  74                 *post = DIV_ROUND_UP(div, *pre);
  75         } else {
  76                 *pre = div;
  77                 *post = 1;
  78         }
  79 }
  80
  81 static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
  82 {
  83         u32 reg = __raw_readl(clk->enable_reg);
  84
  85         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
  86         reg |= mode << clk->enable_shift;
  87
  88         __raw_writel(reg, clk->enable_reg);
  89 }
  90
  91 static int _clk_ccgr_enable(struct clk *clk)
  92 {
  93         _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON);
  94         return 0;
  95 }
  96
  97 static void _clk_ccgr_disable(struct clk *clk)
  98 {
  99         _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF);
 100 }
 101
 102 static int _clk_ccgr_enable_inrun(struct clk *clk)
 103 {
 104         _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
 105         return 0;
 106 }
 107
 108 static void _clk_ccgr_disable_inwait(struct clk *clk)
 109 {
 110         _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
 111 }
 112
 113 /*
 114  * For the 4-to-1 muxed input clock
 115  */
 116 static inline u32 _get_mux(struct clk *parent, struct clk *m0,
 117                            struct clk *m1, struct clk *m2, struct clk *m3)
 118 {
 119         if (parent == m0)
 120                 return 0;
 121         else if (parent == m1)
 122                 return 1;
 123         else if (parent == m2)
 124                 return 2;
 125         else if (parent == m3)
 126                 return 3;
 127         else
 128                 BUG();
 129
 130         return -EINVAL;
 131 }
 132
 133 static inline void __iomem *_mx51_get_pll_base(struct clk *pll)
 134 {
 135         if (pll == &pll1_main_clk)
 136                 return MX51_DPLL1_BASE;
 137         else if (pll == &pll2_sw_clk)
 138                 return MX51_DPLL2_BASE;
 139         else if (pll == &pll3_sw_clk)
 140                 return MX51_DPLL3_BASE;
 141         else
 142                 BUG();
 143
 144         return NULL;
 145 }
 146
 147 static inline void __iomem *_mx53_get_pll_base(struct clk *pll)
 148 {
 149         if (pll == &pll1_main_clk)
 150                 return MX53_DPLL1_BASE;
 151         else if (pll == &pll2_sw_clk)
 152                 return MX53_DPLL2_BASE;
 153         else if (pll == &pll3_sw_clk)
 154                 return MX53_DPLL3_BASE;
 155         else if (pll == &mx53_pll4_sw_clk)
 156                 return MX53_DPLL4_BASE;
 157         else
 158                 BUG();
 159
 160         return NULL;
 161 }
 162
 163 static inline void __iomem *_get_pll_base(struct clk *pll)
 164 {
 165         if (cpu_is_mx51())
 166                 return _mx51_get_pll_base(pll);
 167         else
 168                 return _mx53_get_pll_base(pll);
 169 }
 170
 171 static unsigned long clk_pll_get_rate(struct clk *clk)
 172 {
 173         long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
 174         unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
 175         void __iomem *pllbase;
 176         s64 temp;
 177         unsigned long parent_rate;
 178
 179         parent_rate = clk_get_rate(clk->parent);
 180
 181         pllbase = _get_pll_base(clk);
 182
 183         dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
 184         pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
 185         dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
 186
 187         if (pll_hfsm == 0) {
 188                 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
 189                 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
 190                 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
 191         } else {
 192                 dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
 193                 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
 194                 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
 195         }
 196         pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
 197         mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
 198         mfi = (mfi <= 5) ? 5 : mfi;
 199         mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
 200         mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
 201         /* Sign extend to 32-bits */
 202         if (mfn >= 0x04000000) {
 203                 mfn |= 0xFC000000;
 204                 mfn_abs = -mfn;
 205         }
 206
 207         ref_clk = 2 * parent_rate;
 208         if (dbl != 0)
 209                 ref_clk *= 2;
 210
 211         ref_clk /= (pdf + 1);
 212         temp = (u64) ref_clk * mfn_abs;
 213         do_div(temp, mfd + 1);
 214         if (mfn < 0)
 215                 temp = -temp;
 216         temp = (ref_clk * mfi) + temp;
 217
 218         return temp;
 219 }
 220
 221 static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
 222 {
 223         u32 reg;
 224         void __iomem *pllbase;
 225
 226         long mfi, pdf, mfn, mfd = 999999;
 227         s64 temp64;
 228         unsigned long quad_parent_rate;
 229         unsigned long pll_hfsm, dp_ctl;
 230         unsigned long parent_rate;
 231
 232         parent_rate = clk_get_rate(clk->parent);
 233
 234         pllbase = _get_pll_base(clk);
 235
 236         quad_parent_rate = 4 * parent_rate;
 237         pdf = mfi = -1;
 238         while (++pdf < 16 && mfi < 5)
 239                 mfi = rate * (pdf+1) / quad_parent_rate;
 240         if (mfi > 15)
 241                 return -EINVAL;
 242         pdf--;
 243
 244         temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
 245         do_div(temp64, quad_parent_rate/1000000);
 246         mfn = (long)temp64;
 247
 248         dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
 249         /* use dpdck0_2 */
 250         __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
 251         pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
 252         if (pll_hfsm == 0) {
 253                 reg = mfi << 4 | pdf;
 254                 __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
 255                 __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
 256                 __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
 257         } else {
 258                 reg = mfi << 4 | pdf;
 259                 __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
 260                 __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
 261                 __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
 262         }
 263
 264         return 0;
 265 }
 266
 267 static int _clk_pll_enable(struct clk *clk)
 268 {
 269         u32 reg;
 270         void __iomem *pllbase;
 271         int i = 0;
 272
 273         pllbase = _get_pll_base(clk);
 274         reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
 275         __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
 276
 277         /* Wait for lock */
 278         do {
 279                 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
 280                 if (reg & MXC_PLL_DP_CTL_LRF)
 281                         break;
 282
 283                 udelay(1);
 284         } while (++i < MAX_DPLL_WAIT_TRIES);
 285
 286         if (i == MAX_DPLL_WAIT_TRIES) {
 287                 pr_err("MX5: pll locking failed\n");
 288                 return -EINVAL;
 289         }
 290
 291         return 0;
 292 }
 293
 294 static void _clk_pll_disable(struct clk *clk)
 295 {
 296         u32 reg;
 297         void __iomem *pllbase;
 298
 299         pllbase = _get_pll_base(clk);
 300         reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
 301         __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
 302 }
 303
 304 static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
 305 {
 306         u32 reg, step;
 307
 308         reg = __raw_readl(MXC_CCM_CCSR);
 309
 310         /* When switching from pll_main_clk to a bypass clock, first select a
 311          * multiplexed clock in 'step_sel', then shift the glitchless mux
 312          * 'pll1_sw_clk_sel'.
 313          *
 314          * When switching back, do it in reverse order
 315          */
 316         if (parent == &pll1_main_clk) {
 317                 /* Switch to pll1_main_clk */
 318                 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 319                 __raw_writel(reg, MXC_CCM_CCSR);
 320                 /* step_clk mux switched to lp_apm, to save power. */
 321                 reg = __raw_readl(MXC_CCM_CCSR);
 322                 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
 323                 reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM <<
 324                                 MXC_CCM_CCSR_STEP_SEL_OFFSET);
 325         } else {
 326                 if (parent == &lp_apm_clk) {
 327                         step = MXC_CCM_CCSR_STEP_SEL_LP_APM;
 328                 } else  if (parent == &pll2_sw_clk) {
 329                         step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED;
 330                 } else  if (parent == &pll3_sw_clk) {
 331                         step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED;
 332                 } else
 333                         return -EINVAL;
 334
 335                 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
 336                 reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET);
 337
 338                 __raw_writel(reg, MXC_CCM_CCSR);
 339                 /* Switch to step_clk */
 340                 reg = __raw_readl(MXC_CCM_CCSR);
 341                 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 342         }
 343         __raw_writel(reg, MXC_CCM_CCSR);
 344         return 0;
 345 }
 346
 347 static unsigned long clk_pll1_sw_get_rate(struct clk *clk)
 348 {
 349         u32 reg, div;
 350         unsigned long parent_rate;
 351
 352         parent_rate = clk_get_rate(clk->parent);
 353
 354         reg = __raw_readl(MXC_CCM_CCSR);
 355
 356         if (clk->parent == &pll2_sw_clk) {
 357                 div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
 358                        MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
 359         } else if (clk->parent == &pll3_sw_clk) {
 360                 div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
 361                        MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
 362         } else
 363                 div = 1;
 364         return parent_rate / div;
 365 }
 366
 367 static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
 368 {
 369         u32 reg;
 370
 371         reg = __raw_readl(MXC_CCM_CCSR);
 372
 373         if (parent == &pll2_sw_clk)
 374                 reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
 375         else
 376                 reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
 377
 378         __raw_writel(reg, MXC_CCM_CCSR);
 379         return 0;
 380 }
 381
 382 static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
 383 {
 384         u32 reg;
 385
 386         if (parent == &osc_clk)
 387                 reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
 388         else
 389                 return -EINVAL;
 390
 391         __raw_writel(reg, MXC_CCM_CCSR);
 392
 393         return 0;
 394 }
 395
 396 static unsigned long clk_cpu_get_rate(struct clk *clk)
 397 {
 398         u32 cacrr, div;
 399         unsigned long parent_rate;
 400
 401         parent_rate = clk_get_rate(clk->parent);
 402         cacrr = __raw_readl(MXC_CCM_CACRR);
 403         div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
 404
 405         return parent_rate / div;
 406 }
 407
 408 static int clk_cpu_set_rate(struct clk *clk, unsigned long rate)
 409 {
 410         u32 reg, cpu_podf;
 411         unsigned long parent_rate;
 412
 413         parent_rate = clk_get_rate(clk->parent);
 414         cpu_podf = parent_rate / rate - 1;
 415         /* use post divider to change freq */
 416         reg = __raw_readl(MXC_CCM_CACRR);
 417         reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
 418         reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;
 419         __raw_writel(reg, MXC_CCM_CACRR);
 420
 421         return 0;
 422 }
 423
 424 static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
 425 {
 426         u32 reg, mux;
 427         int i = 0;
 428
 429         mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
 430
 431         reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
 432         reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
 433         __raw_writel(reg, MXC_CCM_CBCMR);
 434
 435         /* Wait for lock */
 436         do {
 437                 reg = __raw_readl(MXC_CCM_CDHIPR);
 438                 if (!(reg &  MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY))
 439                         break;
 440
 441                 udelay(1);
 442         } while (++i < MAX_DPLL_WAIT_TRIES);
 443
 444         if (i == MAX_DPLL_WAIT_TRIES) {
 445                 pr_err("MX5: Set parent for periph_apm clock failed\n");
 446                 return -EINVAL;
 447         }
 448
 449         return 0;
 450 }
 451
 452 static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
 453 {
 454         u32 reg;
 455
 456         reg = __raw_readl(MXC_CCM_CBCDR);
 457
 458         if (parent == &pll2_sw_clk)
 459                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
 460         else if (parent == &periph_apm_clk)
 461                 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
 462         else
 463                 return -EINVAL;
 464
 465         __raw_writel(reg, MXC_CCM_CBCDR);
 466
 467         return 0;
 468 }
 469
 470 static struct clk main_bus_clk = {
 471         .parent = &pll2_sw_clk,
 472         .set_parent = _clk_main_bus_set_parent,
 473 };
 474
 475 static unsigned long clk_ahb_get_rate(struct clk *clk)
 476 {
 477         u32 reg, div;
 478         unsigned long parent_rate;
 479
 480         parent_rate = clk_get_rate(clk->parent);
 481
 482         reg = __raw_readl(MXC_CCM_CBCDR);
 483         div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
 484                MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
 485         return parent_rate / div;
 486 }
 487
 488
 489 static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
 490 {
 491         u32 reg, div;
 492         unsigned long parent_rate;
 493         int i = 0;
 494
 495         parent_rate = clk_get_rate(clk->parent);
 496
 497         div = parent_rate / rate;
 498         if (div > 8 || div < 1 || ((parent_rate / div) != rate))
 499                 return -EINVAL;
 500
 501         reg = __raw_readl(MXC_CCM_CBCDR);
 502         reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
 503         reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
 504         __raw_writel(reg, MXC_CCM_CBCDR);
 505
 506         /* Wait for lock */
 507         do {
 508                 reg = __raw_readl(MXC_CCM_CDHIPR);
 509                 if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY))
 510                         break;
 511
 512                 udelay(1);
 513         } while (++i < MAX_DPLL_WAIT_TRIES);
 514
 515         if (i == MAX_DPLL_WAIT_TRIES) {
 516                 pr_err("MX5: clk_ahb_set_rate failed\n");
 517                 return -EINVAL;
 518         }
 519
 520         return 0;
 521 }
 522
 523 static unsigned long _clk_ahb_round_rate(struct clk *clk,
 524                                                 unsigned long rate)
 525 {
 526         u32 div;
 527         unsigned long parent_rate;
 528
 529         parent_rate = clk_get_rate(clk->parent);
 530
 531         div = parent_rate / rate;
 532         if (div > 8)
 533                 div = 8;
 534         else if (div == 0)
 535                 div++;
 536         return parent_rate / div;
 537 }
 538
 539
 540 static int _clk_max_enable(struct clk *clk)
 541 {
 542         u32 reg;
 543
 544         _clk_ccgr_enable(clk);
 545
 546         /* Handshake with MAX when LPM is entered. */
 547         reg = __raw_readl(MXC_CCM_CLPCR);
 548         if (cpu_is_mx51())
 549                 reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
 550         else if (cpu_is_mx53())
 551                 reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
 552         __raw_writel(reg, MXC_CCM_CLPCR);
 553
 554         return 0;
 555 }
 556
 557 static void _clk_max_disable(struct clk *clk)
 558 {
 559         u32 reg;
 560
 561         _clk_ccgr_disable_inwait(clk);
 562
 563         /* No Handshake with MAX when LPM is entered as its disabled. */
 564         reg = __raw_readl(MXC_CCM_CLPCR);
 565         if (cpu_is_mx51())
 566                 reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
 567         else if (cpu_is_mx53())
 568                 reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
 569         __raw_writel(reg, MXC_CCM_CLPCR);
 570 }
 571
 572 static unsigned long clk_ipg_get_rate(struct clk *clk)
 573 {
 574         u32 reg, div;
 575         unsigned long parent_rate;
 576
 577         parent_rate = clk_get_rate(clk->parent);
 578
 579         reg = __raw_readl(MXC_CCM_CBCDR);
 580         div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
 581                MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
 582
 583         return parent_rate / div;
 584 }
 585
 586 static unsigned long clk_ipg_per_get_rate(struct clk *clk)
 587 {
 588         u32 reg, prediv1, prediv2, podf;
 589         unsigned long parent_rate;
 590
 591         parent_rate = clk_get_rate(clk->parent);
 592
 593         if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
 594                 /* the main_bus_clk is the one before the DVFS engine */
 595                 reg = __raw_readl(MXC_CCM_CBCDR);
 596                 prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
 597                            MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
 598                 prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
 599                            MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
 600                 podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
 601                         MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
 602                 return parent_rate / (prediv1 * prediv2 * podf);
 603         } else if (clk->parent == &ipg_clk)
 604                 return parent_rate;
 605         else
 606                 BUG();
 607 }
 608
 609 static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
 610 {
 611         u32 reg;
 612
 613         reg = __raw_readl(MXC_CCM_CBCMR);
 614
 615         reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
 616         reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
 617
 618         if (parent == &ipg_clk)
 619                 reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
 620         else if (parent == &lp_apm_clk)
 621                 reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
 622         else if (parent != &main_bus_clk)
 623                 return -EINVAL;
 624
 625         __raw_writel(reg, MXC_CCM_CBCMR);
 626
 627         return 0;
 628 }
 629
 630 #define clk_nfc_set_parent      NULL
 631
 632 static unsigned long clk_nfc_get_rate(struct clk *clk)
 633 {
 634         unsigned long rate;
 635         u32 reg, div;
 636
 637         reg = __raw_readl(MXC_CCM_CBCDR);
 638         div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
 639                MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
 640         rate = clk_get_rate(clk->parent) / div;
 641         WARN_ON(rate == 0);
 642         return rate;
 643 }
 644
 645 static unsigned long clk_nfc_round_rate(struct clk *clk,
 646                                                 unsigned long rate)
 647 {
 648         u32 div;
 649         unsigned long parent_rate = clk_get_rate(clk->parent);
 650
 651         if (!rate)
 652                 return -EINVAL;
 653
 654         div = parent_rate / rate;
 655
 656         if (parent_rate % rate)
 657                 div++;
 658
 659         if (div > 8)
 660                 return -EINVAL;
 661
 662         return parent_rate / div;
 663
 664 }
 665
 666 static int clk_nfc_set_rate(struct clk *clk, unsigned long rate)
 667 {
 668         u32 reg, div;
 669
 670         div = clk_get_rate(clk->parent) / rate;
 671         if (div == 0)
 672                 div++;
 673         if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8))
 674                 return -EINVAL;
 675
 676         reg = __raw_readl(MXC_CCM_CBCDR);
 677         reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
 678         reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
 679         __raw_writel(reg, MXC_CCM_CBCDR);
 680
 681         while (__raw_readl(MXC_CCM_CDHIPR) &
 682                         MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
 683         }
 684
 685         return 0;
 686 }
 687
 688 static unsigned long get_high_reference_clock_rate(struct clk *clk)
 689 {
 690         return external_high_reference;
 691 }
 692
 693 static unsigned long get_low_reference_clock_rate(struct clk *clk)
 694 {
 695         return external_low_reference;
 696 }
 697
 698 static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
 699 {
 700         return oscillator_reference;
 701 }
 702
 703 static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
 704 {
 705         return ckih2_reference;
 706 }
 707
 708 static unsigned long clk_emi_slow_get_rate(struct clk *clk)
 709 {
 710         u32 reg, div;
 711
 712         reg = __raw_readl(MXC_CCM_CBCDR);
 713         div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
 714                MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
 715
 716         return clk_get_rate(clk->parent) / div;
 717 }
 718
 719 static unsigned long _clk_ddr_hf_get_rate(struct clk *clk)
 720 {
 721         unsigned long rate;
 722         u32 reg, div;
 723
 724         reg = __raw_readl(MXC_CCM_CBCDR);
 725         div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >>
 726                 MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1;
 727         rate = clk_get_rate(clk->parent) / div;
 728
 729         return rate;
 730 }
 731
 732 /* External high frequency clock */
 733 static struct clk ckih_clk = {
 734         .get_rate = get_high_reference_clock_rate,
 735 };
 736
 737 static struct clk ckih2_clk = {
 738         .get_rate = get_ckih2_reference_clock_rate,
 739 };
 740
 741 static struct clk osc_clk = {
 742         .get_rate = get_oscillator_reference_clock_rate,
 743 };
 744
 745 /* External low frequency (32kHz) clock */
 746 static struct clk ckil_clk = {
 747         .get_rate = get_low_reference_clock_rate,
 748 };
 749
 750 static struct clk pll1_main_clk = {
 751         .parent = &osc_clk,
 752         .get_rate = clk_pll_get_rate,
 753         .enable = _clk_pll_enable,
 754         .disable = _clk_pll_disable,
 755 };
 756
 757 /* Clock tree block diagram (WIP):
 758  *      CCM: Clock Controller Module
 759  *
 760  * PLL output -> |
 761  *               | CCM Switcher -> CCM_CLK_ROOT_GEN ->
 762  * PLL bypass -> |
 763  *
 764  */
 765
 766 /* PLL1 SW supplies to ARM core */
 767 static struct clk pll1_sw_clk = {
 768         .parent = &pll1_main_clk,
 769         .set_parent = _clk_pll1_sw_set_parent,
 770         .get_rate = clk_pll1_sw_get_rate,
 771 };
 772
 773 /* PLL2 SW supplies to AXI/AHB/IP buses */
 774 static struct clk pll2_sw_clk = {
 775         .parent = &osc_clk,
 776         .get_rate = clk_pll_get_rate,
 777         .set_rate = _clk_pll_set_rate,
 778         .set_parent = _clk_pll2_sw_set_parent,
 779         .enable = _clk_pll_enable,
 780         .disable = _clk_pll_disable,
 781 };
 782
 783 /* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
 784 static struct clk pll3_sw_clk = {
 785         .parent = &osc_clk,
 786         .set_rate = _clk_pll_set_rate,
 787         .get_rate = clk_pll_get_rate,
 788         .enable = _clk_pll_enable,
 789         .disable = _clk_pll_disable,
 790 };
 791
 792 /* PLL4 SW supplies to LVDS Display Bridge(LDB) */
 793 static struct clk mx53_pll4_sw_clk = {
 794         .parent = &osc_clk,
 795         .set_rate = _clk_pll_set_rate,
 796         .enable = _clk_pll_enable,
 797         .disable = _clk_pll_disable,
 798 };
 799
 800 /* Low-power Audio Playback Mode clock */
 801 static struct clk lp_apm_clk = {
 802         .parent = &osc_clk,
 803         .set_parent = _clk_lp_apm_set_parent,
 804 };
 805
 806 static struct clk periph_apm_clk = {
 807         .parent = &pll1_sw_clk,
 808         .set_parent = _clk_periph_apm_set_parent,
 809 };
 810
 811 static struct clk cpu_clk = {
 812         .parent = &pll1_sw_clk,
 813         .get_rate = clk_cpu_get_rate,
 814         .set_rate = clk_cpu_set_rate,
 815 };
 816
 817 static struct clk ahb_clk = {
 818         .parent = &main_bus_clk,
 819         .get_rate = clk_ahb_get_rate,
 820         .set_rate = _clk_ahb_set_rate,
 821         .round_rate = _clk_ahb_round_rate,
 822 };
 823
 824 static struct clk iim_clk = {
 825         .parent = &ipg_clk,
 826         .enable_reg = MXC_CCM_CCGR0,
 827         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
 828 };
 829
 830 /* Main IP interface clock for access to registers */
 831 static struct clk ipg_clk = {
 832         .parent = &ahb_clk,
 833         .get_rate = clk_ipg_get_rate,
 834 };
 835
 836 static struct clk ipg_perclk = {
 837         .parent = &lp_apm_clk,
 838         .get_rate = clk_ipg_per_get_rate,
 839         .set_parent = _clk_ipg_per_set_parent,
 840 };
 841
 842 static struct clk ahb_max_clk = {
 843         .parent = &ahb_clk,
 844         .enable_reg = MXC_CCM_CCGR0,
 845         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
 846         .enable = _clk_max_enable,
 847         .disable = _clk_max_disable,
 848 };
 849
 850 static struct clk aips_tz1_clk = {
 851         .parent = &ahb_clk,
 852         .secondary = &ahb_max_clk,
 853         .enable_reg = MXC_CCM_CCGR0,
 854         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
 855         .enable = _clk_ccgr_enable,
 856         .disable = _clk_ccgr_disable_inwait,
 857 };
 858
 859 static struct clk aips_tz2_clk = {
 860         .parent = &ahb_clk,
 861         .secondary = &ahb_max_clk,
 862         .enable_reg = MXC_CCM_CCGR0,
 863         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
 864         .enable = _clk_ccgr_enable,
 865         .disable = _clk_ccgr_disable_inwait,
 866 };
 867
 868 static struct clk gpt_32k_clk = {
 869         .id = 0,
 870         .parent = &ckil_clk,
 871 };
 872
 873 static struct clk dummy_clk = {
 874         .id = 0,
 875 };
 876
 877 static struct clk emi_slow_clk = {
 878         .parent = &pll2_sw_clk,
 879         .enable_reg = MXC_CCM_CCGR5,
 880         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
 881         .enable = _clk_ccgr_enable,
 882         .disable = _clk_ccgr_disable_inwait,
 883         .get_rate = clk_emi_slow_get_rate,
 884 };
 885
 886 static int clk_ipu_enable(struct clk *clk)
 887 {
 888         u32 reg;
 889
 890         _clk_ccgr_enable(clk);
 891
 892         /* Enable handshake with IPU when certain clock rates are changed */
 893         reg = __raw_readl(MXC_CCM_CCDR);
 894         reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
 895         __raw_writel(reg, MXC_CCM_CCDR);
 896
 897         /* Enable handshake with IPU when LPM is entered */
 898         reg = __raw_readl(MXC_CCM_CLPCR);
 899         reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
 900         __raw_writel(reg, MXC_CCM_CLPCR);
 901
 902         return 0;
 903 }
 904
 905 static void clk_ipu_disable(struct clk *clk)
 906 {
 907         u32 reg;
 908
 909         _clk_ccgr_disable(clk);
 910
 911         /* Disable handshake with IPU whe dividers are changed */
 912         reg = __raw_readl(MXC_CCM_CCDR);
 913         reg |= MXC_CCM_CCDR_IPU_HS_MASK;
 914         __raw_writel(reg, MXC_CCM_CCDR);
 915
 916         /* Disable handshake with IPU when LPM is entered */
 917         reg = __raw_readl(MXC_CCM_CLPCR);
 918         reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
 919         __raw_writel(reg, MXC_CCM_CLPCR);
 920 }
 921
 922 static struct clk ahbmux1_clk = {
 923         .parent = &ahb_clk,
 924         .secondary = &ahb_max_clk,
 925         .enable_reg = MXC_CCM_CCGR0,
 926         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
 927         .enable = _clk_ccgr_enable,
 928         .disable = _clk_ccgr_disable_inwait,
 929 };
 930
 931 static struct clk ipu_sec_clk = {
 932         .parent = &emi_fast_clk,
 933         .secondary = &ahbmux1_clk,
 934 };
 935
 936 static struct clk ddr_hf_clk = {
 937         .parent = &pll1_sw_clk,
 938         .get_rate = _clk_ddr_hf_get_rate,
 939 };
 940
 941 static struct clk ddr_clk = {
 942         .parent = &ddr_hf_clk,
 943 };
 944
 945 /* clock definitions for MIPI HSC unit which has been removed
 946  * from documentation, but not from hardware
 947  */
 948 static int _clk_hsc_enable(struct clk *clk)
 949 {
 950         u32 reg;
 951
 952         _clk_ccgr_enable(clk);
 953         /* Handshake with IPU when certain clock rates are changed. */
 954         reg = __raw_readl(MXC_CCM_CCDR);
 955         reg &= ~MXC_CCM_CCDR_HSC_HS_MASK;
 956         __raw_writel(reg, MXC_CCM_CCDR);
 957
 958         reg = __raw_readl(MXC_CCM_CLPCR);
 959         reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
 960         __raw_writel(reg, MXC_CCM_CLPCR);
 961
 962         return 0;
 963 }
 964
 965 static void _clk_hsc_disable(struct clk *clk)
 966 {
 967         u32 reg;
 968
 969         _clk_ccgr_disable(clk);
 970         /* No handshake with HSC as its not enabled. */
 971         reg = __raw_readl(MXC_CCM_CCDR);
 972         reg |= MXC_CCM_CCDR_HSC_HS_MASK;
 973         __raw_writel(reg, MXC_CCM_CCDR);
 974
 975         reg = __raw_readl(MXC_CCM_CLPCR);
 976         reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
 977         __raw_writel(reg, MXC_CCM_CLPCR);
 978 }
 979
 980 static struct clk mipi_hsp_clk = {
 981         .parent = &ipu_clk,
 982         .enable_reg = MXC_CCM_CCGR4,
 983         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
 984         .enable = _clk_hsc_enable,
 985         .disable = _clk_hsc_disable,
 986         .secondary = &mipi_hsc1_clk,
 987 };
 988
 989 #define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s)   \
 990         static struct clk name = {                      \
 991                 .id             = i,                    \
 992                 .enable_reg     = er,                   \
 993                 .enable_shift   = es,                   \
 994                 .get_rate       = pfx##_get_rate,       \
 995                 .set_rate       = pfx##_set_rate,       \
 996                 .round_rate     = pfx##_round_rate,     \
 997                 .set_parent     = pfx##_set_parent,     \
 998                 .enable         = _clk_ccgr_enable,     \
 999                 .disable        = _clk_ccgr_disable,    \
1000                 .parent         = p,                    \
1001                 .secondary      = s,                    \
1002         }
1003
1004 #define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s)    \
1005         static struct clk name = {                      \
1006                 .id             = i,                    \
1007                 .enable_reg     = er,                   \
1008                 .enable_shift   = es,                   \
1009                 .get_rate       = pfx##_get_rate,       \
1010                 .set_rate       = pfx##_set_rate,       \
1011                 .set_parent     = pfx##_set_parent,     \
1012                 .enable         = _clk_max_enable,      \
1013                 .disable        = _clk_max_disable,     \
1014                 .parent         = p,                    \
1015                 .secondary      = s,                    \
1016         }
1017
1018 #define CLK_GET_RATE(name, nr, bitsname)                                \
1019 static unsigned long clk_##name##_get_rate(struct clk *clk)             \
1020 {                                                                       \
1021         u32 reg, pred, podf;                                            \
1022                                                                         \
1023         reg = __raw_readl(MXC_CCM_CSCDR##nr);                           \
1024         pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK)   \
1025                 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET;    \
1026         podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK)   \
1027                 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET;    \
1028                                                                         \
1029         return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent),             \
1030                         (pred + 1) * (podf + 1));                       \
1031 }
1032
1033 #define CLK_SET_PARENT(name, nr, bitsname)                              \
1034 static int clk_##name##_set_parent(struct clk *clk, struct clk *parent) \
1035 {                                                                       \
1036         u32 reg, mux;                                                   \
1037                                                                         \
1038         mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk,              \
1039                         &pll3_sw_clk, &lp_apm_clk);                     \
1040         reg = __raw_readl(MXC_CCM_CSCMR##nr) &                          \
1041                 ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK;         \
1042         reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET;  \
1043         __raw_writel(reg, MXC_CCM_CSCMR##nr);                           \
1044                                                                         \
1045         return 0;                                                       \
1046 }
1047
1048 #define CLK_SET_RATE(name, nr, bitsname)                                \
1049 static int clk_##name##_set_rate(struct clk *clk, unsigned long rate)   \
1050 {                                                                       \
1051         u32 reg, div, parent_rate;                                      \
1052         u32 pre = 0, post = 0;                                          \
1053                                                                         \
1054         parent_rate = clk_get_rate(clk->parent);                        \
1055         div = parent_rate / rate;                                       \
1056                                                                         \
1057         if ((parent_rate / div) != rate)                                \
1058                 return -EINVAL;                                         \
1059                                                                         \
1060         __calc_pre_post_dividers(div, &pre, &post,                      \
1061                 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >>      \
1062                 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1,  \
1063                 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >>      \
1064                 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\
1065                                                                         \
1066         /* Set sdhc1 clock divider */                                   \
1067         reg = __raw_readl(MXC_CCM_CSCDR##nr) &                          \
1068                 ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK        \
1069                 | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK);      \
1070         reg |= (post - 1) <<                                            \
1071                 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET;       \
1072         reg |= (pre - 1) <<                                             \
1073                 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET;       \
1074         __raw_writel(reg, MXC_CCM_CSCDR##nr);                           \
1075                                                                         \
1076         return 0;                                                       \
1077 }
1078
1079 /* UART */
1080 CLK_GET_RATE(uart, 1, UART)
1081 CLK_SET_PARENT(uart, 1, UART)
1082
1083 static struct clk uart_root_clk = {
1084         .parent = &pll2_sw_clk,
1085         .get_rate = clk_uart_get_rate,
1086         .set_parent = clk_uart_set_parent,
1087 };
1088
1089 /* USBOH3 */
1090 CLK_GET_RATE(usboh3, 1, USBOH3)
1091 CLK_SET_PARENT(usboh3, 1, USBOH3)
1092
1093 static struct clk usboh3_clk = {
1094         .parent = &pll2_sw_clk,
1095         .get_rate = clk_usboh3_get_rate,
1096         .set_parent = clk_usboh3_set_parent,
1097         .enable = _clk_ccgr_enable,
1098         .disable = _clk_ccgr_disable,
1099         .enable_reg = MXC_CCM_CCGR2,
1100         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
1101 };
1102
1103 static struct clk usb_ahb_clk = {
1104         .parent = &ipg_clk,
1105         .enable = _clk_ccgr_enable,
1106         .disable = _clk_ccgr_disable,
1107         .enable_reg = MXC_CCM_CCGR2,
1108         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1109 };
1110
1111 static int clk_usb_phy1_set_parent(struct clk *clk, struct clk *parent)
1112 {
1113         u32 reg;
1114
1115         reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
1116
1117         if (parent == &pll3_sw_clk)
1118                 reg |= 1 << MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET;
1119
1120         __raw_writel(reg, MXC_CCM_CSCMR1);
1121
1122         return 0;
1123 }
1124
1125 static struct clk usb_phy1_clk = {
1126         .parent = &pll3_sw_clk,
1127         .set_parent = clk_usb_phy1_set_parent,
1128         .enable = _clk_ccgr_enable,
1129         .enable_reg = MXC_CCM_CCGR2,
1130         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
1131         .disable = _clk_ccgr_disable,
1132 };
1133
1134 /* eCSPI */
1135 CLK_GET_RATE(ecspi, 2, CSPI)
1136 CLK_SET_PARENT(ecspi, 1, CSPI)
1137
1138 static struct clk ecspi_main_clk = {
1139         .parent = &pll3_sw_clk,
1140         .get_rate = clk_ecspi_get_rate,
1141         .set_parent = clk_ecspi_set_parent,
1142 };
1143
1144 /* eSDHC */
1145 CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
1146 CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
1147 CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
1148
1149 /* mx51 specific */
1150 CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
1151 CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
1152 CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
1153
1154 static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
1155 {
1156         u32 reg;
1157
1158         reg = __raw_readl(MXC_CCM_CSCMR1);
1159         if (parent == &esdhc1_clk)
1160                 reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
1161         else if (parent == &esdhc2_clk)
1162                 reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
1163         else
1164                 return -EINVAL;
1165         __raw_writel(reg, MXC_CCM_CSCMR1);
1166
1167         return 0;
1168 }
1169
1170 static int clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
1171 {
1172         u32 reg;
1173
1174         reg = __raw_readl(MXC_CCM_CSCMR1);
1175         if (parent == &esdhc1_clk)
1176                 reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1177         else if (parent == &esdhc2_clk)
1178                 reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1179         else
1180                 return -EINVAL;
1181         __raw_writel(reg, MXC_CCM_CSCMR1);
1182
1183         return 0;
1184 }
1185
1186 /* mx53 specific */
1187 static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent)
1188 {
1189         u32 reg;
1190
1191         reg = __raw_readl(MXC_CCM_CSCMR1);
1192         if (parent == &esdhc1_clk)
1193                 reg &= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
1194         else if (parent == &esdhc3_mx53_clk)
1195                 reg |= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
1196         else
1197                 return -EINVAL;
1198         __raw_writel(reg, MXC_CCM_CSCMR1);
1199
1200         return 0;
1201 }
1202
1203 CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
1204 CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53)
1205 CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
1206
1207 static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent)
1208 {
1209         u32 reg;
1210
1211         reg = __raw_readl(MXC_CCM_CSCMR1);
1212         if (parent == &esdhc1_clk)
1213                 reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1214         else if (parent == &esdhc3_mx53_clk)
1215                 reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1216         else
1217                 return -EINVAL;
1218         __raw_writel(reg, MXC_CCM_CSCMR1);
1219
1220         return 0;
1221 }
1222
1223 #define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s)          \
1224         static struct clk name = {                                      \
1225                 .id             = i,                                    \
1226                 .enable_reg     = er,                                   \
1227                 .enable_shift   = es,                                   \
1228                 .get_rate       = gr,                                   \
1229                 .set_rate       = sr,                                   \
1230                 .enable         = e,                                    \
1231                 .disable        = d,                                    \
1232                 .parent         = p,                                    \
1233                 .secondary      = s,                                    \
1234         }
1235
1236 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)                     \
1237         DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
1238
1239 /* Shared peripheral bus arbiter */
1240 DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
1241         NULL,  NULL, &ipg_clk, NULL);
1242
1243 /* UART */
1244 DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
1245         NULL,  NULL, &ipg_clk, &aips_tz1_clk);
1246 DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
1247         NULL,  NULL, &ipg_clk, &aips_tz1_clk);
1248 DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
1249         NULL,  NULL, &ipg_clk, &spba_clk);
1250 DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
1251         NULL,  NULL, &uart_root_clk, &uart1_ipg_clk);
1252 DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
1253         NULL,  NULL, &uart_root_clk, &uart2_ipg_clk);
1254 DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
1255         NULL,  NULL, &uart_root_clk, &uart3_ipg_clk);
1256
1257 /* GPT */
1258 DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
1259         NULL,  NULL, &ipg_clk, NULL);
1260 DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
1261         NULL,  NULL, &ipg_clk, &gpt_ipg_clk);
1262
1263 DEFINE_CLOCK(pwm1_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG6_OFFSET,
1264         NULL, NULL, &ipg_clk, NULL);
1265 DEFINE_CLOCK(pwm2_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG8_OFFSET,
1266         NULL, NULL, &ipg_clk, NULL);
1267
1268 /* I2C */
1269 DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
1270         NULL, NULL, &ipg_clk, NULL);
1271 DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
1272         NULL, NULL, &ipg_clk, NULL);
1273 DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
1274         NULL, NULL, &ipg_clk, NULL);
1275
1276 /* FEC */
1277 DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
1278         NULL,  NULL, &ipg_clk, NULL);
1279
1280 /* NFC */
1281 DEFINE_CLOCK_CCGR(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
1282         clk_nfc, &emi_slow_clk, NULL);
1283
1284 /* SSI */
1285 DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET,
1286         NULL, NULL, &ipg_clk, NULL);
1287 DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET,
1288         NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk);
1289 DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
1290         NULL, NULL, &ipg_clk, NULL);
1291 DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
1292         NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
1293 DEFINE_CLOCK(ssi3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG12_OFFSET,
1294         NULL, NULL, &ipg_clk, NULL);
1295 DEFINE_CLOCK(ssi3_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG13_OFFSET,
1296         NULL, NULL, &pll3_sw_clk, &ssi3_ipg_clk);
1297
1298 /* eCSPI */
1299 DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
1300                 NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
1301                 &ipg_clk, &spba_clk);
1302 DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
1303                 NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
1304 DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
1305                 NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
1306                 &ipg_clk, &aips_tz2_clk);
1307 DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
1308                 NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
1309
1310 /* CSPI */
1311 DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
1312                 NULL, NULL, &ipg_clk, &aips_tz2_clk);
1313 DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
1314                 NULL, NULL, &ipg_clk, &cspi_ipg_clk);
1315
1316 /* SDMA */
1317 DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET,
1318                 NULL, NULL, &ahb_clk, NULL);
1319
1320 /* eSDHC */
1321 DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET,
1322         NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1323 DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
1324         clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
1325 DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
1326         NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1327 DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET,
1328         NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1329 DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET,
1330         NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1331
1332 /* mx51 specific */
1333 DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
1334         clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
1335
1336 static struct clk esdhc3_clk = {
1337         .id = 2,
1338         .parent = &esdhc1_clk,
1339         .set_parent = clk_esdhc3_set_parent,
1340         .enable_reg = MXC_CCM_CCGR3,
1341         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
1342         .enable  = _clk_max_enable,
1343         .disable = _clk_max_disable,
1344         .secondary = &esdhc3_ipg_clk,
1345 };
1346 static struct clk esdhc4_clk = {
1347         .id = 3,
1348         .parent = &esdhc1_clk,
1349         .set_parent = clk_esdhc4_set_parent,
1350         .enable_reg = MXC_CCM_CCGR3,
1351         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1352         .enable  = _clk_max_enable,
1353         .disable = _clk_max_disable,
1354         .secondary = &esdhc4_ipg_clk,
1355 };
1356
1357 /* mx53 specific */
1358 static struct clk esdhc2_mx53_clk = {
1359         .id = 2,
1360         .parent = &esdhc1_clk,
1361         .set_parent = clk_esdhc2_mx53_set_parent,
1362         .enable_reg = MXC_CCM_CCGR3,
1363         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1364         .enable  = _clk_max_enable,
1365         .disable = _clk_max_disable,
1366         .secondary = &esdhc3_ipg_clk,
1367 };
1368
1369 DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET,
1370         clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk);
1371
1372 static struct clk esdhc4_mx53_clk = {
1373         .id = 3,
1374         .parent = &esdhc1_clk,
1375         .set_parent = clk_esdhc4_mx53_set_parent,
1376         .enable_reg = MXC_CCM_CCGR3,
1377         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1378         .enable  = _clk_max_enable,
1379         .disable = _clk_max_disable,
1380         .secondary = &esdhc4_ipg_clk,
1381 };
1382
1383 DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
1384 DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
1385 DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
1386
1387 /* IPU */
1388 DEFINE_CLOCK_FULL(ipu_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG5_OFFSET,
1389         NULL,  NULL, clk_ipu_enable, clk_ipu_disable, &ahb_clk, &ipu_sec_clk);
1390
1391 DEFINE_CLOCK_FULL(emi_fast_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG7_OFFSET,
1392                 NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable_inwait,
1393                 &ddr_clk, NULL);
1394
1395 DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET,
1396                 NULL, NULL, &pll3_sw_clk, NULL);
1397 DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET,
1398                 NULL, NULL, &pll3_sw_clk, NULL);
1399
1400 #define _REGISTER_CLOCK(d, n, c) \
1401        { \
1402                 .dev_id = d, \
1403                 .con_id = n, \
1404                 .clk = &c,   \
1405        },
1406
1407 static struct clk_lookup mx51_lookups[] = {
1408         _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
1409         _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
1410         _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
1411         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
1412         _REGISTER_CLOCK("fec.0", NULL, fec_clk)
1413         _REGISTER_CLOCK("mxc_pwm.0", "pwm", pwm1_clk)
1414         _REGISTER_CLOCK("mxc_pwm.1", "pwm", pwm2_clk)
1415         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
1416         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
1417         _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
1418         _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
1419         _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk)
1420         _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk)
1421         _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
1422         _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk)
1423         _REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk)
1424         _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
1425         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
1426         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
1427         _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
1428         _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
1429         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
1430         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
1431         _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
1432         _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
1433         _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
1434         _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
1435         _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
1436         _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
1437         _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
1438         _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
1439         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
1440         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
1441         _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk)
1442         _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_clk)
1443         _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
1444         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
1445         _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
1446         _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
1447         _REGISTER_CLOCK(NULL, "mipi_hsp", mipi_hsp_clk)
1448         _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk)
1449         _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk)
1450         _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk)
1451 };
1452
1453 static struct clk_lookup mx53_lookups[] = {
1454         _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
1455         _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
1456         _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
1457         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
1458         _REGISTER_CLOCK("fec.0", NULL, fec_clk)
1459         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
1460         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
1461         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
1462         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
1463         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_mx53_clk)
1464         _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_mx53_clk)
1465         _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_mx53_clk)
1466         _REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk)
1467         _REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk)
1468         _REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk)
1469         _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
1470         _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
1471 };
1472
1473 static void clk_tree_init(void)
1474 {
1475         u32 reg;
1476
1477         ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
1478
1479         /*
1480          * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
1481          * 8MHz, its derived from lp_apm.
1482          *
1483          * FIXME: Verify if true for all boards
1484          */
1485         reg = __raw_readl(MXC_CCM_CBCDR);
1486         reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
1487         reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
1488         reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
1489         reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
1490         __raw_writel(reg, MXC_CCM_CBCDR);
1491 }
1492
1493 int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
1494                         unsigned long ckih1, unsigned long ckih2)
1495 {
1496         int i;
1497
1498         external_low_reference = ckil;
1499         external_high_reference = ckih1;
1500         ckih2_reference = ckih2;
1501         oscillator_reference = osc;
1502
1503         for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++)
1504                 clkdev_add(&mx51_lookups[i]);
1505
1506         clk_tree_init();
1507
1508         clk_enable(&cpu_clk);
1509         clk_enable(&main_bus_clk);
1510
1511         clk_enable(&iim_clk);
1512         mx51_revision();
1513         clk_disable(&iim_clk);
1514
1515         /* move usb_phy_clk to 24MHz */
1516         clk_set_parent(&usb_phy1_clk, &osc_clk);
1517
1518         /* set the usboh3_clk parent to pll2_sw_clk */
1519         clk_set_parent(&usboh3_clk, &pll2_sw_clk);
1520
1521         /* Set SDHC parents to be PLL2 */
1522         clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
1523         clk_set_parent(&esdhc2_clk, &pll2_sw_clk);
1524
1525         /* set SDHC root clock as 166.25MHZ*/
1526         clk_set_rate(&esdhc1_clk, 166250000);
1527         clk_set_rate(&esdhc2_clk, 166250000);
1528
1529         /* System timer */
1530         mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
1531                 MX51_MXC_INT_GPT);
1532         return 0;
1533 }
1534
1535 int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
1536                         unsigned long ckih1, unsigned long ckih2)
1537 {
1538         int i;
1539
1540         external_low_reference = ckil;
1541         external_high_reference = ckih1;
1542         ckih2_reference = ckih2;
1543         oscillator_reference = osc;
1544
1545         for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++)
1546                 clkdev_add(&mx53_lookups[i]);
1547
1548         clk_tree_init();
1549
1550         clk_set_parent(&uart_root_clk, &pll3_sw_clk);
1551         clk_enable(&cpu_clk);
1552         clk_enable(&main_bus_clk);
1553
1554         clk_enable(&iim_clk);
1555         mx53_revision();
1556         clk_disable(&iim_clk);
1557
1558         /* Set SDHC parents to be PLL2 */
1559         clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
1560         clk_set_parent(&esdhc3_mx53_clk, &pll2_sw_clk);
1561
1562         /* set SDHC root clock as 200MHZ*/
1563         clk_set_rate(&esdhc1_clk, 200000000);
1564         clk_set_rate(&esdhc3_mx53_clk, 200000000);
1565
1566         /* System timer */
1567         mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
1568                 MX53_INT_GPT);
1569         return 0;
1570 }