Fix pata imx resource
[pandora-kernel.git] / arch / arm / mach-mx5 / clock-mx51-mx53.c
1 /*
2  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
4  *
5  * The code contained herein is licensed under the GNU General Public
6  * License. You may obtain a copy of the GNU General Public License
7  * Version 2 or later at the following locations:
8  *
9  * http://www.opensource.org/licenses/gpl-license.html
10  * http://www.gnu.org/copyleft/gpl.html
11  */
12
13 #include <linux/mm.h>
14 #include <linux/delay.h>
15 #include <linux/clk.h>
16 #include <linux/io.h>
17 #include <linux/clkdev.h>
18
19 #include <asm/div64.h>
20
21 #include <mach/hardware.h>
22 #include <mach/common.h>
23 #include <mach/clock.h>
24
25 #include "crm_regs.h"
26
27 /* External clock values passed-in by the board code */
28 static unsigned long external_high_reference, external_low_reference;
29 static unsigned long oscillator_reference, ckih2_reference;
30
31 static struct clk osc_clk;
32 static struct clk pll1_main_clk;
33 static struct clk pll1_sw_clk;
34 static struct clk pll2_sw_clk;
35 static struct clk pll3_sw_clk;
36 static struct clk mx53_pll4_sw_clk;
37 static struct clk lp_apm_clk;
38 static struct clk periph_apm_clk;
39 static struct clk ahb_clk;
40 static struct clk ipg_clk;
41 static struct clk usboh3_clk;
42 static struct clk emi_fast_clk;
43 static struct clk ipu_clk;
44 static struct clk mipi_hsc1_clk;
45 static struct clk esdhc1_clk;
46 static struct clk esdhc2_clk;
47 static struct clk esdhc3_mx53_clk;
48
49 #define MAX_DPLL_WAIT_TRIES     1000 /* 1000 * udelay(1) = 1ms */
50
51 /* calculate best pre and post dividers to get the required divider */
52 static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post,
53         u32 max_pre, u32 max_post)
54 {
55         if (div >= max_pre * max_post) {
56                 *pre = max_pre;
57                 *post = max_post;
58         } else if (div >= max_pre) {
59                 u32 min_pre, temp_pre, old_err, err;
60                 min_pre = DIV_ROUND_UP(div, max_post);
61                 old_err = max_pre;
62                 for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) {
63                         err = div % temp_pre;
64                         if (err == 0) {
65                                 *pre = temp_pre;
66                                 break;
67                         }
68                         err = temp_pre - err;
69                         if (err < old_err) {
70                                 old_err = err;
71                                 *pre = temp_pre;
72                         }
73                 }
74                 *post = DIV_ROUND_UP(div, *pre);
75         } else {
76                 *pre = div;
77                 *post = 1;
78         }
79 }
80
81 static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
82 {
83         u32 reg = __raw_readl(clk->enable_reg);
84
85         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
86         reg |= mode << clk->enable_shift;
87
88         __raw_writel(reg, clk->enable_reg);
89 }
90
91 static int _clk_ccgr_enable(struct clk *clk)
92 {
93         _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON);
94         return 0;
95 }
96
97 static void _clk_ccgr_disable(struct clk *clk)
98 {
99         _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF);
100 }
101
102 static int _clk_ccgr_enable_inrun(struct clk *clk)
103 {
104         _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
105         return 0;
106 }
107
108 static void _clk_ccgr_disable_inwait(struct clk *clk)
109 {
110         _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
111 }
112
113 /*
114  * For the 4-to-1 muxed input clock
115  */
116 static inline u32 _get_mux(struct clk *parent, struct clk *m0,
117                            struct clk *m1, struct clk *m2, struct clk *m3)
118 {
119         if (parent == m0)
120                 return 0;
121         else if (parent == m1)
122                 return 1;
123         else if (parent == m2)
124                 return 2;
125         else if (parent == m3)
126                 return 3;
127         else
128                 BUG();
129
130         return -EINVAL;
131 }
132
133 static inline void __iomem *_mx51_get_pll_base(struct clk *pll)
134 {
135         if (pll == &pll1_main_clk)
136                 return MX51_DPLL1_BASE;
137         else if (pll == &pll2_sw_clk)
138                 return MX51_DPLL2_BASE;
139         else if (pll == &pll3_sw_clk)
140                 return MX51_DPLL3_BASE;
141         else
142                 BUG();
143
144         return NULL;
145 }
146
147 static inline void __iomem *_mx53_get_pll_base(struct clk *pll)
148 {
149         if (pll == &pll1_main_clk)
150                 return MX53_DPLL1_BASE;
151         else if (pll == &pll2_sw_clk)
152                 return MX53_DPLL2_BASE;
153         else if (pll == &pll3_sw_clk)
154                 return MX53_DPLL3_BASE;
155         else if (pll == &mx53_pll4_sw_clk)
156                 return MX53_DPLL4_BASE;
157         else
158                 BUG();
159
160         return NULL;
161 }
162
163 static inline void __iomem *_get_pll_base(struct clk *pll)
164 {
165         if (cpu_is_mx51())
166                 return _mx51_get_pll_base(pll);
167         else
168                 return _mx53_get_pll_base(pll);
169 }
170
171 static unsigned long clk_pll_get_rate(struct clk *clk)
172 {
173         long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
174         unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
175         void __iomem *pllbase;
176         s64 temp;
177         unsigned long parent_rate;
178
179         parent_rate = clk_get_rate(clk->parent);
180
181         pllbase = _get_pll_base(clk);
182
183         dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
184         pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
185         dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
186
187         if (pll_hfsm == 0) {
188                 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
189                 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
190                 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
191         } else {
192                 dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
193                 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
194                 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
195         }
196         pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
197         mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
198         mfi = (mfi <= 5) ? 5 : mfi;
199         mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
200         mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
201         /* Sign extend to 32-bits */
202         if (mfn >= 0x04000000) {
203                 mfn |= 0xFC000000;
204                 mfn_abs = -mfn;
205         }
206
207         ref_clk = 2 * parent_rate;
208         if (dbl != 0)
209                 ref_clk *= 2;
210
211         ref_clk /= (pdf + 1);
212         temp = (u64) ref_clk * mfn_abs;
213         do_div(temp, mfd + 1);
214         if (mfn < 0)
215                 temp = -temp;
216         temp = (ref_clk * mfi) + temp;
217
218         return temp;
219 }
220
221 static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
222 {
223         u32 reg;
224         void __iomem *pllbase;
225
226         long mfi, pdf, mfn, mfd = 999999;
227         s64 temp64;
228         unsigned long quad_parent_rate;
229         unsigned long pll_hfsm, dp_ctl;
230         unsigned long parent_rate;
231
232         parent_rate = clk_get_rate(clk->parent);
233
234         pllbase = _get_pll_base(clk);
235
236         quad_parent_rate = 4 * parent_rate;
237         pdf = mfi = -1;
238         while (++pdf < 16 && mfi < 5)
239                 mfi = rate * (pdf+1) / quad_parent_rate;
240         if (mfi > 15)
241                 return -EINVAL;
242         pdf--;
243
244         temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
245         do_div(temp64, quad_parent_rate/1000000);
246         mfn = (long)temp64;
247
248         dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
249         /* use dpdck0_2 */
250         __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
251         pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
252         if (pll_hfsm == 0) {
253                 reg = mfi << 4 | pdf;
254                 __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
255                 __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
256                 __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
257         } else {
258                 reg = mfi << 4 | pdf;
259                 __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
260                 __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
261                 __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
262         }
263
264         return 0;
265 }
266
267 static int _clk_pll_enable(struct clk *clk)
268 {
269         u32 reg;
270         void __iomem *pllbase;
271         int i = 0;
272
273         pllbase = _get_pll_base(clk);
274         reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
275         __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
276
277         /* Wait for lock */
278         do {
279                 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
280                 if (reg & MXC_PLL_DP_CTL_LRF)
281                         break;
282
283                 udelay(1);
284         } while (++i < MAX_DPLL_WAIT_TRIES);
285
286         if (i == MAX_DPLL_WAIT_TRIES) {
287                 pr_err("MX5: pll locking failed\n");
288                 return -EINVAL;
289         }
290
291         return 0;
292 }
293
294 static void _clk_pll_disable(struct clk *clk)
295 {
296         u32 reg;
297         void __iomem *pllbase;
298
299         pllbase = _get_pll_base(clk);
300         reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
301         __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
302 }
303
304 static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
305 {
306         u32 reg, step;
307
308         reg = __raw_readl(MXC_CCM_CCSR);
309
310         /* When switching from pll_main_clk to a bypass clock, first select a
311          * multiplexed clock in 'step_sel', then shift the glitchless mux
312          * 'pll1_sw_clk_sel'.
313          *
314          * When switching back, do it in reverse order
315          */
316         if (parent == &pll1_main_clk) {
317                 /* Switch to pll1_main_clk */
318                 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
319                 __raw_writel(reg, MXC_CCM_CCSR);
320                 /* step_clk mux switched to lp_apm, to save power. */
321                 reg = __raw_readl(MXC_CCM_CCSR);
322                 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
323                 reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM <<
324                                 MXC_CCM_CCSR_STEP_SEL_OFFSET);
325         } else {
326                 if (parent == &lp_apm_clk) {
327                         step = MXC_CCM_CCSR_STEP_SEL_LP_APM;
328                 } else  if (parent == &pll2_sw_clk) {
329                         step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED;
330                 } else  if (parent == &pll3_sw_clk) {
331                         step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED;
332                 } else
333                         return -EINVAL;
334
335                 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
336                 reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET);
337
338                 __raw_writel(reg, MXC_CCM_CCSR);
339                 /* Switch to step_clk */
340                 reg = __raw_readl(MXC_CCM_CCSR);
341                 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
342         }
343         __raw_writel(reg, MXC_CCM_CCSR);
344         return 0;
345 }
346
347 static unsigned long clk_pll1_sw_get_rate(struct clk *clk)
348 {
349         u32 reg, div;
350         unsigned long parent_rate;
351
352         parent_rate = clk_get_rate(clk->parent);
353
354         reg = __raw_readl(MXC_CCM_CCSR);
355
356         if (clk->parent == &pll2_sw_clk) {
357                 div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
358                        MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
359         } else if (clk->parent == &pll3_sw_clk) {
360                 div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
361                        MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
362         } else
363                 div = 1;
364         return parent_rate / div;
365 }
366
367 static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
368 {
369         u32 reg;
370
371         reg = __raw_readl(MXC_CCM_CCSR);
372
373         if (parent == &pll2_sw_clk)
374                 reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
375         else
376                 reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
377
378         __raw_writel(reg, MXC_CCM_CCSR);
379         return 0;
380 }
381
382 static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
383 {
384         u32 reg;
385
386         if (parent == &osc_clk)
387                 reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
388         else
389                 return -EINVAL;
390
391         __raw_writel(reg, MXC_CCM_CCSR);
392
393         return 0;
394 }
395
396 static unsigned long clk_cpu_get_rate(struct clk *clk)
397 {
398         u32 cacrr, div;
399         unsigned long parent_rate;
400
401         parent_rate = clk_get_rate(clk->parent);
402         cacrr = __raw_readl(MXC_CCM_CACRR);
403         div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
404
405         return parent_rate / div;
406 }
407
408 static int clk_cpu_set_rate(struct clk *clk, unsigned long rate)
409 {
410         u32 reg, cpu_podf;
411         unsigned long parent_rate;
412
413         parent_rate = clk_get_rate(clk->parent);
414         cpu_podf = parent_rate / rate - 1;
415         /* use post divider to change freq */
416         reg = __raw_readl(MXC_CCM_CACRR);
417         reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
418         reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;
419         __raw_writel(reg, MXC_CCM_CACRR);
420
421         return 0;
422 }
423
424 static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
425 {
426         u32 reg, mux;
427         int i = 0;
428
429         mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
430
431         reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
432         reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
433         __raw_writel(reg, MXC_CCM_CBCMR);
434
435         /* Wait for lock */
436         do {
437                 reg = __raw_readl(MXC_CCM_CDHIPR);
438                 if (!(reg &  MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY))
439                         break;
440
441                 udelay(1);
442         } while (++i < MAX_DPLL_WAIT_TRIES);
443
444         if (i == MAX_DPLL_WAIT_TRIES) {
445                 pr_err("MX5: Set parent for periph_apm clock failed\n");
446                 return -EINVAL;
447         }
448
449         return 0;
450 }
451
452 static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
453 {
454         u32 reg;
455
456         reg = __raw_readl(MXC_CCM_CBCDR);
457
458         if (parent == &pll2_sw_clk)
459                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
460         else if (parent == &periph_apm_clk)
461                 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
462         else
463                 return -EINVAL;
464
465         __raw_writel(reg, MXC_CCM_CBCDR);
466
467         return 0;
468 }
469
470 static struct clk main_bus_clk = {
471         .parent = &pll2_sw_clk,
472         .set_parent = _clk_main_bus_set_parent,
473 };
474
475 static unsigned long clk_ahb_get_rate(struct clk *clk)
476 {
477         u32 reg, div;
478         unsigned long parent_rate;
479
480         parent_rate = clk_get_rate(clk->parent);
481
482         reg = __raw_readl(MXC_CCM_CBCDR);
483         div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
484                MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
485         return parent_rate / div;
486 }
487
488
489 static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
490 {
491         u32 reg, div;
492         unsigned long parent_rate;
493         int i = 0;
494
495         parent_rate = clk_get_rate(clk->parent);
496
497         div = parent_rate / rate;
498         if (div > 8 || div < 1 || ((parent_rate / div) != rate))
499                 return -EINVAL;
500
501         reg = __raw_readl(MXC_CCM_CBCDR);
502         reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
503         reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
504         __raw_writel(reg, MXC_CCM_CBCDR);
505
506         /* Wait for lock */
507         do {
508                 reg = __raw_readl(MXC_CCM_CDHIPR);
509                 if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY))
510                         break;
511
512                 udelay(1);
513         } while (++i < MAX_DPLL_WAIT_TRIES);
514
515         if (i == MAX_DPLL_WAIT_TRIES) {
516                 pr_err("MX5: clk_ahb_set_rate failed\n");
517                 return -EINVAL;
518         }
519
520         return 0;
521 }
522
523 static unsigned long _clk_ahb_round_rate(struct clk *clk,
524                                                 unsigned long rate)
525 {
526         u32 div;
527         unsigned long parent_rate;
528
529         parent_rate = clk_get_rate(clk->parent);
530
531         div = parent_rate / rate;
532         if (div > 8)
533                 div = 8;
534         else if (div == 0)
535                 div++;
536         return parent_rate / div;
537 }
538
539
540 static int _clk_max_enable(struct clk *clk)
541 {
542         u32 reg;
543
544         _clk_ccgr_enable(clk);
545
546         /* Handshake with MAX when LPM is entered. */
547         reg = __raw_readl(MXC_CCM_CLPCR);
548         if (cpu_is_mx51())
549                 reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
550         else if (cpu_is_mx53())
551                 reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
552         __raw_writel(reg, MXC_CCM_CLPCR);
553
554         return 0;
555 }
556
557 static void _clk_max_disable(struct clk *clk)
558 {
559         u32 reg;
560
561         _clk_ccgr_disable_inwait(clk);
562
563         /* No Handshake with MAX when LPM is entered as its disabled. */
564         reg = __raw_readl(MXC_CCM_CLPCR);
565         if (cpu_is_mx51())
566                 reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
567         else if (cpu_is_mx53())
568                 reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
569         __raw_writel(reg, MXC_CCM_CLPCR);
570 }
571
572 static unsigned long clk_ipg_get_rate(struct clk *clk)
573 {
574         u32 reg, div;
575         unsigned long parent_rate;
576
577         parent_rate = clk_get_rate(clk->parent);
578
579         reg = __raw_readl(MXC_CCM_CBCDR);
580         div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
581                MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
582
583         return parent_rate / div;
584 }
585
586 static unsigned long clk_ipg_per_get_rate(struct clk *clk)
587 {
588         u32 reg, prediv1, prediv2, podf;
589         unsigned long parent_rate;
590
591         parent_rate = clk_get_rate(clk->parent);
592
593         if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
594                 /* the main_bus_clk is the one before the DVFS engine */
595                 reg = __raw_readl(MXC_CCM_CBCDR);
596                 prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
597                            MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
598                 prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
599                            MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
600                 podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
601                         MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
602                 return parent_rate / (prediv1 * prediv2 * podf);
603         } else if (clk->parent == &ipg_clk)
604                 return parent_rate;
605         else
606                 BUG();
607 }
608
609 static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
610 {
611         u32 reg;
612
613         reg = __raw_readl(MXC_CCM_CBCMR);
614
615         reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
616         reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
617
618         if (parent == &ipg_clk)
619                 reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
620         else if (parent == &lp_apm_clk)
621                 reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
622         else if (parent != &main_bus_clk)
623                 return -EINVAL;
624
625         __raw_writel(reg, MXC_CCM_CBCMR);
626
627         return 0;
628 }
629
630 #define clk_nfc_set_parent      NULL
631
632 static unsigned long clk_nfc_get_rate(struct clk *clk)
633 {
634         unsigned long rate;
635         u32 reg, div;
636
637         reg = __raw_readl(MXC_CCM_CBCDR);
638         div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
639                MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
640         rate = clk_get_rate(clk->parent) / div;
641         WARN_ON(rate == 0);
642         return rate;
643 }
644
645 static unsigned long clk_nfc_round_rate(struct clk *clk,
646                                                 unsigned long rate)
647 {
648         u32 div;
649         unsigned long parent_rate = clk_get_rate(clk->parent);
650
651         if (!rate)
652                 return -EINVAL;
653
654         div = parent_rate / rate;
655
656         if (parent_rate % rate)
657                 div++;
658
659         if (div > 8)
660                 return -EINVAL;
661
662         return parent_rate / div;
663
664 }
665
666 static int clk_nfc_set_rate(struct clk *clk, unsigned long rate)
667 {
668         u32 reg, div;
669
670         div = clk_get_rate(clk->parent) / rate;
671         if (div == 0)
672                 div++;
673         if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8))
674                 return -EINVAL;
675
676         reg = __raw_readl(MXC_CCM_CBCDR);
677         reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
678         reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
679         __raw_writel(reg, MXC_CCM_CBCDR);
680
681         while (__raw_readl(MXC_CCM_CDHIPR) &
682                         MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
683         }
684
685         return 0;
686 }
687
688 static unsigned long get_high_reference_clock_rate(struct clk *clk)
689 {
690         return external_high_reference;
691 }
692
693 static unsigned long get_low_reference_clock_rate(struct clk *clk)
694 {
695         return external_low_reference;
696 }
697
698 static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
699 {
700         return oscillator_reference;
701 }
702
703 static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
704 {
705         return ckih2_reference;
706 }
707
708 static unsigned long clk_emi_slow_get_rate(struct clk *clk)
709 {
710         u32 reg, div;
711
712         reg = __raw_readl(MXC_CCM_CBCDR);
713         div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
714                MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
715
716         return clk_get_rate(clk->parent) / div;
717 }
718
719 static unsigned long _clk_ddr_hf_get_rate(struct clk *clk)
720 {
721         unsigned long rate;
722         u32 reg, div;
723
724         reg = __raw_readl(MXC_CCM_CBCDR);
725         div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >>
726                 MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1;
727         rate = clk_get_rate(clk->parent) / div;
728
729         return rate;
730 }
731
732 /* External high frequency clock */
733 static struct clk ckih_clk = {
734         .get_rate = get_high_reference_clock_rate,
735 };
736
737 static struct clk ckih2_clk = {
738         .get_rate = get_ckih2_reference_clock_rate,
739 };
740
741 static struct clk osc_clk = {
742         .get_rate = get_oscillator_reference_clock_rate,
743 };
744
745 /* External low frequency (32kHz) clock */
746 static struct clk ckil_clk = {
747         .get_rate = get_low_reference_clock_rate,
748 };
749
750 static struct clk pll1_main_clk = {
751         .parent = &osc_clk,
752         .get_rate = clk_pll_get_rate,
753         .enable = _clk_pll_enable,
754         .disable = _clk_pll_disable,
755 };
756
757 /* Clock tree block diagram (WIP):
758  *      CCM: Clock Controller Module
759  *
760  * PLL output -> |
761  *               | CCM Switcher -> CCM_CLK_ROOT_GEN ->
762  * PLL bypass -> |
763  *
764  */
765
766 /* PLL1 SW supplies to ARM core */
767 static struct clk pll1_sw_clk = {
768         .parent = &pll1_main_clk,
769         .set_parent = _clk_pll1_sw_set_parent,
770         .get_rate = clk_pll1_sw_get_rate,
771 };
772
773 /* PLL2 SW supplies to AXI/AHB/IP buses */
774 static struct clk pll2_sw_clk = {
775         .parent = &osc_clk,
776         .get_rate = clk_pll_get_rate,
777         .set_rate = _clk_pll_set_rate,
778         .set_parent = _clk_pll2_sw_set_parent,
779         .enable = _clk_pll_enable,
780         .disable = _clk_pll_disable,
781 };
782
783 /* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
784 static struct clk pll3_sw_clk = {
785         .parent = &osc_clk,
786         .set_rate = _clk_pll_set_rate,
787         .get_rate = clk_pll_get_rate,
788         .enable = _clk_pll_enable,
789         .disable = _clk_pll_disable,
790 };
791
792 /* PLL4 SW supplies to LVDS Display Bridge(LDB) */
793 static struct clk mx53_pll4_sw_clk = {
794         .parent = &osc_clk,
795         .set_rate = _clk_pll_set_rate,
796         .enable = _clk_pll_enable,
797         .disable = _clk_pll_disable,
798 };
799
800 /* Low-power Audio Playback Mode clock */
801 static struct clk lp_apm_clk = {
802         .parent = &osc_clk,
803         .set_parent = _clk_lp_apm_set_parent,
804 };
805
806 static struct clk periph_apm_clk = {
807         .parent = &pll1_sw_clk,
808         .set_parent = _clk_periph_apm_set_parent,
809 };
810
811 static struct clk cpu_clk = {
812         .parent = &pll1_sw_clk,
813         .get_rate = clk_cpu_get_rate,
814         .set_rate = clk_cpu_set_rate,
815 };
816
817 static struct clk ahb_clk = {
818         .parent = &main_bus_clk,
819         .get_rate = clk_ahb_get_rate,
820         .set_rate = _clk_ahb_set_rate,
821         .round_rate = _clk_ahb_round_rate,
822 };
823
824 static struct clk iim_clk = {
825         .parent = &ipg_clk,
826         .enable_reg = MXC_CCM_CCGR0,
827         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
828 };
829
830 /* Main IP interface clock for access to registers */
831 static struct clk ipg_clk = {
832         .parent = &ahb_clk,
833         .get_rate = clk_ipg_get_rate,
834 };
835
836 static struct clk ipg_perclk = {
837         .parent = &lp_apm_clk,
838         .get_rate = clk_ipg_per_get_rate,
839         .set_parent = _clk_ipg_per_set_parent,
840 };
841
842 static struct clk ahb_max_clk = {
843         .parent = &ahb_clk,
844         .enable_reg = MXC_CCM_CCGR0,
845         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
846         .enable = _clk_max_enable,
847         .disable = _clk_max_disable,
848 };
849
850 static struct clk aips_tz1_clk = {
851         .parent = &ahb_clk,
852         .secondary = &ahb_max_clk,
853         .enable_reg = MXC_CCM_CCGR0,
854         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
855         .enable = _clk_ccgr_enable,
856         .disable = _clk_ccgr_disable_inwait,
857 };
858
859 static struct clk aips_tz2_clk = {
860         .parent = &ahb_clk,
861         .secondary = &ahb_max_clk,
862         .enable_reg = MXC_CCM_CCGR0,
863         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
864         .enable = _clk_ccgr_enable,
865         .disable = _clk_ccgr_disable_inwait,
866 };
867
868 static struct clk gpc_dvfs_clk = {
869         .enable_reg = MXC_CCM_CCGR5,
870         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
871         .enable = _clk_ccgr_enable,
872         .disable = _clk_ccgr_disable,
873 };
874
875 static struct clk gpt_32k_clk = {
876         .id = 0,
877         .parent = &ckil_clk,
878 };
879
880 static struct clk dummy_clk = {
881         .id = 0,
882 };
883
884 static struct clk emi_slow_clk = {
885         .parent = &pll2_sw_clk,
886         .enable_reg = MXC_CCM_CCGR5,
887         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
888         .enable = _clk_ccgr_enable,
889         .disable = _clk_ccgr_disable_inwait,
890         .get_rate = clk_emi_slow_get_rate,
891 };
892
893 static int clk_ipu_enable(struct clk *clk)
894 {
895         u32 reg;
896
897         _clk_ccgr_enable(clk);
898
899         /* Enable handshake with IPU when certain clock rates are changed */
900         reg = __raw_readl(MXC_CCM_CCDR);
901         reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
902         __raw_writel(reg, MXC_CCM_CCDR);
903
904         /* Enable handshake with IPU when LPM is entered */
905         reg = __raw_readl(MXC_CCM_CLPCR);
906         reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
907         __raw_writel(reg, MXC_CCM_CLPCR);
908
909         return 0;
910 }
911
912 static void clk_ipu_disable(struct clk *clk)
913 {
914         u32 reg;
915
916         _clk_ccgr_disable(clk);
917
918         /* Disable handshake with IPU whe dividers are changed */
919         reg = __raw_readl(MXC_CCM_CCDR);
920         reg |= MXC_CCM_CCDR_IPU_HS_MASK;
921         __raw_writel(reg, MXC_CCM_CCDR);
922
923         /* Disable handshake with IPU when LPM is entered */
924         reg = __raw_readl(MXC_CCM_CLPCR);
925         reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
926         __raw_writel(reg, MXC_CCM_CLPCR);
927 }
928
929 static struct clk ahbmux1_clk = {
930         .parent = &ahb_clk,
931         .secondary = &ahb_max_clk,
932         .enable_reg = MXC_CCM_CCGR0,
933         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
934         .enable = _clk_ccgr_enable,
935         .disable = _clk_ccgr_disable_inwait,
936 };
937
938 static struct clk ipu_sec_clk = {
939         .parent = &emi_fast_clk,
940         .secondary = &ahbmux1_clk,
941 };
942
943 static struct clk ddr_hf_clk = {
944         .parent = &pll1_sw_clk,
945         .get_rate = _clk_ddr_hf_get_rate,
946 };
947
948 static struct clk ddr_clk = {
949         .parent = &ddr_hf_clk,
950 };
951
952 /* clock definitions for MIPI HSC unit which has been removed
953  * from documentation, but not from hardware
954  */
955 static int _clk_hsc_enable(struct clk *clk)
956 {
957         u32 reg;
958
959         _clk_ccgr_enable(clk);
960         /* Handshake with IPU when certain clock rates are changed. */
961         reg = __raw_readl(MXC_CCM_CCDR);
962         reg &= ~MXC_CCM_CCDR_HSC_HS_MASK;
963         __raw_writel(reg, MXC_CCM_CCDR);
964
965         reg = __raw_readl(MXC_CCM_CLPCR);
966         reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
967         __raw_writel(reg, MXC_CCM_CLPCR);
968
969         return 0;
970 }
971
972 static void _clk_hsc_disable(struct clk *clk)
973 {
974         u32 reg;
975
976         _clk_ccgr_disable(clk);
977         /* No handshake with HSC as its not enabled. */
978         reg = __raw_readl(MXC_CCM_CCDR);
979         reg |= MXC_CCM_CCDR_HSC_HS_MASK;
980         __raw_writel(reg, MXC_CCM_CCDR);
981
982         reg = __raw_readl(MXC_CCM_CLPCR);
983         reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
984         __raw_writel(reg, MXC_CCM_CLPCR);
985 }
986
987 static struct clk mipi_hsp_clk = {
988         .parent = &ipu_clk,
989         .enable_reg = MXC_CCM_CCGR4,
990         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
991         .enable = _clk_hsc_enable,
992         .disable = _clk_hsc_disable,
993         .secondary = &mipi_hsc1_clk,
994 };
995
996 #define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s)   \
997         static struct clk name = {                      \
998                 .id             = i,                    \
999                 .enable_reg     = er,                   \
1000                 .enable_shift   = es,                   \
1001                 .get_rate       = pfx##_get_rate,       \
1002                 .set_rate       = pfx##_set_rate,       \
1003                 .round_rate     = pfx##_round_rate,     \
1004                 .set_parent     = pfx##_set_parent,     \
1005                 .enable         = _clk_ccgr_enable,     \
1006                 .disable        = _clk_ccgr_disable,    \
1007                 .parent         = p,                    \
1008                 .secondary      = s,                    \
1009         }
1010
1011 #define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s)    \
1012         static struct clk name = {                      \
1013                 .id             = i,                    \
1014                 .enable_reg     = er,                   \
1015                 .enable_shift   = es,                   \
1016                 .get_rate       = pfx##_get_rate,       \
1017                 .set_rate       = pfx##_set_rate,       \
1018                 .set_parent     = pfx##_set_parent,     \
1019                 .enable         = _clk_max_enable,      \
1020                 .disable        = _clk_max_disable,     \
1021                 .parent         = p,                    \
1022                 .secondary      = s,                    \
1023         }
1024
1025 #define CLK_GET_RATE(name, nr, bitsname)                                \
1026 static unsigned long clk_##name##_get_rate(struct clk *clk)             \
1027 {                                                                       \
1028         u32 reg, pred, podf;                                            \
1029                                                                         \
1030         reg = __raw_readl(MXC_CCM_CSCDR##nr);                           \
1031         pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK)   \
1032                 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET;    \
1033         podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK)   \
1034                 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET;    \
1035                                                                         \
1036         return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent),             \
1037                         (pred + 1) * (podf + 1));                       \
1038 }
1039
1040 #define CLK_SET_PARENT(name, nr, bitsname)                              \
1041 static int clk_##name##_set_parent(struct clk *clk, struct clk *parent) \
1042 {                                                                       \
1043         u32 reg, mux;                                                   \
1044                                                                         \
1045         mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk,              \
1046                         &pll3_sw_clk, &lp_apm_clk);                     \
1047         reg = __raw_readl(MXC_CCM_CSCMR##nr) &                          \
1048                 ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK;         \
1049         reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET;  \
1050         __raw_writel(reg, MXC_CCM_CSCMR##nr);                           \
1051                                                                         \
1052         return 0;                                                       \
1053 }
1054
1055 #define CLK_SET_RATE(name, nr, bitsname)                                \
1056 static int clk_##name##_set_rate(struct clk *clk, unsigned long rate)   \
1057 {                                                                       \
1058         u32 reg, div, parent_rate;                                      \
1059         u32 pre = 0, post = 0;                                          \
1060                                                                         \
1061         parent_rate = clk_get_rate(clk->parent);                        \
1062         div = parent_rate / rate;                                       \
1063                                                                         \
1064         if ((parent_rate / div) != rate)                                \
1065                 return -EINVAL;                                         \
1066                                                                         \
1067         __calc_pre_post_dividers(div, &pre, &post,                      \
1068                 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >>      \
1069                 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1,  \
1070                 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >>      \
1071                 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\
1072                                                                         \
1073         /* Set sdhc1 clock divider */                                   \
1074         reg = __raw_readl(MXC_CCM_CSCDR##nr) &                          \
1075                 ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK        \
1076                 | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK);      \
1077         reg |= (post - 1) <<                                            \
1078                 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET;       \
1079         reg |= (pre - 1) <<                                             \
1080                 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET;       \
1081         __raw_writel(reg, MXC_CCM_CSCDR##nr);                           \
1082                                                                         \
1083         return 0;                                                       \
1084 }
1085
1086 /* UART */
1087 CLK_GET_RATE(uart, 1, UART)
1088 CLK_SET_PARENT(uart, 1, UART)
1089
1090 static struct clk uart_root_clk = {
1091         .parent = &pll2_sw_clk,
1092         .get_rate = clk_uart_get_rate,
1093         .set_parent = clk_uart_set_parent,
1094 };
1095
1096 /* USBOH3 */
1097 CLK_GET_RATE(usboh3, 1, USBOH3)
1098 CLK_SET_PARENT(usboh3, 1, USBOH3)
1099
1100 static struct clk usboh3_clk = {
1101         .parent = &pll2_sw_clk,
1102         .get_rate = clk_usboh3_get_rate,
1103         .set_parent = clk_usboh3_set_parent,
1104         .enable = _clk_ccgr_enable,
1105         .disable = _clk_ccgr_disable,
1106         .enable_reg = MXC_CCM_CCGR2,
1107         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
1108 };
1109
1110 static struct clk usb_ahb_clk = {
1111         .parent = &ipg_clk,
1112         .enable = _clk_ccgr_enable,
1113         .disable = _clk_ccgr_disable,
1114         .enable_reg = MXC_CCM_CCGR2,
1115         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1116 };
1117
1118 static int clk_usb_phy1_set_parent(struct clk *clk, struct clk *parent)
1119 {
1120         u32 reg;
1121
1122         reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
1123
1124         if (parent == &pll3_sw_clk)
1125                 reg |= 1 << MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET;
1126
1127         __raw_writel(reg, MXC_CCM_CSCMR1);
1128
1129         return 0;
1130 }
1131
1132 static struct clk usb_phy1_clk = {
1133         .parent = &pll3_sw_clk,
1134         .set_parent = clk_usb_phy1_set_parent,
1135         .enable = _clk_ccgr_enable,
1136         .enable_reg = MXC_CCM_CCGR2,
1137         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
1138         .disable = _clk_ccgr_disable,
1139 };
1140
1141 /* eCSPI */
1142 CLK_GET_RATE(ecspi, 2, CSPI)
1143 CLK_SET_PARENT(ecspi, 1, CSPI)
1144
1145 static struct clk ecspi_main_clk = {
1146         .parent = &pll3_sw_clk,
1147         .get_rate = clk_ecspi_get_rate,
1148         .set_parent = clk_ecspi_set_parent,
1149 };
1150
1151 /* eSDHC */
1152 CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
1153 CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
1154 CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
1155
1156 /* mx51 specific */
1157 CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
1158 CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
1159 CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
1160
1161 static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
1162 {
1163         u32 reg;
1164
1165         reg = __raw_readl(MXC_CCM_CSCMR1);
1166         if (parent == &esdhc1_clk)
1167                 reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
1168         else if (parent == &esdhc2_clk)
1169                 reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
1170         else
1171                 return -EINVAL;
1172         __raw_writel(reg, MXC_CCM_CSCMR1);
1173
1174         return 0;
1175 }
1176
1177 static int clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
1178 {
1179         u32 reg;
1180
1181         reg = __raw_readl(MXC_CCM_CSCMR1);
1182         if (parent == &esdhc1_clk)
1183                 reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1184         else if (parent == &esdhc2_clk)
1185                 reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1186         else
1187                 return -EINVAL;
1188         __raw_writel(reg, MXC_CCM_CSCMR1);
1189
1190         return 0;
1191 }
1192
1193 /* mx53 specific */
1194 static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent)
1195 {
1196         u32 reg;
1197
1198         reg = __raw_readl(MXC_CCM_CSCMR1);
1199         if (parent == &esdhc1_clk)
1200                 reg &= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
1201         else if (parent == &esdhc3_mx53_clk)
1202                 reg |= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
1203         else
1204                 return -EINVAL;
1205         __raw_writel(reg, MXC_CCM_CSCMR1);
1206
1207         return 0;
1208 }
1209
1210 CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
1211 CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53)
1212 CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
1213
1214 static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent)
1215 {
1216         u32 reg;
1217
1218         reg = __raw_readl(MXC_CCM_CSCMR1);
1219         if (parent == &esdhc1_clk)
1220                 reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1221         else if (parent == &esdhc3_mx53_clk)
1222                 reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1223         else
1224                 return -EINVAL;
1225         __raw_writel(reg, MXC_CCM_CSCMR1);
1226
1227         return 0;
1228 }
1229
1230 #define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s)          \
1231         static struct clk name = {                                      \
1232                 .id             = i,                                    \
1233                 .enable_reg     = er,                                   \
1234                 .enable_shift   = es,                                   \
1235                 .get_rate       = gr,                                   \
1236                 .set_rate       = sr,                                   \
1237                 .enable         = e,                                    \
1238                 .disable        = d,                                    \
1239                 .parent         = p,                                    \
1240                 .secondary      = s,                                    \
1241         }
1242
1243 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)                     \
1244         DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
1245
1246 /* Shared peripheral bus arbiter */
1247 DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
1248         NULL,  NULL, &ipg_clk, NULL);
1249
1250 /* UART */
1251 DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
1252         NULL,  NULL, &ipg_clk, &aips_tz1_clk);
1253 DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
1254         NULL,  NULL, &ipg_clk, &aips_tz1_clk);
1255 DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
1256         NULL,  NULL, &ipg_clk, &spba_clk);
1257 DEFINE_CLOCK(uart4_ipg_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG4_OFFSET,
1258         NULL,  NULL, &ipg_clk, &spba_clk);
1259 DEFINE_CLOCK(uart5_ipg_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG6_OFFSET,
1260         NULL,  NULL, &ipg_clk, &spba_clk);
1261 DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
1262         NULL,  NULL, &uart_root_clk, &uart1_ipg_clk);
1263 DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
1264         NULL,  NULL, &uart_root_clk, &uart2_ipg_clk);
1265 DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
1266         NULL,  NULL, &uart_root_clk, &uart3_ipg_clk);
1267 DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG5_OFFSET,
1268         NULL,  NULL, &uart_root_clk, &uart4_ipg_clk);
1269 DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG7_OFFSET,
1270         NULL,  NULL, &uart_root_clk, &uart5_ipg_clk);
1271
1272 /* GPT */
1273 DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
1274         NULL,  NULL, &ipg_clk, NULL);
1275 DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
1276         NULL,  NULL, &ipg_clk, &gpt_ipg_clk);
1277
1278 DEFINE_CLOCK(pwm1_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG6_OFFSET,
1279         NULL, NULL, &ipg_clk, NULL);
1280 DEFINE_CLOCK(pwm2_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG8_OFFSET,
1281         NULL, NULL, &ipg_clk, NULL);
1282
1283 /* I2C */
1284 DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
1285         NULL, NULL, &ipg_perclk, NULL);
1286 DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
1287         NULL, NULL, &ipg_perclk, NULL);
1288 DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
1289         NULL, NULL, &ipg_clk, NULL);
1290 DEFINE_CLOCK(i2c3_mx53_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
1291         NULL, NULL, &ipg_perclk, NULL);
1292
1293 /* FEC */
1294 DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
1295         NULL,  NULL, &ipg_clk, NULL);
1296
1297 /* NFC */
1298 DEFINE_CLOCK_CCGR(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
1299         clk_nfc, &emi_slow_clk, NULL);
1300
1301 /* SSI */
1302 DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET,
1303         NULL, NULL, &ipg_clk, NULL);
1304 DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET,
1305         NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk);
1306 DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
1307         NULL, NULL, &ipg_clk, NULL);
1308 DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
1309         NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
1310 DEFINE_CLOCK(ssi3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG12_OFFSET,
1311         NULL, NULL, &ipg_clk, NULL);
1312 DEFINE_CLOCK(ssi3_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG13_OFFSET,
1313         NULL, NULL, &pll3_sw_clk, &ssi3_ipg_clk);
1314
1315 /* eCSPI */
1316 DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
1317                 NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
1318                 &ipg_clk, &spba_clk);
1319 DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
1320                 NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
1321 DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
1322                 NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
1323                 &ipg_clk, &aips_tz2_clk);
1324 DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
1325                 NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
1326
1327 /* CSPI */
1328 DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
1329                 NULL, NULL, &ipg_clk, &aips_tz2_clk);
1330 DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
1331                 NULL, NULL, &ipg_clk, &cspi_ipg_clk);
1332
1333 /* SDMA */
1334 DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET,
1335                 NULL, NULL, &ahb_clk, NULL);
1336
1337 /* eSDHC */
1338 DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET,
1339         NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1340 DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
1341         clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
1342 DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
1343         NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1344 DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET,
1345         NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1346 DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET,
1347         NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1348
1349 /* mx51 specific */
1350 DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
1351         clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
1352
1353 static struct clk esdhc3_clk = {
1354         .id = 2,
1355         .parent = &esdhc1_clk,
1356         .set_parent = clk_esdhc3_set_parent,
1357         .enable_reg = MXC_CCM_CCGR3,
1358         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
1359         .enable  = _clk_max_enable,
1360         .disable = _clk_max_disable,
1361         .secondary = &esdhc3_ipg_clk,
1362 };
1363 static struct clk esdhc4_clk = {
1364         .id = 3,
1365         .parent = &esdhc1_clk,
1366         .set_parent = clk_esdhc4_set_parent,
1367         .enable_reg = MXC_CCM_CCGR3,
1368         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1369         .enable  = _clk_max_enable,
1370         .disable = _clk_max_disable,
1371         .secondary = &esdhc4_ipg_clk,
1372 };
1373
1374 /* mx53 specific */
1375 static struct clk esdhc2_mx53_clk = {
1376         .id = 2,
1377         .parent = &esdhc1_clk,
1378         .set_parent = clk_esdhc2_mx53_set_parent,
1379         .enable_reg = MXC_CCM_CCGR3,
1380         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1381         .enable  = _clk_max_enable,
1382         .disable = _clk_max_disable,
1383         .secondary = &esdhc3_ipg_clk,
1384 };
1385
1386 DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET,
1387         clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk);
1388
1389 static struct clk esdhc4_mx53_clk = {
1390         .id = 3,
1391         .parent = &esdhc1_clk,
1392         .set_parent = clk_esdhc4_mx53_set_parent,
1393         .enable_reg = MXC_CCM_CCGR3,
1394         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1395         .enable  = _clk_max_enable,
1396         .disable = _clk_max_disable,
1397         .secondary = &esdhc4_ipg_clk,
1398 };
1399
1400 DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
1401 DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
1402 DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
1403
1404 /* IPU */
1405 DEFINE_CLOCK_FULL(ipu_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG5_OFFSET,
1406         NULL,  NULL, clk_ipu_enable, clk_ipu_disable, &ahb_clk, &ipu_sec_clk);
1407
1408 DEFINE_CLOCK_FULL(emi_fast_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG7_OFFSET,
1409                 NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable_inwait,
1410                 &ddr_clk, NULL);
1411
1412 DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET,
1413                 NULL, NULL, &pll3_sw_clk, NULL);
1414 DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET,
1415                 NULL, NULL, &pll3_sw_clk, NULL);
1416
1417 /* PATA */
1418 DEFINE_CLOCK(pata_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG0_OFFSET,
1419                 NULL, NULL, &ipg_clk, &spba_clk);
1420
1421 #define _REGISTER_CLOCK(d, n, c) \
1422        { \
1423                 .dev_id = d, \
1424                 .con_id = n, \
1425                 .clk = &c,   \
1426        },
1427
1428 static struct clk_lookup mx51_lookups[] = {
1429         /* i.mx51 has the i.mx21 type uart */
1430         _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
1431         _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
1432         _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
1433         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
1434         /* i.mx51 has the i.mx27 type fec */
1435         _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
1436         _REGISTER_CLOCK("mxc_pwm.0", "pwm", pwm1_clk)
1437         _REGISTER_CLOCK("mxc_pwm.1", "pwm", pwm2_clk)
1438         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
1439         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
1440         _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
1441         _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
1442         _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk)
1443         _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk)
1444         _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
1445         _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk)
1446         _REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk)
1447         _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
1448         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
1449         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
1450         _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
1451         _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
1452         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
1453         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
1454         _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
1455         /* i.mx51 has the i.mx35 type sdma */
1456         _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
1457         _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
1458         _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
1459         _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
1460         _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
1461         _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
1462         /* i.mx51 has the i.mx35 type cspi */
1463         _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
1464         _REGISTER_CLOCK("sdhci-esdhc-imx51.0", NULL, esdhc1_clk)
1465         _REGISTER_CLOCK("sdhci-esdhc-imx51.1", NULL, esdhc2_clk)
1466         _REGISTER_CLOCK("sdhci-esdhc-imx51.2", NULL, esdhc3_clk)
1467         _REGISTER_CLOCK("sdhci-esdhc-imx51.3", NULL, esdhc4_clk)
1468         _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
1469         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
1470         _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
1471         _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
1472         _REGISTER_CLOCK(NULL, "mipi_hsp", mipi_hsp_clk)
1473         _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk)
1474         _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk)
1475         _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk)
1476         _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk)
1477         _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
1478 };
1479
1480 static struct clk_lookup mx53_lookups[] = {
1481         /* i.mx53 has the i.mx21 type uart */
1482         _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
1483         _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
1484         _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
1485         _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
1486         _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
1487         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
1488         /* i.mx53 has the i.mx25 type fec */
1489         _REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk)
1490         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
1491         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
1492         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
1493         _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_mx53_clk)
1494         /* i.mx53 has the i.mx51 type ecspi */
1495         _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
1496         _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
1497         /* i.mx53 has the i.mx25 type cspi */
1498         _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
1499         _REGISTER_CLOCK("sdhci-esdhc-imx53.0", NULL, esdhc1_clk)
1500         _REGISTER_CLOCK("sdhci-esdhc-imx53.1", NULL, esdhc2_mx53_clk)
1501         _REGISTER_CLOCK("sdhci-esdhc-imx53.2", NULL, esdhc3_mx53_clk)
1502         _REGISTER_CLOCK("sdhci-esdhc-imx53.3", NULL, esdhc4_mx53_clk)
1503         _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
1504         _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
1505         /* i.mx53 has the i.mx35 type sdma */
1506         _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
1507         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
1508         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
1509         _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
1510         _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
1511         _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
1512 };
1513
1514 static void clk_tree_init(void)
1515 {
1516         u32 reg;
1517
1518         ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
1519
1520         /*
1521          * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
1522          * 8MHz, its derived from lp_apm.
1523          *
1524          * FIXME: Verify if true for all boards
1525          */
1526         reg = __raw_readl(MXC_CCM_CBCDR);
1527         reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
1528         reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
1529         reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
1530         reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
1531         __raw_writel(reg, MXC_CCM_CBCDR);
1532 }
1533
1534 int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
1535                         unsigned long ckih1, unsigned long ckih2)
1536 {
1537         int i;
1538
1539         external_low_reference = ckil;
1540         external_high_reference = ckih1;
1541         ckih2_reference = ckih2;
1542         oscillator_reference = osc;
1543
1544         for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++)
1545                 clkdev_add(&mx51_lookups[i]);
1546
1547         clk_tree_init();
1548
1549         clk_enable(&cpu_clk);
1550         clk_enable(&main_bus_clk);
1551
1552         clk_enable(&iim_clk);
1553         mx51_revision();
1554         clk_disable(&iim_clk);
1555         mx51_display_revision();
1556
1557         /* move usb_phy_clk to 24MHz */
1558         clk_set_parent(&usb_phy1_clk, &osc_clk);
1559
1560         /* set the usboh3_clk parent to pll2_sw_clk */
1561         clk_set_parent(&usboh3_clk, &pll2_sw_clk);
1562
1563         /* Set SDHC parents to be PLL2 */
1564         clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
1565         clk_set_parent(&esdhc2_clk, &pll2_sw_clk);
1566
1567         /* set SDHC root clock as 166.25MHZ*/
1568         clk_set_rate(&esdhc1_clk, 166250000);
1569         clk_set_rate(&esdhc2_clk, 166250000);
1570
1571         /* System timer */
1572         mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
1573                 MX51_MXC_INT_GPT);
1574         return 0;
1575 }
1576
1577 int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
1578                         unsigned long ckih1, unsigned long ckih2)
1579 {
1580         int i;
1581
1582         external_low_reference = ckil;
1583         external_high_reference = ckih1;
1584         ckih2_reference = ckih2;
1585         oscillator_reference = osc;
1586
1587         for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++)
1588                 clkdev_add(&mx53_lookups[i]);
1589
1590         clk_tree_init();
1591
1592         clk_set_parent(&uart_root_clk, &pll3_sw_clk);
1593         clk_enable(&cpu_clk);
1594         clk_enable(&main_bus_clk);
1595
1596         clk_enable(&iim_clk);
1597         mx53_revision();
1598         clk_disable(&iim_clk);
1599         mx53_display_revision();
1600
1601         /* Set SDHC parents to be PLL2 */
1602         clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
1603         clk_set_parent(&esdhc3_mx53_clk, &pll2_sw_clk);
1604
1605         /* set SDHC root clock as 200MHZ*/
1606         clk_set_rate(&esdhc1_clk, 200000000);
1607         clk_set_rate(&esdhc3_mx53_clk, 200000000);
1608
1609         /* System timer */
1610         mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
1611                 MX53_INT_GPT);
1612         return 0;
1613 }