2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/types.h>
20 #include <linux/init.h>
21 #include <linux/clk.h>
22 #include <linux/irq.h>
23 #include <linux/gpio.h>
24 #include <linux/smsc911x.h>
25 #include <linux/platform_device.h>
26 #include <linux/mfd/mc13783.h>
27 #include <linux/spi/spi.h>
28 #include <linux/regulator/machine.h>
30 #include <mach/hardware.h>
31 #include <asm/mach-types.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/time.h>
34 #include <asm/memory.h>
35 #include <asm/mach/map.h>
36 #include <mach/common.h>
37 #include <mach/board-mx31_3ds.h>
38 #include <mach/imx-uart.h>
39 #include <mach/iomux-mx3.h>
40 #include <mach/mxc_nand.h>
47 * @brief This file contains the board-specific initialization routines.
52 static int mx31_3ds_pins[] = {
58 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
60 MX31_PIN_CSPI2_SCLK__SCLK,
61 MX31_PIN_CSPI2_MOSI__MOSI,
62 MX31_PIN_CSPI2_MISO__MISO,
63 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
64 MX31_PIN_CSPI2_SS0__SS0,
65 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
67 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
71 static struct regulator_init_data pwgtx_init = {
78 static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
80 .id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */
81 .init_data = &pwgtx_init,
83 .id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */
84 .init_data = &pwgtx_init,
89 static struct mc13783_platform_data mc13783_pdata __initdata = {
90 .regulators = mx31_3ds_regulators,
91 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
92 .flags = MC13783_USE_REGULATOR,
96 static int spi1_internal_chipselect[] = {
101 static struct spi_imx_master spi1_pdata = {
102 .chipselect = spi1_internal_chipselect,
103 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
106 static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
108 .modalias = "mc13783",
109 .max_speed_hz = 1000000,
111 .chip_select = 1, /* SS2 */
112 .platform_data = &mc13783_pdata,
113 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
121 static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
124 #ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
129 static struct imxuart_platform_data uart_pdata = {
130 .flags = IMXUART_HAVE_RTSCTS,
134 * Support for the SMSC9217 on the Debug board.
137 static struct smsc911x_platform_config smsc911x_config = {
138 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
139 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
140 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
141 .phy_interface = PHY_INTERFACE_MODE_MII,
144 static struct resource smsc911x_resources[] = {
146 .start = LAN9217_BASE_ADDR,
147 .end = LAN9217_BASE_ADDR + 0xff,
148 .flags = IORESOURCE_MEM,
150 .start = EXPIO_INT_ENET,
151 .end = EXPIO_INT_ENET,
152 .flags = IORESOURCE_IRQ,
156 static struct platform_device smsc911x_device = {
159 .num_resources = ARRAY_SIZE(smsc911x_resources),
160 .resource = smsc911x_resources,
162 .platform_data = &smsc911x_config,
167 * Routines for the CPLD on the debug board. It contains a CPLD handling
168 * LEDs, switches, interrupts for Ethernet.
171 static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
177 imr_val = __raw_readw(CPLD_INT_MASK_REG);
178 int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
180 expio_irq = MXC_EXP_IO_BASE;
181 for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
182 if ((int_valid & 1) == 0)
184 generic_handle_irq(expio_irq);
189 * Disable an expio pin's interrupt by setting the bit in the imr.
190 * @param irq an expio virtual irq number
192 static void expio_mask_irq(uint32_t irq)
195 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
197 /* mask the interrupt */
198 reg = __raw_readw(CPLD_INT_MASK_REG);
200 __raw_writew(reg, CPLD_INT_MASK_REG);
204 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
205 * @param irq an expanded io virtual irq number
207 static void expio_ack_irq(uint32_t irq)
209 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
211 /* clear the interrupt status */
212 __raw_writew(1 << expio, CPLD_INT_RESET_REG);
213 __raw_writew(0, CPLD_INT_RESET_REG);
214 /* mask the interrupt */
219 * Enable a expio pin's interrupt by clearing the bit in the imr.
220 * @param irq a expio virtual irq number
222 static void expio_unmask_irq(uint32_t irq)
225 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
227 /* unmask the interrupt */
228 reg = __raw_readw(CPLD_INT_MASK_REG);
229 reg &= ~(1 << expio);
230 __raw_writew(reg, CPLD_INT_MASK_REG);
233 static struct irq_chip expio_irq_chip = {
234 .ack = expio_ack_irq,
235 .mask = expio_mask_irq,
236 .unmask = expio_unmask_irq,
239 static int __init mx31_3ds_init_expio(void)
244 /* Check if there's a debug board connected */
245 if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
246 (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
247 (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
248 /* No Debug board found */
252 pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
253 __raw_readw(CPLD_CODE_VER_REG));
256 * Configure INT line as GPIO input
258 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
260 pr_warning("could not get LAN irq gpio\n");
262 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
264 /* Disable the interrupts and clear the status */
265 __raw_writew(0, CPLD_INT_MASK_REG);
266 __raw_writew(0xFFFF, CPLD_INT_RESET_REG);
267 __raw_writew(0, CPLD_INT_RESET_REG);
268 __raw_writew(0x1F, CPLD_INT_MASK_REG);
269 for (i = MXC_EXP_IO_BASE;
270 i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
272 set_irq_chip(i, &expio_irq_chip);
273 set_irq_handler(i, handle_level_irq);
274 set_irq_flags(i, IRQF_VALID);
276 set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
277 set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
283 * This structure defines the MX31 memory map.
285 static struct map_desc mx31_3ds_io_desc[] __initdata = {
287 .virtual = MX31_CS5_BASE_ADDR_VIRT,
288 .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
289 .length = MX31_CS5_SIZE,
295 * Set up static virtual mappings.
297 static void __init mx31_3ds_map_io(void)
300 iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
304 * Board specific initialization.
306 static void __init mxc_board_init(void)
308 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
311 mxc_register_device(&mxc_uart_device0, &uart_pdata);
312 mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);
314 mxc_register_device(&mxc_spi_device1, &spi1_pdata);
315 spi_register_board_info(mx31_3ds_spi_devs,
316 ARRAY_SIZE(mx31_3ds_spi_devs));
318 if (!mx31_3ds_init_expio())
319 platform_device_register(&smsc911x_device);
322 static void __init mx31_3ds_timer_init(void)
324 mx31_clocks_init(26000000);
327 static struct sys_timer mx31_3ds_timer = {
328 .init = mx31_3ds_timer_init,
332 * The following uses standard kernel macros defined in arch.h in order to
333 * initialize __mach_desc_MX31_3DS data structure.
335 MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
336 /* Maintainer: Freescale Semiconductor, Inc. */
337 .phys_io = MX31_AIPS1_BASE_ADDR,
338 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
339 .boot_params = MX3x_PHYS_OFFSET + 0x100,
340 .map_io = mx31_3ds_map_io,
341 .init_irq = mx31_init_irq,
342 .init_machine = mxc_board_init,
343 .timer = &mx31_3ds_timer,