arch/arm/mach-mx2/mach-mx21ads.c

   1 /*
   2  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   3  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   4  *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 #include <linux/platform_device.h>
  22 #include <linux/mtd/mtd.h>
  23 #include <linux/mtd/physmap.h>
  24 #include <linux/gpio.h>
  25 #include <mach/common.h>
  26 #include <mach/hardware.h>
  27 #include <asm/mach-types.h>
  28 #include <asm/mach/arch.h>
  29 #include <asm/mach/time.h>
  30 #include <asm/mach/map.h>
  31 #include <mach/imx-uart.h>
  32 #include <mach/imxfb.h>
  33 #include <mach/iomux-mx21.h>
  34 #include <mach/mxc_nand.h>
  35 #include <mach/mmc.h>
  36 #include <mach/board-mx21ads.h>
  37
  38 #include "devices.h"
  39
  40 static unsigned int mx21ads_pins[] = {
  41
  42         /* CS8900A */
  43         (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11),
  44
  45         /* UART1 */
  46         PE12_PF_UART1_TXD,
  47         PE13_PF_UART1_RXD,
  48         PE14_PF_UART1_CTS,
  49         PE15_PF_UART1_RTS,
  50
  51         /* UART3 (IrDA) - only TXD and RXD */
  52         PE8_PF_UART3_TXD,
  53         PE9_PF_UART3_RXD,
  54
  55         /* UART4 */
  56         PB26_AF_UART4_RTS,
  57         PB28_AF_UART4_TXD,
  58         PB29_AF_UART4_CTS,
  59         PB31_AF_UART4_RXD,
  60
  61         /* LCDC */
  62         PA5_PF_LSCLK,
  63         PA6_PF_LD0,
  64         PA7_PF_LD1,
  65         PA8_PF_LD2,
  66         PA9_PF_LD3,
  67         PA10_PF_LD4,
  68         PA11_PF_LD5,
  69         PA12_PF_LD6,
  70         PA13_PF_LD7,
  71         PA14_PF_LD8,
  72         PA15_PF_LD9,
  73         PA16_PF_LD10,
  74         PA17_PF_LD11,
  75         PA18_PF_LD12,
  76         PA19_PF_LD13,
  77         PA20_PF_LD14,
  78         PA21_PF_LD15,
  79         PA22_PF_LD16,
  80         PA24_PF_REV,     /* Sharp panel dedicated signal */
  81         PA25_PF_CLS,     /* Sharp panel dedicated signal */
  82         PA26_PF_PS,      /* Sharp panel dedicated signal */
  83         PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */
  84         PA28_PF_HSYNC,
  85         PA29_PF_VSYNC,
  86         PA30_PF_CONTRAST,
  87         PA31_PF_OE_ACD,
  88
  89         /* MMC/SDHC */
  90         PE18_PF_SD1_D0,
  91         PE19_PF_SD1_D1,
  92         PE20_PF_SD1_D2,
  93         PE21_PF_SD1_D3,
  94         PE22_PF_SD1_CMD,
  95         PE23_PF_SD1_CLK,
  96
  97         /* NFC */
  98         PF0_PF_NRFB,
  99         PF1_PF_NFCE,
 100         PF2_PF_NFWP,
 101         PF3_PF_NFCLE,
 102         PF4_PF_NFALE,
 103         PF5_PF_NFRE,
 104         PF6_PF_NFWE,
 105         PF7_PF_NFIO0,
 106         PF8_PF_NFIO1,
 107         PF9_PF_NFIO2,
 108         PF10_PF_NFIO3,
 109         PF11_PF_NFIO4,
 110         PF12_PF_NFIO5,
 111         PF13_PF_NFIO6,
 112         PF14_PF_NFIO7,
 113 };
 114
 115 /* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */
 116 static struct physmap_flash_data mx21ads_flash_data = {
 117         .width = 4,
 118 };
 119
 120 static struct resource mx21ads_flash_resource = {
 121         .start = MX21_CS0_BASE_ADDR,
 122         .end = MX21_CS0_BASE_ADDR + 0x02000000 - 1,
 123         .flags = IORESOURCE_MEM,
 124 };
 125
 126 static struct platform_device mx21ads_nor_mtd_device = {
 127         .name = "physmap-flash",
 128         .id = 0,
 129         .dev = {
 130                 .platform_data = &mx21ads_flash_data,
 131         },
 132         .num_resources = 1,
 133         .resource = &mx21ads_flash_resource,
 134 };
 135
 136 static struct imxuart_platform_data uart_pdata = {
 137         .flags = IMXUART_HAVE_RTSCTS,
 138 };
 139
 140 static struct imxuart_platform_data uart_norts_pdata = {
 141 };
 142
 143
 144 static int mx21ads_fb_init(struct platform_device *pdev)
 145 {
 146         u16 tmp;
 147
 148         tmp = __raw_readw(MX21ADS_IO_REG);
 149         tmp |= MX21ADS_IO_LCDON;
 150         __raw_writew(tmp, MX21ADS_IO_REG);
 151         return 0;
 152 }
 153
 154 static void mx21ads_fb_exit(struct platform_device *pdev)
 155 {
 156         u16 tmp;
 157
 158         tmp = __raw_readw(MX21ADS_IO_REG);
 159         tmp &= ~MX21ADS_IO_LCDON;
 160         __raw_writew(tmp, MX21ADS_IO_REG);
 161 }
 162
 163 /*
 164  * Connected is a portrait Sharp-QVGA display
 165  * of type: LQ035Q7DB02
 166  */
 167 static struct imx_fb_videomode mx21ads_modes[] = {
 168         {
 169                 .mode = {
 170                         .name           = "Sharp-LQ035Q7",
 171                         .refresh        = 60,
 172                         .xres           = 240,
 173                         .yres           = 320,
 174                         .pixclock       = 188679, /* in ps (5.3MHz) */
 175                         .hsync_len      = 2,
 176                         .left_margin    = 6,
 177                         .right_margin   = 16,
 178                         .vsync_len      = 1,
 179                         .upper_margin   = 8,
 180                         .lower_margin   = 10,
 181                 },
 182                 .pcr            = 0xfb108bc7,
 183                 .bpp            = 16,
 184         },
 185 };
 186
 187 static struct imx_fb_platform_data mx21ads_fb_data = {
 188         .mode = mx21ads_modes,
 189         .num_modes = ARRAY_SIZE(mx21ads_modes),
 190
 191         .pwmr           = 0x00a903ff,
 192         .lscr1          = 0x00120300,
 193         .dmacr          = 0x00020008,
 194
 195         .init = mx21ads_fb_init,
 196         .exit = mx21ads_fb_exit,
 197 };
 198
 199 static int mx21ads_sdhc_get_ro(struct device *dev)
 200 {
 201         return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0;
 202 }
 203
 204 static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
 205         void *data)
 206 {
 207         int ret;
 208
 209         ret = request_irq(IRQ_GPIOD(25), detect_irq,
 210                 IRQF_TRIGGER_FALLING, "mmc-detect", data);
 211         if (ret)
 212                 goto out;
 213         return 0;
 214 out:
 215         return ret;
 216 }
 217
 218 static void mx21ads_sdhc_exit(struct device *dev, void *data)
 219 {
 220         free_irq(IRQ_GPIOD(25), data);
 221 }
 222
 223 static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
 224         .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */
 225         .get_ro = mx21ads_sdhc_get_ro,
 226         .init = mx21ads_sdhc_init,
 227         .exit = mx21ads_sdhc_exit,
 228 };
 229
 230 static struct mxc_nand_platform_data mx21ads_nand_board_info = {
 231         .width = 1,
 232         .hw_ecc = 1,
 233 };
 234
 235 static struct map_desc mx21ads_io_desc[] __initdata = {
 236         /*
 237          * Memory-mapped I/O on MX21ADS Base board:
 238          *   - CS8900A Ethernet controller
 239          *   - ST16C2552CJ UART
 240          *   - CPU and Base board version
 241          *   - Base board I/O register
 242          */
 243         {
 244                 .virtual = MX21ADS_MMIO_BASE_ADDR,
 245                 .pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR),
 246                 .length = MX21ADS_MMIO_SIZE,
 247                 .type = MT_DEVICE,
 248         },
 249 };
 250
 251 static void __init mx21ads_map_io(void)
 252 {
 253         mx21_map_io();
 254         iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc));
 255 }
 256
 257 static struct platform_device *platform_devices[] __initdata = {
 258         &mx21ads_nor_mtd_device,
 259 };
 260
 261 static void __init mx21ads_board_init(void)
 262 {
 263         mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
 264                         "mx21ads");
 265
 266         mxc_register_device(&mxc_uart_device0, &uart_pdata);
 267         mxc_register_device(&mxc_uart_device2, &uart_norts_pdata);
 268         mxc_register_device(&mxc_uart_device3, &uart_pdata);
 269         mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
 270         mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
 271         mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info);
 272
 273         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 274 }
 275
 276 static void __init mx21ads_timer_init(void)
 277 {
 278         mx21_clocks_init(32768, 26000000);
 279 }
 280
 281 static struct sys_timer mx21ads_timer = {
 282         .init   = mx21ads_timer_init,
 283 };
 284
 285 MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
 286         /* maintainer: Freescale Semiconductor, Inc. */
 287         .phys_io        = MX21_AIPI_BASE_ADDR,
 288         .io_pg_offst    = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
 289         .boot_params    = MX21_PHYS_OFFSET + 0x100,
 290         .map_io         = mx21ads_map_io,
 291         .init_irq       = mx21_init_irq,
 292         .init_machine   = mx21ads_board_init,
 293         .timer          = &mx21ads_timer,
 294 MACHINE_END