arch/arm/mach-mv78xx0/common.c

   1 /*
   2  * arch/arm/mach-mv78xx0/common.c
   3  *
   4  * Core functions for Marvell MV78xx0 SoCs
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/serial_8250.h>
  15 #include <linux/mbus.h>
  16 #include <linux/mv643xx_eth.h>
  17 #include <linux/ata_platform.h>
  18 #include <asm/mach/map.h>
  19 #include <asm/mach/time.h>
  20 #include <mach/mv78xx0.h>
  21 #include <plat/cache-feroceon-l2.h>
  22 #include <plat/ehci-orion.h>
  23 #include <plat/orion_nand.h>
  24 #include <plat/time.h>
  25 #include "common.h"
  26
  27
  28 /*****************************************************************************
  29  * Common bits
  30  ****************************************************************************/
  31 int mv78xx0_core_index(void)
  32 {
  33         u32 extra;
  34
  35         /*
  36          * Read Extra Features register.
  37          */
  38         __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
  39
  40         return !!(extra & 0x00004000);
  41 }
  42
  43 static int get_hclk(void)
  44 {
  45         int hclk;
  46
  47         /*
  48          * HCLK tick rate is configured by DEV_D[7:5] pins.
  49          */
  50         switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
  51         case 0:
  52                 hclk = 166666667;
  53                 break;
  54         case 1:
  55                 hclk = 200000000;
  56                 break;
  57         case 2:
  58                 hclk = 266666667;
  59                 break;
  60         case 3:
  61                 hclk = 333333333;
  62                 break;
  63         case 4:
  64                 hclk = 400000000;
  65                 break;
  66         default:
  67                 panic("unknown HCLK PLL setting: %.8x\n",
  68                         readl(SAMPLE_AT_RESET_LOW));
  69         }
  70
  71         return hclk;
  72 }
  73
  74 static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
  75 {
  76         u32 cfg;
  77
  78         /*
  79          * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
  80          * PCLK/L2CLK by bits [19:14].
  81          */
  82         if (core_index == 0) {
  83                 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
  84         } else {
  85                 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
  86         }
  87
  88         /*
  89          * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
  90          * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
  91          */
  92         *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
  93
  94         /*
  95          * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
  96          * ratio (1, 2, 3).
  97          */
  98         *l2clk = *pclk / (((cfg >> 4) & 3) + 1);
  99 }
 100
 101 static int get_tclk(void)
 102 {
 103         int tclk;
 104
 105         /*
 106          * TCLK tick rate is configured by DEV_A[2:0] strap pins.
 107          */
 108         switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
 109         case 1:
 110                 tclk = 166666667;
 111                 break;
 112         case 3:
 113                 tclk = 200000000;
 114                 break;
 115         default:
 116                 panic("unknown TCLK PLL setting: %.8x\n",
 117                         readl(SAMPLE_AT_RESET_HIGH));
 118         }
 119
 120         return tclk;
 121 }
 122
 123
 124 /*****************************************************************************
 125  * I/O Address Mapping
 126  ****************************************************************************/
 127 static struct map_desc mv78xx0_io_desc[] __initdata = {
 128         {
 129                 .virtual        = MV78XX0_CORE_REGS_VIRT_BASE,
 130                 .pfn            = 0,
 131                 .length         = MV78XX0_CORE_REGS_SIZE,
 132                 .type           = MT_DEVICE,
 133         }, {
 134                 .virtual        = MV78XX0_PCIE_IO_VIRT_BASE(0),
 135                 .pfn            = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
 136                 .length         = MV78XX0_PCIE_IO_SIZE * 8,
 137                 .type           = MT_DEVICE,
 138         }, {
 139                 .virtual        = MV78XX0_REGS_VIRT_BASE,
 140                 .pfn            = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
 141                 .length         = MV78XX0_REGS_SIZE,
 142                 .type           = MT_DEVICE,
 143         },
 144 };
 145
 146 void __init mv78xx0_map_io(void)
 147 {
 148         unsigned long phys;
 149
 150         /*
 151          * Map the right set of per-core registers depending on
 152          * which core we are running on.
 153          */
 154         if (mv78xx0_core_index() == 0) {
 155                 phys = MV78XX0_CORE0_REGS_PHYS_BASE;
 156         } else {
 157                 phys = MV78XX0_CORE1_REGS_PHYS_BASE;
 158         }
 159         mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
 160
 161         iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
 162 }
 163
 164
 165 /*****************************************************************************
 166  * EHCI
 167  ****************************************************************************/
 168 static struct orion_ehci_data mv78xx0_ehci_data = {
 169         .dram           = &mv78xx0_mbus_dram_info,
 170         .phy_version    = EHCI_PHY_NA,
 171 };
 172
 173 static u64 ehci_dmamask = 0xffffffffUL;
 174
 175
 176 /*****************************************************************************
 177  * EHCI0
 178  ****************************************************************************/
 179 static struct resource mv78xx0_ehci0_resources[] = {
 180         {
 181                 .start  = USB0_PHYS_BASE,
 182                 .end    = USB0_PHYS_BASE + 0x0fff,
 183                 .flags  = IORESOURCE_MEM,
 184         }, {
 185                 .start  = IRQ_MV78XX0_USB_0,
 186                 .end    = IRQ_MV78XX0_USB_0,
 187                 .flags  = IORESOURCE_IRQ,
 188         },
 189 };
 190
 191 static struct platform_device mv78xx0_ehci0 = {
 192         .name           = "orion-ehci",
 193         .id             = 0,
 194         .dev            = {
 195                 .dma_mask               = &ehci_dmamask,
 196                 .coherent_dma_mask      = 0xffffffff,
 197                 .platform_data          = &mv78xx0_ehci_data,
 198         },
 199         .resource       = mv78xx0_ehci0_resources,
 200         .num_resources  = ARRAY_SIZE(mv78xx0_ehci0_resources),
 201 };
 202
 203 void __init mv78xx0_ehci0_init(void)
 204 {
 205         platform_device_register(&mv78xx0_ehci0);
 206 }
 207
 208
 209 /*****************************************************************************
 210  * EHCI1
 211  ****************************************************************************/
 212 static struct resource mv78xx0_ehci1_resources[] = {
 213         {
 214                 .start  = USB1_PHYS_BASE,
 215                 .end    = USB1_PHYS_BASE + 0x0fff,
 216                 .flags  = IORESOURCE_MEM,
 217         }, {
 218                 .start  = IRQ_MV78XX0_USB_1,
 219                 .end    = IRQ_MV78XX0_USB_1,
 220                 .flags  = IORESOURCE_IRQ,
 221         },
 222 };
 223
 224 static struct platform_device mv78xx0_ehci1 = {
 225         .name           = "orion-ehci",
 226         .id             = 1,
 227         .dev            = {
 228                 .dma_mask               = &ehci_dmamask,
 229                 .coherent_dma_mask      = 0xffffffff,
 230                 .platform_data          = &mv78xx0_ehci_data,
 231         },
 232         .resource       = mv78xx0_ehci1_resources,
 233         .num_resources  = ARRAY_SIZE(mv78xx0_ehci1_resources),
 234 };
 235
 236 void __init mv78xx0_ehci1_init(void)
 237 {
 238         platform_device_register(&mv78xx0_ehci1);
 239 }
 240
 241
 242 /*****************************************************************************
 243  * EHCI2
 244  ****************************************************************************/
 245 static struct resource mv78xx0_ehci2_resources[] = {
 246         {
 247                 .start  = USB2_PHYS_BASE,
 248                 .end    = USB2_PHYS_BASE + 0x0fff,
 249                 .flags  = IORESOURCE_MEM,
 250         }, {
 251                 .start  = IRQ_MV78XX0_USB_2,
 252                 .end    = IRQ_MV78XX0_USB_2,
 253                 .flags  = IORESOURCE_IRQ,
 254         },
 255 };
 256
 257 static struct platform_device mv78xx0_ehci2 = {
 258         .name           = "orion-ehci",
 259         .id             = 2,
 260         .dev            = {
 261                 .dma_mask               = &ehci_dmamask,
 262                 .coherent_dma_mask      = 0xffffffff,
 263                 .platform_data          = &mv78xx0_ehci_data,
 264         },
 265         .resource       = mv78xx0_ehci2_resources,
 266         .num_resources  = ARRAY_SIZE(mv78xx0_ehci2_resources),
 267 };
 268
 269 void __init mv78xx0_ehci2_init(void)
 270 {
 271         platform_device_register(&mv78xx0_ehci2);
 272 }
 273
 274
 275 /*****************************************************************************
 276  * GE00
 277  ****************************************************************************/
 278 struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = {
 279         .t_clk          = 0,
 280         .dram           = &mv78xx0_mbus_dram_info,
 281 };
 282
 283 static struct resource mv78xx0_ge00_shared_resources[] = {
 284         {
 285                 .name   = "ge00 base",
 286                 .start  = GE00_PHYS_BASE + 0x2000,
 287                 .end    = GE00_PHYS_BASE + 0x3fff,
 288                 .flags  = IORESOURCE_MEM,
 289         }, {
 290                 .name   = "ge err irq",
 291                 .start  = IRQ_MV78XX0_GE_ERR,
 292                 .end    = IRQ_MV78XX0_GE_ERR,
 293                 .flags  = IORESOURCE_IRQ,
 294         },
 295 };
 296
 297 static struct platform_device mv78xx0_ge00_shared = {
 298         .name           = MV643XX_ETH_SHARED_NAME,
 299         .id             = 0,
 300         .dev            = {
 301                 .platform_data  = &mv78xx0_ge00_shared_data,
 302         },
 303         .num_resources  = ARRAY_SIZE(mv78xx0_ge00_shared_resources),
 304         .resource       = mv78xx0_ge00_shared_resources,
 305 };
 306
 307 static struct resource mv78xx0_ge00_resources[] = {
 308         {
 309                 .name   = "ge00 irq",
 310                 .start  = IRQ_MV78XX0_GE00_SUM,
 311                 .end    = IRQ_MV78XX0_GE00_SUM,
 312                 .flags  = IORESOURCE_IRQ,
 313         },
 314 };
 315
 316 static struct platform_device mv78xx0_ge00 = {
 317         .name           = MV643XX_ETH_NAME,
 318         .id             = 0,
 319         .num_resources  = 1,
 320         .resource       = mv78xx0_ge00_resources,
 321 };
 322
 323 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 324 {
 325         eth_data->shared = &mv78xx0_ge00_shared;
 326         mv78xx0_ge00.dev.platform_data = eth_data;
 327
 328         platform_device_register(&mv78xx0_ge00_shared);
 329         platform_device_register(&mv78xx0_ge00);
 330 }
 331
 332
 333 /*****************************************************************************
 334  * GE01
 335  ****************************************************************************/
 336 struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = {
 337         .t_clk          = 0,
 338         .dram           = &mv78xx0_mbus_dram_info,
 339         .shared_smi     = &mv78xx0_ge00_shared,
 340 };
 341
 342 static struct resource mv78xx0_ge01_shared_resources[] = {
 343         {
 344                 .name   = "ge01 base",
 345                 .start  = GE01_PHYS_BASE + 0x2000,
 346                 .end    = GE01_PHYS_BASE + 0x3fff,
 347                 .flags  = IORESOURCE_MEM,
 348         },
 349 };
 350
 351 static struct platform_device mv78xx0_ge01_shared = {
 352         .name           = MV643XX_ETH_SHARED_NAME,
 353         .id             = 1,
 354         .dev            = {
 355                 .platform_data  = &mv78xx0_ge01_shared_data,
 356         },
 357         .num_resources  = 1,
 358         .resource       = mv78xx0_ge01_shared_resources,
 359 };
 360
 361 static struct resource mv78xx0_ge01_resources[] = {
 362         {
 363                 .name   = "ge01 irq",
 364                 .start  = IRQ_MV78XX0_GE01_SUM,
 365                 .end    = IRQ_MV78XX0_GE01_SUM,
 366                 .flags  = IORESOURCE_IRQ,
 367         },
 368 };
 369
 370 static struct platform_device mv78xx0_ge01 = {
 371         .name           = MV643XX_ETH_NAME,
 372         .id             = 1,
 373         .num_resources  = 1,
 374         .resource       = mv78xx0_ge01_resources,
 375 };
 376
 377 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 378 {
 379         eth_data->shared = &mv78xx0_ge01_shared;
 380         mv78xx0_ge01.dev.platform_data = eth_data;
 381
 382         platform_device_register(&mv78xx0_ge01_shared);
 383         platform_device_register(&mv78xx0_ge01);
 384 }
 385
 386
 387 /*****************************************************************************
 388  * GE10
 389  ****************************************************************************/
 390 struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = {
 391         .t_clk          = 0,
 392         .dram           = &mv78xx0_mbus_dram_info,
 393         .shared_smi     = &mv78xx0_ge00_shared,
 394 };
 395
 396 static struct resource mv78xx0_ge10_shared_resources[] = {
 397         {
 398                 .name   = "ge10 base",
 399                 .start  = GE10_PHYS_BASE + 0x2000,
 400                 .end    = GE10_PHYS_BASE + 0x3fff,
 401                 .flags  = IORESOURCE_MEM,
 402         },
 403 };
 404
 405 static struct platform_device mv78xx0_ge10_shared = {
 406         .name           = MV643XX_ETH_SHARED_NAME,
 407         .id             = 2,
 408         .dev            = {
 409                 .platform_data  = &mv78xx0_ge10_shared_data,
 410         },
 411         .num_resources  = 1,
 412         .resource       = mv78xx0_ge10_shared_resources,
 413 };
 414
 415 static struct resource mv78xx0_ge10_resources[] = {
 416         {
 417                 .name   = "ge10 irq",
 418                 .start  = IRQ_MV78XX0_GE10_SUM,
 419                 .end    = IRQ_MV78XX0_GE10_SUM,
 420                 .flags  = IORESOURCE_IRQ,
 421         },
 422 };
 423
 424 static struct platform_device mv78xx0_ge10 = {
 425         .name           = MV643XX_ETH_NAME,
 426         .id             = 2,
 427         .num_resources  = 1,
 428         .resource       = mv78xx0_ge10_resources,
 429 };
 430
 431 void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
 432 {
 433         eth_data->shared = &mv78xx0_ge10_shared;
 434         mv78xx0_ge10.dev.platform_data = eth_data;
 435
 436         platform_device_register(&mv78xx0_ge10_shared);
 437         platform_device_register(&mv78xx0_ge10);
 438 }
 439
 440
 441 /*****************************************************************************
 442  * GE11
 443  ****************************************************************************/
 444 struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = {
 445         .t_clk          = 0,
 446         .dram           = &mv78xx0_mbus_dram_info,
 447         .shared_smi     = &mv78xx0_ge00_shared,
 448 };
 449
 450 static struct resource mv78xx0_ge11_shared_resources[] = {
 451         {
 452                 .name   = "ge11 base",
 453                 .start  = GE11_PHYS_BASE + 0x2000,
 454                 .end    = GE11_PHYS_BASE + 0x3fff,
 455                 .flags  = IORESOURCE_MEM,
 456         },
 457 };
 458
 459 static struct platform_device mv78xx0_ge11_shared = {
 460         .name           = MV643XX_ETH_SHARED_NAME,
 461         .id             = 3,
 462         .dev            = {
 463                 .platform_data  = &mv78xx0_ge11_shared_data,
 464         },
 465         .num_resources  = 1,
 466         .resource       = mv78xx0_ge11_shared_resources,
 467 };
 468
 469 static struct resource mv78xx0_ge11_resources[] = {
 470         {
 471                 .name   = "ge11 irq",
 472                 .start  = IRQ_MV78XX0_GE11_SUM,
 473                 .end    = IRQ_MV78XX0_GE11_SUM,
 474                 .flags  = IORESOURCE_IRQ,
 475         },
 476 };
 477
 478 static struct platform_device mv78xx0_ge11 = {
 479         .name           = MV643XX_ETH_NAME,
 480         .id             = 3,
 481         .num_resources  = 1,
 482         .resource       = mv78xx0_ge11_resources,
 483 };
 484
 485 void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
 486 {
 487         eth_data->shared = &mv78xx0_ge11_shared;
 488         mv78xx0_ge11.dev.platform_data = eth_data;
 489
 490         platform_device_register(&mv78xx0_ge11_shared);
 491         platform_device_register(&mv78xx0_ge11);
 492 }
 493
 494
 495 /*****************************************************************************
 496  * SATA
 497  ****************************************************************************/
 498 static struct resource mv78xx0_sata_resources[] = {
 499         {
 500                 .name   = "sata base",
 501                 .start  = SATA_PHYS_BASE,
 502                 .end    = SATA_PHYS_BASE + 0x5000 - 1,
 503                 .flags  = IORESOURCE_MEM,
 504         }, {
 505                 .name   = "sata irq",
 506                 .start  = IRQ_MV78XX0_SATA,
 507                 .end    = IRQ_MV78XX0_SATA,
 508                 .flags  = IORESOURCE_IRQ,
 509         },
 510 };
 511
 512 static struct platform_device mv78xx0_sata = {
 513         .name           = "sata_mv",
 514         .id             = 0,
 515         .dev            = {
 516                 .coherent_dma_mask      = 0xffffffff,
 517         },
 518         .num_resources  = ARRAY_SIZE(mv78xx0_sata_resources),
 519         .resource       = mv78xx0_sata_resources,
 520 };
 521
 522 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
 523 {
 524         sata_data->dram = &mv78xx0_mbus_dram_info;
 525         mv78xx0_sata.dev.platform_data = sata_data;
 526         platform_device_register(&mv78xx0_sata);
 527 }
 528
 529
 530 /*****************************************************************************
 531  * UART0
 532  ****************************************************************************/
 533 static struct plat_serial8250_port mv78xx0_uart0_data[] = {
 534         {
 535                 .mapbase        = UART0_PHYS_BASE,
 536                 .membase        = (char *)UART0_VIRT_BASE,
 537                 .irq            = IRQ_MV78XX0_UART_0,
 538                 .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
 539                 .iotype         = UPIO_MEM,
 540                 .regshift       = 2,
 541                 .uartclk        = 0,
 542         }, {
 543         },
 544 };
 545
 546 static struct resource mv78xx0_uart0_resources[] = {
 547         {
 548                 .start          = UART0_PHYS_BASE,
 549                 .end            = UART0_PHYS_BASE + 0xff,
 550                 .flags          = IORESOURCE_MEM,
 551         }, {
 552                 .start          = IRQ_MV78XX0_UART_0,
 553                 .end            = IRQ_MV78XX0_UART_0,
 554                 .flags          = IORESOURCE_IRQ,
 555         },
 556 };
 557
 558 static struct platform_device mv78xx0_uart0 = {
 559         .name                   = "serial8250",
 560         .id                     = 0,
 561         .dev                    = {
 562                 .platform_data  = mv78xx0_uart0_data,
 563         },
 564         .resource               = mv78xx0_uart0_resources,
 565         .num_resources          = ARRAY_SIZE(mv78xx0_uart0_resources),
 566 };
 567
 568 void __init mv78xx0_uart0_init(void)
 569 {
 570         platform_device_register(&mv78xx0_uart0);
 571 }
 572
 573
 574 /*****************************************************************************
 575  * UART1
 576  ****************************************************************************/
 577 static struct plat_serial8250_port mv78xx0_uart1_data[] = {
 578         {
 579                 .mapbase        = UART1_PHYS_BASE,
 580                 .membase        = (char *)UART1_VIRT_BASE,
 581                 .irq            = IRQ_MV78XX0_UART_1,
 582                 .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
 583                 .iotype         = UPIO_MEM,
 584                 .regshift       = 2,
 585                 .uartclk        = 0,
 586         }, {
 587         },
 588 };
 589
 590 static struct resource mv78xx0_uart1_resources[] = {
 591         {
 592                 .start          = UART1_PHYS_BASE,
 593                 .end            = UART1_PHYS_BASE + 0xff,
 594                 .flags          = IORESOURCE_MEM,
 595         }, {
 596                 .start          = IRQ_MV78XX0_UART_1,
 597                 .end            = IRQ_MV78XX0_UART_1,
 598                 .flags          = IORESOURCE_IRQ,
 599         },
 600 };
 601
 602 static struct platform_device mv78xx0_uart1 = {
 603         .name                   = "serial8250",
 604         .id                     = 1,
 605         .dev                    = {
 606                 .platform_data  = mv78xx0_uart1_data,
 607         },
 608         .resource               = mv78xx0_uart1_resources,
 609         .num_resources          = ARRAY_SIZE(mv78xx0_uart1_resources),
 610 };
 611
 612 void __init mv78xx0_uart1_init(void)
 613 {
 614         platform_device_register(&mv78xx0_uart1);
 615 }
 616
 617
 618 /*****************************************************************************
 619  * UART2
 620  ****************************************************************************/
 621 static struct plat_serial8250_port mv78xx0_uart2_data[] = {
 622         {
 623                 .mapbase        = UART2_PHYS_BASE,
 624                 .membase        = (char *)UART2_VIRT_BASE,
 625                 .irq            = IRQ_MV78XX0_UART_2,
 626                 .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
 627                 .iotype         = UPIO_MEM,
 628                 .regshift       = 2,
 629                 .uartclk        = 0,
 630         }, {
 631         },
 632 };
 633
 634 static struct resource mv78xx0_uart2_resources[] = {
 635         {
 636                 .start          = UART2_PHYS_BASE,
 637                 .end            = UART2_PHYS_BASE + 0xff,
 638                 .flags          = IORESOURCE_MEM,
 639         }, {
 640                 .start          = IRQ_MV78XX0_UART_2,
 641                 .end            = IRQ_MV78XX0_UART_2,
 642                 .flags          = IORESOURCE_IRQ,
 643         },
 644 };
 645
 646 static struct platform_device mv78xx0_uart2 = {
 647         .name                   = "serial8250",
 648         .id                     = 2,
 649         .dev                    = {
 650                 .platform_data  = mv78xx0_uart2_data,
 651         },
 652         .resource               = mv78xx0_uart2_resources,
 653         .num_resources          = ARRAY_SIZE(mv78xx0_uart2_resources),
 654 };
 655
 656 void __init mv78xx0_uart2_init(void)
 657 {
 658         platform_device_register(&mv78xx0_uart2);
 659 }
 660
 661
 662 /*****************************************************************************
 663  * UART3
 664  ****************************************************************************/
 665 static struct plat_serial8250_port mv78xx0_uart3_data[] = {
 666         {
 667                 .mapbase        = UART3_PHYS_BASE,
 668                 .membase        = (char *)UART3_VIRT_BASE,
 669                 .irq            = IRQ_MV78XX0_UART_3,
 670                 .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
 671                 .iotype         = UPIO_MEM,
 672                 .regshift       = 2,
 673                 .uartclk        = 0,
 674         }, {
 675         },
 676 };
 677
 678 static struct resource mv78xx0_uart3_resources[] = {
 679         {
 680                 .start          = UART3_PHYS_BASE,
 681                 .end            = UART3_PHYS_BASE + 0xff,
 682                 .flags          = IORESOURCE_MEM,
 683         }, {
 684                 .start          = IRQ_MV78XX0_UART_3,
 685                 .end            = IRQ_MV78XX0_UART_3,
 686                 .flags          = IORESOURCE_IRQ,
 687         },
 688 };
 689
 690 static struct platform_device mv78xx0_uart3 = {
 691         .name                   = "serial8250",
 692         .id                     = 3,
 693         .dev                    = {
 694                 .platform_data  = mv78xx0_uart3_data,
 695         },
 696         .resource               = mv78xx0_uart3_resources,
 697         .num_resources          = ARRAY_SIZE(mv78xx0_uart3_resources),
 698 };
 699
 700 void __init mv78xx0_uart3_init(void)
 701 {
 702         platform_device_register(&mv78xx0_uart3);
 703 }
 704
 705
 706 /*****************************************************************************
 707  * Time handling
 708  ****************************************************************************/
 709 static void mv78xx0_timer_init(void)
 710 {
 711         orion_time_init(IRQ_MV78XX0_TIMER_1, get_tclk());
 712 }
 713
 714 struct sys_timer mv78xx0_timer = {
 715         .init = mv78xx0_timer_init,
 716 };
 717
 718
 719 /*****************************************************************************
 720  * General
 721  ****************************************************************************/
 722 static int __init is_l2_writethrough(void)
 723 {
 724         return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
 725 }
 726
 727 void __init mv78xx0_init(void)
 728 {
 729         int core_index;
 730         int hclk;
 731         int pclk;
 732         int l2clk;
 733         int tclk;
 734
 735         core_index = mv78xx0_core_index();
 736         hclk = get_hclk();
 737         get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
 738         tclk = get_tclk();
 739
 740         printk(KERN_INFO "MV78xx0 core #%d, ", core_index);
 741         printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
 742         printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
 743         printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
 744         printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000);
 745
 746         mv78xx0_setup_cpu_mbus();
 747
 748 #ifdef CONFIG_CACHE_FEROCEON_L2
 749         feroceon_l2_init(is_l2_writethrough());
 750 #endif
 751
 752         mv78xx0_ge00_shared_data.t_clk = tclk;
 753         mv78xx0_ge01_shared_data.t_clk = tclk;
 754         mv78xx0_ge10_shared_data.t_clk = tclk;
 755         mv78xx0_ge11_shared_data.t_clk = tclk;
 756         mv78xx0_uart0_data[0].uartclk = tclk;
 757         mv78xx0_uart1_data[0].uartclk = tclk;
 758         mv78xx0_uart2_data[0].uartclk = tclk;
 759         mv78xx0_uart3_data[0].uartclk = tclk;
 760 }