arch/arm/mach-msm/include/mach/sirc.h

   1 /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #ifndef __ASM_ARCH_MSM_SIRC_H
  14 #define __ASM_ARCH_MSM_SIRC_H
  15
  16 struct sirc_regs_t {
  17         void    *int_enable;
  18         void    *int_enable_clear;
  19         void    *int_enable_set;
  20         void    *int_type;
  21         void    *int_polarity;
  22         void    *int_clear;
  23 };
  24
  25 struct sirc_cascade_regs {
  26         void    *int_status;
  27         unsigned int    cascade_irq;
  28 };
  29
  30 void msm_init_sirc(void);
  31 void msm_sirc_enter_sleep(void);
  32 void msm_sirc_exit_sleep(void);
  33
  34 #if defined(CONFIG_ARCH_MSM_SCORPION)
  35
  36 #include <mach/msm_iomap.h>
  37
  38 /*
  39  * Secondary interrupt controller interrupts
  40  */
  41
  42 #define FIRST_SIRC_IRQ (NR_MSM_IRQS + NR_GPIO_IRQS)
  43
  44 #define INT_UART1                     (FIRST_SIRC_IRQ + 0)
  45 #define INT_UART2                     (FIRST_SIRC_IRQ + 1)
  46 #define INT_UART3                     (FIRST_SIRC_IRQ + 2)
  47 #define INT_UART1_RX                  (FIRST_SIRC_IRQ + 3)
  48 #define INT_UART2_RX                  (FIRST_SIRC_IRQ + 4)
  49 #define INT_UART3_RX                  (FIRST_SIRC_IRQ + 5)
  50 #define INT_SPI_INPUT                 (FIRST_SIRC_IRQ + 6)
  51 #define INT_SPI_OUTPUT                (FIRST_SIRC_IRQ + 7)
  52 #define INT_SPI_ERROR                 (FIRST_SIRC_IRQ + 8)
  53 #define INT_GPIO_GROUP1               (FIRST_SIRC_IRQ + 9)
  54 #define INT_GPIO_GROUP2               (FIRST_SIRC_IRQ + 10)
  55 #define INT_GPIO_GROUP1_SECURE        (FIRST_SIRC_IRQ + 11)
  56 #define INT_GPIO_GROUP2_SECURE        (FIRST_SIRC_IRQ + 12)
  57 #define INT_AVS_SVIC                  (FIRST_SIRC_IRQ + 13)
  58 #define INT_AVS_REQ_UP                (FIRST_SIRC_IRQ + 14)
  59 #define INT_AVS_REQ_DOWN              (FIRST_SIRC_IRQ + 15)
  60 #define INT_PBUS_ERR                  (FIRST_SIRC_IRQ + 16)
  61 #define INT_AXI_ERR                   (FIRST_SIRC_IRQ + 17)
  62 #define INT_SMI_ERR                   (FIRST_SIRC_IRQ + 18)
  63 #define INT_EBI1_ERR                  (FIRST_SIRC_IRQ + 19)
  64 #define INT_IMEM_ERR                  (FIRST_SIRC_IRQ + 20)
  65 #define INT_TEMP_SENSOR               (FIRST_SIRC_IRQ + 21)
  66 #define INT_TV_ENC                    (FIRST_SIRC_IRQ + 22)
  67 #define INT_GRP2D                     (FIRST_SIRC_IRQ + 23)
  68 #define INT_GSBI_QUP                  (FIRST_SIRC_IRQ + 24)
  69 #define INT_SC_ACG                    (FIRST_SIRC_IRQ + 25)
  70 #define INT_WDT0                      (FIRST_SIRC_IRQ + 26)
  71 #define INT_WDT1                      (FIRST_SIRC_IRQ + 27)
  72
  73 #if defined(CONFIG_MSM_SOC_REV_A)
  74 #define NR_SIRC_IRQS                  28
  75 #define SIRC_MASK                     0x0FFFFFFF
  76 #else
  77 #define NR_SIRC_IRQS                  23
  78 #define SIRC_MASK                     0x007FFFFF
  79 #endif
  80
  81 #define LAST_SIRC_IRQ                 (FIRST_SIRC_IRQ + NR_SIRC_IRQS - 1)
  82
  83 #define SPSS_SIRC_INT_SELECT          (MSM_SIRC_BASE + 0x00)
  84 #define SPSS_SIRC_INT_ENABLE          (MSM_SIRC_BASE + 0x04)
  85 #define SPSS_SIRC_INT_ENABLE_CLEAR    (MSM_SIRC_BASE + 0x08)
  86 #define SPSS_SIRC_INT_ENABLE_SET      (MSM_SIRC_BASE + 0x0C)
  87 #define SPSS_SIRC_INT_TYPE            (MSM_SIRC_BASE + 0x10)
  88 #define SPSS_SIRC_INT_POLARITY        (MSM_SIRC_BASE + 0x14)
  89 #define SPSS_SIRC_SECURITY            (MSM_SIRC_BASE + 0x18)
  90 #define SPSS_SIRC_IRQ_STATUS          (MSM_SIRC_BASE + 0x1C)
  91 #define SPSS_SIRC_IRQ1_STATUS         (MSM_SIRC_BASE + 0x20)
  92 #define SPSS_SIRC_RAW_STATUS          (MSM_SIRC_BASE + 0x24)
  93 #define SPSS_SIRC_INT_CLEAR           (MSM_SIRC_BASE + 0x28)
  94 #define SPSS_SIRC_SOFT_INT            (MSM_SIRC_BASE + 0x2C)
  95
  96 #endif
  97
  98 #endif