arch/arm/mach-msm/devices-qsd8x50.c

   1 /*
   2  * Copyright (C) 2008 Google, Inc.
   3  * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/clkdev.h>
  19 #include <linux/dma-mapping.h>
  20
  21 #include <mach/irqs.h>
  22 #include <mach/msm_iomap.h>
  23 #include <mach/dma.h>
  24 #include <mach/board.h>
  25
  26 #include "devices.h"
  27
  28 #include <asm/mach/flash.h>
  29
  30 #include <mach/mmc.h>
  31 #include "clock-pcom.h"
  32
  33 static struct resource resources_uart3[] = {
  34         {
  35                 .start  = INT_UART3,
  36                 .end    = INT_UART3,
  37                 .flags  = IORESOURCE_IRQ,
  38         },
  39         {
  40                 .start  = MSM_UART3_PHYS,
  41                 .end    = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
  42                 .flags  = IORESOURCE_MEM,
  43                 .name  = "uart_resource"
  44         },
  45 };
  46
  47 struct platform_device msm_device_uart3 = {
  48         .name   = "msm_serial",
  49         .id     = 2,
  50         .num_resources  = ARRAY_SIZE(resources_uart3),
  51         .resource       = resources_uart3,
  52 };
  53
  54 struct platform_device msm_device_smd = {
  55         .name   = "msm_smd",
  56         .id     = -1,
  57 };
  58
  59 static struct resource resources_otg[] = {
  60         {
  61                 .start  = MSM_HSUSB_PHYS,
  62                 .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
  63                 .flags  = IORESOURCE_MEM,
  64         },
  65         {
  66                 .start  = INT_USB_HS,
  67                 .end    = INT_USB_HS,
  68                 .flags  = IORESOURCE_IRQ,
  69         },
  70 };
  71
  72 struct platform_device msm_device_otg = {
  73         .name           = "msm_otg",
  74         .id             = -1,
  75         .num_resources  = ARRAY_SIZE(resources_otg),
  76         .resource       = resources_otg,
  77         .dev            = {
  78                 .coherent_dma_mask      = 0xffffffff,
  79         },
  80 };
  81
  82 static struct resource resources_hsusb[] = {
  83         {
  84                 .start  = MSM_HSUSB_PHYS,
  85                 .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
  86                 .flags  = IORESOURCE_MEM,
  87         },
  88         {
  89                 .start  = INT_USB_HS,
  90                 .end    = INT_USB_HS,
  91                 .flags  = IORESOURCE_IRQ,
  92         },
  93 };
  94
  95 struct platform_device msm_device_hsusb = {
  96         .name           = "msm_hsusb",
  97         .id             = -1,
  98         .num_resources  = ARRAY_SIZE(resources_hsusb),
  99         .resource       = resources_hsusb,
 100         .dev            = {
 101                 .coherent_dma_mask      = 0xffffffff,
 102         },
 103 };
 104
 105 static u64 dma_mask = 0xffffffffULL;
 106 static struct resource resources_hsusb_host[] = {
 107         {
 108                 .start  = MSM_HSUSB_PHYS,
 109                 .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
 110                 .flags  = IORESOURCE_MEM,
 111         },
 112         {
 113                 .start  = INT_USB_HS,
 114                 .end    = INT_USB_HS,
 115                 .flags  = IORESOURCE_IRQ,
 116         },
 117 };
 118
 119 struct platform_device msm_device_hsusb_host = {
 120         .name           = "msm_hsusb_host",
 121         .id             = -1,
 122         .num_resources  = ARRAY_SIZE(resources_hsusb_host),
 123         .resource       = resources_hsusb_host,
 124         .dev            = {
 125                 .dma_mask               = &dma_mask,
 126                 .coherent_dma_mask      = 0xffffffffULL,
 127         },
 128 };
 129
 130 static struct resource resources_sdc1[] = {
 131         {
 132                 .start  = MSM_SDC1_PHYS,
 133                 .end    = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
 134                 .flags  = IORESOURCE_MEM,
 135         },
 136         {
 137                 .start  = INT_SDC1_0,
 138                 .end    = INT_SDC1_0,
 139                 .flags  = IORESOURCE_IRQ,
 140                 .name   = "cmd_irq",
 141         },
 142         {
 143                 .start  = INT_SDC1_1,
 144                 .end    = INT_SDC1_1,
 145                 .flags  = IORESOURCE_IRQ,
 146                 .name   = "pio_irq",
 147         },
 148         {
 149                 .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
 150                 .name   = "status_irq"
 151         },
 152         {
 153                 .start  = 8,
 154                 .end    = 8,
 155                 .flags  = IORESOURCE_DMA,
 156         },
 157 };
 158
 159 static struct resource resources_sdc2[] = {
 160         {
 161                 .start  = MSM_SDC2_PHYS,
 162                 .end    = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
 163                 .flags  = IORESOURCE_MEM,
 164         },
 165         {
 166                 .start  = INT_SDC2_0,
 167                 .end    = INT_SDC2_0,
 168                 .flags  = IORESOURCE_IRQ,
 169                 .name   = "cmd_irq",
 170         },
 171                 {
 172                 .start  = INT_SDC2_1,
 173                 .end    = INT_SDC2_1,
 174                 .flags  = IORESOURCE_IRQ,
 175                 .name   = "pio_irq",
 176         },
 177         {
 178                 .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
 179                 .name   = "status_irq"
 180         },
 181         {
 182                 .start  = 8,
 183                 .end    = 8,
 184                 .flags  = IORESOURCE_DMA,
 185         },
 186 };
 187
 188 static struct resource resources_sdc3[] = {
 189         {
 190                 .start  = MSM_SDC3_PHYS,
 191                 .end    = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
 192                 .flags  = IORESOURCE_MEM,
 193         },
 194         {
 195                 .start  = INT_SDC3_0,
 196                 .end    = INT_SDC3_0,
 197                 .flags  = IORESOURCE_IRQ,
 198                 .name   = "cmd_irq",
 199         },
 200                 {
 201                 .start  = INT_SDC3_1,
 202                 .end    = INT_SDC3_1,
 203                 .flags  = IORESOURCE_IRQ,
 204                 .name   = "pio_irq",
 205         },
 206         {
 207                 .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
 208                 .name   = "status_irq"
 209         },
 210         {
 211                 .start  = 8,
 212                 .end    = 8,
 213                 .flags  = IORESOURCE_DMA,
 214         },
 215 };
 216
 217 static struct resource resources_sdc4[] = {
 218         {
 219                 .start  = MSM_SDC4_PHYS,
 220                 .end    = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
 221                 .flags  = IORESOURCE_MEM,
 222         },
 223         {
 224                 .start  = INT_SDC4_0,
 225                 .end    = INT_SDC4_0,
 226                 .flags  = IORESOURCE_IRQ,
 227                 .name   = "cmd_irq",
 228         },
 229                 {
 230                 .start  = INT_SDC4_1,
 231                 .end    = INT_SDC4_1,
 232                 .flags  = IORESOURCE_IRQ,
 233                 .name   = "pio_irq",
 234         },
 235         {
 236                 .flags  = IORESOURCE_IRQ | IORESOURCE_DISABLED,
 237                 .name   = "status_irq"
 238         },
 239         {
 240                 .start  = 8,
 241                 .end    = 8,
 242                 .flags  = IORESOURCE_DMA,
 243         },
 244 };
 245
 246 struct platform_device msm_device_sdc1 = {
 247         .name           = "msm_sdcc",
 248         .id             = 1,
 249         .num_resources  = ARRAY_SIZE(resources_sdc1),
 250         .resource       = resources_sdc1,
 251         .dev            = {
 252                 .coherent_dma_mask      = 0xffffffff,
 253         },
 254 };
 255
 256 struct platform_device msm_device_sdc2 = {
 257         .name           = "msm_sdcc",
 258         .id             = 2,
 259         .num_resources  = ARRAY_SIZE(resources_sdc2),
 260         .resource       = resources_sdc2,
 261         .dev            = {
 262                 .coherent_dma_mask      = 0xffffffff,
 263         },
 264 };
 265
 266 struct platform_device msm_device_sdc3 = {
 267         .name           = "msm_sdcc",
 268         .id             = 3,
 269         .num_resources  = ARRAY_SIZE(resources_sdc3),
 270         .resource       = resources_sdc3,
 271         .dev            = {
 272                 .coherent_dma_mask      = 0xffffffff,
 273         },
 274 };
 275
 276 struct platform_device msm_device_sdc4 = {
 277         .name           = "msm_sdcc",
 278         .id             = 4,
 279         .num_resources  = ARRAY_SIZE(resources_sdc4),
 280         .resource       = resources_sdc4,
 281         .dev            = {
 282                 .coherent_dma_mask      = 0xffffffff,
 283         },
 284 };
 285
 286 static struct platform_device *msm_sdcc_devices[] __initdata = {
 287         &msm_device_sdc1,
 288         &msm_device_sdc2,
 289         &msm_device_sdc3,
 290         &msm_device_sdc4,
 291 };
 292
 293 int __init msm_add_sdcc(unsigned int controller,
 294                         struct msm_mmc_platform_data *plat,
 295                         unsigned int stat_irq, unsigned long stat_irq_flags)
 296 {
 297         struct platform_device  *pdev;
 298         struct resource *res;
 299
 300         if (controller < 1 || controller > 4)
 301                 return -EINVAL;
 302
 303         pdev = msm_sdcc_devices[controller-1];
 304         pdev->dev.platform_data = plat;
 305
 306         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq");
 307         if (!res)
 308                 return -EINVAL;
 309         else if (stat_irq) {
 310                 res->start = res->end = stat_irq;
 311                 res->flags &= ~IORESOURCE_DISABLED;
 312                 res->flags |= stat_irq_flags;
 313         }
 314
 315         return platform_device_register(pdev);
 316 }
 317
 318 struct clk_lookup msm_clocks_8x50[] = {
 319         CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
 320         CLK_PCOM("ce_clk",      CE_CLK,         NULL, 0),
 321         CLK_PCOM("ebi1_clk",    EBI1_CLK,       NULL, CLK_MIN),
 322         CLK_PCOM("ebi2_clk",    EBI2_CLK,       NULL, 0),
 323         CLK_PCOM("ecodec_clk",  ECODEC_CLK,     NULL, 0),
 324         CLK_PCOM("emdh_clk",    EMDH_CLK,       NULL, OFF | CLK_MINMAX),
 325         CLK_PCOM("gp_clk",      GP_CLK,         NULL, 0),
 326         CLK_PCOM("grp_clk",     GRP_3D_CLK,     NULL, 0),
 327         CLK_PCOM("i2c_clk",     I2C_CLK,        NULL, 0),
 328         CLK_PCOM("icodec_rx_clk",       ICODEC_RX_CLK,  NULL, 0),
 329         CLK_PCOM("icodec_tx_clk",       ICODEC_TX_CLK,  NULL, 0),
 330         CLK_PCOM("imem_clk",    IMEM_CLK,       NULL, OFF),
 331         CLK_PCOM("mdc_clk",     MDC_CLK,        NULL, 0),
 332         CLK_PCOM("mddi_clk",    PMDH_CLK,       NULL, OFF | CLK_MINMAX),
 333         CLK_PCOM("mdp_clk",     MDP_CLK,        NULL, OFF),
 334         CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0),
 335         CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0),
 336         CLK_PCOM("mdp_vsync_clk",       MDP_VSYNC_CLK,  NULL, 0),
 337         CLK_PCOM("pbus_clk",    PBUS_CLK,       NULL, CLK_MIN),
 338         CLK_PCOM("pcm_clk",     PCM_CLK,        NULL, 0),
 339         CLK_PCOM("sdac_clk",    SDAC_CLK,       NULL, OFF),
 340         CLK_PCOM("sdc_clk",     SDC1_CLK,       "msm_sdcc.1", OFF),
 341         CLK_PCOM("sdc_pclk",    SDC1_P_CLK,     "msm_sdcc.1", OFF),
 342         CLK_PCOM("sdc_clk",     SDC2_CLK,       "msm_sdcc.2", OFF),
 343         CLK_PCOM("sdc_pclk",    SDC2_P_CLK,     "msm_sdcc.2", OFF),
 344         CLK_PCOM("sdc_clk",     SDC3_CLK,       "msm_sdcc.3", OFF),
 345         CLK_PCOM("sdc_pclk",    SDC3_P_CLK,     "msm_sdcc.3", OFF),
 346         CLK_PCOM("sdc_clk",     SDC4_CLK,       "msm_sdcc.4", OFF),
 347         CLK_PCOM("sdc_pclk",    SDC4_P_CLK,     "msm_sdcc.4", OFF),
 348         CLK_PCOM("spi_clk",     SPI_CLK,        NULL, 0),
 349         CLK_PCOM("tsif_clk",    TSIF_CLK,       NULL, 0),
 350         CLK_PCOM("tsif_ref_clk",        TSIF_REF_CLK,   NULL, 0),
 351         CLK_PCOM("tv_dac_clk",  TV_DAC_CLK,     NULL, 0),
 352         CLK_PCOM("tv_enc_clk",  TV_ENC_CLK,     NULL, 0),
 353         CLK_PCOM("uart_clk",    UART1_CLK,      NULL, OFF),
 354         CLK_PCOM("uart_clk",    UART2_CLK,      NULL, 0),
 355         CLK_PCOM("uart_clk",    UART3_CLK,      "msm_serial.2", OFF),
 356         CLK_PCOM("uartdm_clk",  UART1DM_CLK,    NULL, OFF),
 357         CLK_PCOM("uartdm_clk",  UART2DM_CLK,    NULL, 0),
 358         CLK_PCOM("usb_hs_clk",  USB_HS_CLK,     NULL, OFF),
 359         CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK,   NULL, OFF),
 360         CLK_PCOM("usb_otg_clk", USB_OTG_CLK,    NULL, 0),
 361         CLK_PCOM("vdc_clk",     VDC_CLK,        NULL, OFF | CLK_MIN),
 362         CLK_PCOM("vfe_clk",     VFE_CLK,        NULL, OFF),
 363         CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK,    NULL, OFF),
 364         CLK_PCOM("vfe_axi_clk", VFE_AXI_CLK,    NULL, OFF),
 365         CLK_PCOM("usb_hs2_clk", USB_HS2_CLK,    NULL, OFF),
 366         CLK_PCOM("usb_hs2_pclk",        USB_HS2_P_CLK,  NULL, OFF),
 367         CLK_PCOM("usb_hs3_clk", USB_HS3_CLK,    NULL, OFF),
 368         CLK_PCOM("usb_hs3_pclk",        USB_HS3_P_CLK,  NULL, OFF),
 369         CLK_PCOM("usb_phy_clk", USB_PHY_CLK,    NULL, 0),
 370 };
 371
 372 unsigned msm_num_clocks_8x50 = ARRAY_SIZE(msm_clocks_8x50);
 373