arch/arm/mach-lh7a40x/arch-lpd7a40x.c

   1 /* arch/arm/mach-lh7a40x/arch-lpd7a40x.c
   2  *
   3  *  Copyright (C) 2004 Logic Product Development
   4  *
   5  *  This program is free software; you can redistribute it and/or
   6  *  modify it under the terms of the GNU General Public License
   7  *  version 2 as published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include <linux/tty.h>
  12 #include <linux/init.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16
  17 #include <asm/hardware.h>
  18 #include <asm/setup.h>
  19 #include <asm/mach-types.h>
  20 #include <asm/mach/arch.h>
  21 #include <asm/irq.h>
  22 #include <asm/mach/irq.h>
  23 #include <asm/mach/map.h>
  24
  25 #include "common.h"
  26
  27 #define CPLD_INT_NETHERNET      (1<<0)
  28 #define CPLD_INTMASK_ETHERNET   (1<<2)
  29 #if defined (CONFIG_MACH_LPD7A400)
  30 # define CPLD_INT_NTOUCH                (1<<1)
  31 # define CPLD_INTMASK_TOUCH     (1<<3)
  32 # define CPLD_INT_PEN           (1<<4)
  33 # define CPLD_INTMASK_PEN       (1<<4)
  34 # define CPLD_INT_PIRQ          (1<<4)
  35 #endif
  36 #define CPLD_INTMASK_CPLD       (1<<7)
  37 #define CPLD_INT_CPLD           (1<<6)
  38
  39 #define CPLD_CONTROL_SWINT              (1<<7) /* Disable all CPLD IRQs */
  40 #define CPLD_CONTROL_OCMSK              (1<<6) /* Mask USB1 connect IRQ */
  41 #define CPLD_CONTROL_PDRV               (1<<5) /* PCC_nDRV high */
  42 #define CPLD_CONTROL_USB1C              (1<<4) /* USB1 connect IRQ active */
  43 #define CPLD_CONTROL_USB1P              (1<<3) /* USB1 power disable */
  44 #define CPLD_CONTROL_AWKP               (1<<2) /* Auto-wakeup disabled  */
  45 #define CPLD_CONTROL_LCD_ENABLE         (1<<1) /* LCD Vee enable */
  46 #define CPLD_CONTROL_WRLAN_NENABLE      (1<<0) /* SMC91x power disable */
  47
  48
  49 static struct resource smc91x_resources[] = {
  50         [0] = {
  51                 .start  = CPLD00_PHYS,
  52                 .end    = CPLD00_PHYS + CPLD00_SIZE - 1, /* Only needs 16B */
  53                 .flags  = IORESOURCE_MEM,
  54         },
  55
  56         [1] = {
  57                 .start  = IRQ_LPD7A40X_ETH_INT,
  58                 .end    = IRQ_LPD7A40X_ETH_INT,
  59                 .flags  = IORESOURCE_IRQ,
  60         },
  61
  62 };
  63
  64 static struct platform_device smc91x_device = {
  65         .name           = "smc91x",
  66         .id             = 0,
  67         .num_resources  = ARRAY_SIZE(smc91x_resources),
  68         .resource       = smc91x_resources,
  69 };
  70
  71 static struct resource lh7a40x_usbclient_resources[] = {
  72         [0] = {
  73                 .start  = USB_PHYS,
  74                 .end    = (USB_PHYS + PAGE_SIZE),
  75                 .flags  = IORESOURCE_MEM,
  76         },
  77         [1] = {
  78                 .start  = IRQ_USB,
  79                 .end    = IRQ_USB,
  80                 .flags  = IORESOURCE_IRQ,
  81         },
  82 };
  83
  84 static u64 lh7a40x_usbclient_dma_mask = 0xffffffffUL;
  85
  86 static struct platform_device lh7a40x_usbclient_device = {
  87 //      .name           = "lh7a40x_udc",
  88         .name           = "lh7-udc",
  89         .id             = 0,
  90         .dev            = {
  91                 .dma_mask = &lh7a40x_usbclient_dma_mask,
  92                 .coherent_dma_mask = 0xffffffffUL,
  93         },
  94         .num_resources  = ARRAY_SIZE (lh7a40x_usbclient_resources),
  95         .resource       = lh7a40x_usbclient_resources,
  96 };
  97
  98 #if defined (CONFIG_ARCH_LH7A404)
  99
 100 static struct resource lh7a404_usbhost_resources [] = {
 101         [0] = {
 102                 .start  = USBH_PHYS,
 103                 .end    = (USBH_PHYS + 0xFF),
 104                 .flags  = IORESOURCE_MEM,
 105         },
 106         [1] = {
 107                 .start  = IRQ_USHINTR,
 108                 .end    = IRQ_USHINTR,
 109                 .flags  = IORESOURCE_IRQ,
 110         },
 111 };
 112
 113 static u64 lh7a404_usbhost_dma_mask = 0xffffffffUL;
 114
 115 static struct platform_device lh7a404_usbhost_device = {
 116         .name           = "lh7a404-ohci",
 117         .id             = 0,
 118         .dev            = {
 119                 .dma_mask = &lh7a404_usbhost_dma_mask,
 120                 .coherent_dma_mask = 0xffffffffUL,
 121         },
 122         .num_resources  = ARRAY_SIZE (lh7a404_usbhost_resources),
 123         .resource       = lh7a404_usbhost_resources,
 124 };
 125
 126 #endif
 127
 128 static struct platform_device* lpd7a40x_devs[] __initdata = {
 129         &smc91x_device,
 130         &lh7a40x_usbclient_device,
 131 #if defined (CONFIG_ARCH_LH7A404)
 132         &lh7a404_usbhost_device,
 133 #endif
 134 };
 135
 136 extern void lpd7a400_map_io (void);
 137
 138 static void __init lpd7a40x_init (void)
 139 {
 140 #if defined (CONFIG_MACH_LPD7A400)
 141         CPLD_CONTROL |= 0
 142                 | CPLD_CONTROL_SWINT /* Disable software interrupt */
 143                 | CPLD_CONTROL_OCMSK; /* Mask USB1 connection IRQ */
 144         CPLD_CONTROL &= ~(0
 145                           | CPLD_CONTROL_LCD_ENABLE     /* Disable LCD */
 146                           | CPLD_CONTROL_WRLAN_NENABLE  /* Enable SMC91x */
 147                 );
 148 #endif
 149
 150 #if defined (CONFIG_MACH_LPD7A404)
 151         CPLD_CONTROL &= ~(0
 152                           | CPLD_CONTROL_WRLAN_NENABLE  /* Enable SMC91x */
 153                 );
 154 #endif
 155
 156         platform_add_devices (lpd7a40x_devs, ARRAY_SIZE (lpd7a40x_devs));
 157 #if defined (CONFIG_FB_ARMCLCD)
 158         lh7a40x_clcd_init ();
 159 #endif
 160 }
 161
 162 static void lh7a40x_ack_cpld_irq (u32 irq)
 163 {
 164         /* CPLD doesn't have ack capability, but some devices may */
 165
 166 #if defined (CPLD_INTMASK_TOUCH)
 167         /* The touch control *must* mask the the interrupt because the
 168          * interrupt bit is read by the driver to determine if the pen
 169          * is still down. */
 170         if (irq == IRQ_TOUCH)
 171                 CPLD_INTERRUPTS |= CPLD_INTMASK_TOUCH;
 172 #endif
 173 }
 174
 175 static void lh7a40x_mask_cpld_irq (u32 irq)
 176 {
 177         switch (irq) {
 178         case IRQ_LPD7A40X_ETH_INT:
 179                 CPLD_INTERRUPTS |= CPLD_INTMASK_ETHERNET;
 180                 break;
 181 #if defined (IRQ_TOUCH)
 182         case IRQ_TOUCH:
 183                 CPLD_INTERRUPTS |= CPLD_INTMASK_TOUCH;
 184                 break;
 185 #endif
 186         }
 187 }
 188
 189 static void lh7a40x_unmask_cpld_irq (u32 irq)
 190 {
 191         switch (irq) {
 192         case IRQ_LPD7A40X_ETH_INT:
 193                 CPLD_INTERRUPTS &= ~CPLD_INTMASK_ETHERNET;
 194                 break;
 195 #if defined (IRQ_TOUCH)
 196         case IRQ_TOUCH:
 197                 CPLD_INTERRUPTS &= ~CPLD_INTMASK_TOUCH;
 198                 break;
 199 #endif
 200         }
 201 }
 202
 203 static struct irq_chip lpd7a40x_cpld_chip = {
 204         .name   = "CPLD",
 205         .ack    = lh7a40x_ack_cpld_irq,
 206         .mask   = lh7a40x_mask_cpld_irq,
 207         .unmask = lh7a40x_unmask_cpld_irq,
 208 };
 209
 210 static void lpd7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc,
 211                                   struct pt_regs *regs)
 212 {
 213         unsigned int mask = CPLD_INTERRUPTS;
 214
 215         desc->chip->ack (irq);
 216
 217         if ((mask & (1<<0)) == 0)       /* WLAN */
 218                 IRQ_DISPATCH (IRQ_LPD7A40X_ETH_INT);
 219
 220 #if defined (IRQ_TOUCH)
 221         if ((mask & (1<<1)) == 0)       /* Touch */
 222                 IRQ_DISPATCH (IRQ_TOUCH);
 223 #endif
 224
 225         desc->chip->unmask (irq); /* Level-triggered need this */
 226 }
 227
 228
 229 void __init lh7a40x_init_board_irq (void)
 230 {
 231         int irq;
 232
 233                 /* Rev A (v2.8): PF0, PF1, PF2, and PF3 are available IRQs.
 234                                  PF7 supports the CPLD.
 235                    Rev B (v3.4): PF0, PF1, and PF2 are available IRQs.
 236                                  PF3 supports the CPLD.
 237                    (Some) LPD7A404 prerelease boards report a version
 238                    number of 0x16, but we force an override since the
 239                    hardware is of the newer variety.
 240                 */
 241
 242         unsigned char cpld_version = CPLD_REVISION;
 243         int pinCPLD = (cpld_version == 0x28) ? 7 : 3;
 244
 245 #if defined CONFIG_MACH_LPD7A404
 246         cpld_version = 0x34;    /* Coerce LPD7A404 to RevB */
 247 #endif
 248
 249                 /* First, configure user controlled GPIOF interrupts  */
 250
 251         GPIO_PFDD       &= ~0x0f; /* PF0-3 are inputs */
 252         GPIO_INTTYPE1   &= ~0x0f; /* PF0-3 are level triggered */
 253         GPIO_INTTYPE2   &= ~0x0f; /* PF0-3 are active low */
 254         barrier ();
 255         GPIO_GPIOFINTEN |=  0x0f; /* Enable PF0, PF1, PF2, and PF3 IRQs */
 256
 257                 /* Then, configure CPLD interrupt */
 258
 259                         /* Disable all CPLD interrupts */
 260 #if defined (CONFIG_MACH_LPD7A400)
 261         CPLD_INTERRUPTS = CPLD_INTMASK_TOUCH | CPLD_INTMASK_PEN
 262                 | CPLD_INTMASK_ETHERNET;
 263         /* *** FIXME: don't know why we need 7 and 4. 7 is way wrong
 264                and 4 is uncefined. */
 265         // (1<<7)|(1<<4)|(1<<3)|(1<<2);
 266 #endif
 267 #if defined (CONFIG_MACH_LPD7A404)
 268         CPLD_INTERRUPTS = CPLD_INTMASK_ETHERNET;
 269         /* *** FIXME: don't know why we need 6 and 5, neither is defined. */
 270         // (1<<6)|(1<<5)|(1<<3);
 271 #endif
 272         GPIO_PFDD       &= ~(1 << pinCPLD); /* Make input */
 273         GPIO_INTTYPE1   &= ~(1 << pinCPLD); /* Level triggered */
 274         GPIO_INTTYPE2   &= ~(1 << pinCPLD); /* Active low */
 275         barrier ();
 276         GPIO_GPIOFINTEN |=  (1 << pinCPLD); /* Enable */
 277
 278                 /* Cascade CPLD interrupts */
 279
 280         for (irq = IRQ_BOARD_START;
 281              irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) {
 282                 set_irq_chip (irq, &lpd7a40x_cpld_chip);
 283                 set_irq_handler (irq, do_level_IRQ);
 284                 set_irq_flags (irq, IRQF_VALID);
 285         }
 286
 287         set_irq_chained_handler ((cpld_version == 0x28)
 288                                  ? IRQ_CPLD_V28
 289                                  : IRQ_CPLD_V34,
 290                                  lpd7a40x_cpld_handler);
 291 }
 292
 293 static struct map_desc lpd7a40x_io_desc[] __initdata = {
 294         {
 295                 .virtual        = IO_VIRT,
 296                 .pfn            = __phys_to_pfn(IO_PHYS),
 297                 .length         = IO_SIZE,
 298                 .type           = MT_DEVICE
 299         },
 300         {       /* Mapping added to work around chip select problems */
 301                 .virtual        = IOBARRIER_VIRT,
 302                 .pfn            = __phys_to_pfn(IOBARRIER_PHYS),
 303                 .length         = IOBARRIER_SIZE,
 304                 .type           = MT_DEVICE
 305         },
 306         {
 307                 .virtual        = CF_VIRT,
 308                 .pfn            = __phys_to_pfn(CF_PHYS),
 309                 .length         = CF_SIZE,
 310                 .type           = MT_DEVICE
 311         },
 312         {
 313                 .virtual        = CPLD02_VIRT,
 314                 .pfn            = __phys_to_pfn(CPLD02_PHYS),
 315                 .length         = CPLD02_SIZE,
 316                 .type           = MT_DEVICE
 317         },
 318         {
 319                 .virtual        = CPLD06_VIRT,
 320                 .pfn            = __phys_to_pfn(CPLD06_PHYS),
 321                 .length         = CPLD06_SIZE,
 322                 .type           = MT_DEVICE
 323         },
 324         {
 325                 .virtual        = CPLD08_VIRT,
 326                 .pfn            = __phys_to_pfn(CPLD08_PHYS),
 327                 .length         = CPLD08_SIZE,
 328                 .type           = MT_DEVICE
 329         },
 330         {
 331                 .virtual        = CPLD08_VIRT,
 332                 .pfn            = __phys_to_pfn(CPLD08_PHYS),
 333                 .length         = CPLD08_SIZE,
 334                 .type           = MT_DEVICE
 335         },
 336         {
 337                 .virtual        = CPLD0A_VIRT,
 338                 .pfn            = __phys_to_pfn(CPLD0A_PHYS),
 339                 .length         = CPLD0A_SIZE,
 340                 .type           = MT_DEVICE
 341         },
 342         {
 343                 .virtual        = CPLD0C_VIRT,
 344                 .pfn            = __phys_to_pfn(CPLD0C_PHYS),
 345                 .length         = CPLD0C_SIZE,
 346                 .type           = MT_DEVICE
 347         },
 348         {
 349                 .virtual        = CPLD0E_VIRT,
 350                 .pfn            = __phys_to_pfn(CPLD0E_PHYS),
 351                 .length         = CPLD0E_SIZE,
 352                 .type           = MT_DEVICE
 353         },
 354         {
 355                 .virtual        = CPLD10_VIRT,
 356                 .pfn            = __phys_to_pfn(CPLD10_PHYS),
 357                 .length         = CPLD10_SIZE,
 358                 .type           = MT_DEVICE
 359         },
 360         {
 361                 .virtual        = CPLD12_VIRT,
 362                 .pfn            = __phys_to_pfn(CPLD12_PHYS),
 363                 .length         = CPLD12_SIZE,
 364                 .type           = MT_DEVICE
 365         },
 366         {
 367                 .virtual        = CPLD14_VIRT,
 368                 .pfn            = __phys_to_pfn(CPLD14_PHYS),
 369                 .length         = CPLD14_SIZE,
 370                 .type           = MT_DEVICE
 371         },
 372         {
 373                 .virtual        = CPLD16_VIRT,
 374                 .pfn            = __phys_to_pfn(CPLD16_PHYS),
 375                 .length         = CPLD16_SIZE,
 376                 .type           = MT_DEVICE
 377         },
 378         {
 379                 .virtual        = CPLD18_VIRT,
 380                 .pfn            = __phys_to_pfn(CPLD18_PHYS),
 381                 .length         = CPLD18_SIZE,
 382                 .type           = MT_DEVICE
 383         },
 384         {
 385                 .virtual        = CPLD1A_VIRT,
 386                 .pfn            = __phys_to_pfn(CPLD1A_PHYS),
 387                 .length         = CPLD1A_SIZE,
 388                 .type           = MT_DEVICE
 389         },
 390 };
 391
 392 void __init
 393 lpd7a40x_map_io(void)
 394 {
 395         iotable_init (lpd7a40x_io_desc, ARRAY_SIZE (lpd7a40x_io_desc));
 396 }
 397
 398 #ifdef CONFIG_MACH_LPD7A400
 399
 400 MACHINE_START (LPD7A400, "Logic Product Development LPD7A400-10")
 401         /* Maintainer: Marc Singer */
 402         .phys_io        = 0x80000000,
 403         .io_pg_offst    = ((io_p2v (0x80000000))>>18) & 0xfffc,
 404         .boot_params    = 0xc0000100,
 405         .map_io         = lpd7a40x_map_io,
 406         .init_irq       = lh7a400_init_irq,
 407         .timer          = &lh7a40x_timer,
 408         .init_machine   = lpd7a40x_init,
 409 MACHINE_END
 410
 411 #endif
 412
 413 #ifdef CONFIG_MACH_LPD7A404
 414
 415 MACHINE_START (LPD7A404, "Logic Product Development LPD7A404-10")
 416         /* Maintainer: Marc Singer */
 417         .phys_io        = 0x80000000,
 418         .io_pg_offst    = ((io_p2v (0x80000000))>>18) & 0xfffc,
 419         .boot_params    = 0xc0000100,
 420         .map_io         = lpd7a40x_map_io,
 421         .init_irq       = lh7a404_init_irq,
 422         .timer          = &lh7a40x_timer,
 423         .init_machine   = lpd7a40x_init,
 424 MACHINE_END
 425
 426 #endif