arch/arm/mach-ixp4xx/common.c

   1 /*
   2  * arch/arm/mach-ixp4xx/common.c
   3  *
   4  * Generic code shared across all IXP4XX platforms
   5  *
   6  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright 2002 (c) Intel Corporation
   9  * Copyright 2003-2004 (c) MontaVista, Software, Inc.
  10  *
  11  * This file is licensed under  the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/mm.h>
  18 #include <linux/init.h>
  19 #include <linux/serial.h>
  20 #include <linux/sched.h>
  21 #include <linux/tty.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/serial_core.h>
  24 #include <linux/bootmem.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/bitops.h>
  27 #include <linux/time.h>
  28 #include <linux/timex.h>
  29
  30 #include <asm/hardware.h>
  31 #include <asm/uaccess.h>
  32 #include <asm/io.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/page.h>
  35 #include <asm/irq.h>
  36
  37 #include <asm/mach/map.h>
  38 #include <asm/mach/irq.h>
  39 #include <asm/mach/time.h>
  40
  41 /*************************************************************************
  42  * IXP4xx chipset I/O mapping
  43  *************************************************************************/
  44 static struct map_desc ixp4xx_io_desc[] __initdata = {
  45         {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
  46                 .virtual        = IXP4XX_PERIPHERAL_BASE_VIRT,
  47                 .pfn            = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
  48                 .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
  49                 .type           = MT_DEVICE
  50         }, {    /* Expansion Bus Config Registers */
  51                 .virtual        = IXP4XX_EXP_CFG_BASE_VIRT,
  52                 .pfn            = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
  53                 .length         = IXP4XX_EXP_CFG_REGION_SIZE,
  54                 .type           = MT_DEVICE
  55         }, {    /* PCI Registers */
  56                 .virtual        = IXP4XX_PCI_CFG_BASE_VIRT,
  57                 .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
  58                 .length         = IXP4XX_PCI_CFG_REGION_SIZE,
  59                 .type           = MT_DEVICE
  60         },
  61 #ifdef CONFIG_DEBUG_LL
  62         {       /* Debug UART mapping */
  63                 .virtual        = IXP4XX_DEBUG_UART_BASE_VIRT,
  64                 .pfn            = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
  65                 .length         = IXP4XX_DEBUG_UART_REGION_SIZE,
  66                 .type           = MT_DEVICE
  67         }
  68 #endif
  69 };
  70
  71 void __init ixp4xx_map_io(void)
  72 {
  73         iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
  74 }
  75
  76
  77 /*************************************************************************
  78  * IXP4xx chipset IRQ handling
  79  *
  80  * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
  81  *       (be it PCI or something else) configures that GPIO line
  82  *       as an IRQ.
  83  **************************************************************************/
  84 enum ixp4xx_irq_type {
  85         IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
  86 };
  87
  88 static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type);
  89
  90 /*
  91  * IRQ -> GPIO mapping table
  92  */
  93 static signed char irq2gpio[32] = {
  94         -1, -1, -1, -1, -1, -1,  0,  1,
  95         -1, -1, -1, -1, -1, -1, -1, -1,
  96         -1, -1, -1,  2,  3,  4,  5,  6,
  97          7,  8,  9, 10, 11, 12, -1, -1,
  98 };
  99
 100 static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
 101 {
 102         int line = irq2gpio[irq];
 103         u32 int_style;
 104         enum ixp4xx_irq_type irq_type;
 105         volatile u32 *int_reg;
 106
 107         /*
 108          * Only for GPIO IRQs
 109          */
 110         if (line < 0)
 111                 return -EINVAL;
 112
 113         switch (type){
 114         case IRQT_BOTHEDGE:
 115                 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
 116                 irq_type = IXP4XX_IRQ_EDGE;
 117                 break;
 118         case IRQT_RISING:
 119                 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
 120                 irq_type = IXP4XX_IRQ_EDGE;
 121                 break;
 122         case IRQT_FALLING:
 123                 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
 124                 irq_type = IXP4XX_IRQ_EDGE;
 125                 break;
 126         case IRQT_HIGH:
 127                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
 128                 irq_type = IXP4XX_IRQ_LEVEL;
 129                 break;
 130         case IRQT_LOW:
 131                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
 132                 irq_type = IXP4XX_IRQ_LEVEL;
 133                 break;
 134         default:
 135                 return -EINVAL;
 136         }
 137         ixp4xx_config_irq(irq, irq_type);
 138
 139         if (line >= 8) {        /* pins 8-15 */
 140                 line -= 8;
 141                 int_reg = IXP4XX_GPIO_GPIT2R;
 142         } else {                /* pins 0-7 */
 143                 int_reg = IXP4XX_GPIO_GPIT1R;
 144         }
 145
 146         /* Clear the style for the appropriate pin */
 147         *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
 148                         (line * IXP4XX_GPIO_STYLE_SIZE));
 149
 150         *IXP4XX_GPIO_GPISR = (1 << line);
 151
 152         /* Set the new style */
 153         *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
 154
 155         /* Configure the line as an input */
 156         gpio_line_config(line, IXP4XX_GPIO_IN);
 157
 158         return 0;
 159 }
 160
 161 static void ixp4xx_irq_mask(unsigned int irq)
 162 {
 163         if (cpu_is_ixp46x() && irq >= 32)
 164                 *IXP4XX_ICMR2 &= ~(1 << (irq - 32));
 165         else
 166                 *IXP4XX_ICMR &= ~(1 << irq);
 167 }
 168
 169 static void ixp4xx_irq_unmask(unsigned int irq)
 170 {
 171         if (cpu_is_ixp46x() && irq >= 32)
 172                 *IXP4XX_ICMR2 |= (1 << (irq - 32));
 173         else
 174                 *IXP4XX_ICMR |= (1 << irq);
 175 }
 176
 177 static void ixp4xx_irq_ack(unsigned int irq)
 178 {
 179         int line = (irq < 32) ? irq2gpio[irq] : -1;
 180
 181         if (line >= 0)
 182                 *IXP4XX_GPIO_GPISR = (1 << line);
 183 }
 184
 185 /*
 186  * Level triggered interrupts on GPIO lines can only be cleared when the
 187  * interrupt condition disappears.
 188  */
 189 static void ixp4xx_irq_level_unmask(unsigned int irq)
 190 {
 191         ixp4xx_irq_ack(irq);
 192         ixp4xx_irq_unmask(irq);
 193 }
 194
 195 static struct irqchip ixp4xx_irq_level_chip = {
 196         .ack            = ixp4xx_irq_mask,
 197         .mask           = ixp4xx_irq_mask,
 198         .unmask         = ixp4xx_irq_level_unmask,
 199         .set_type       = ixp4xx_set_irq_type,
 200 };
 201
 202 static struct irqchip ixp4xx_irq_edge_chip = {
 203         .ack            = ixp4xx_irq_ack,
 204         .mask           = ixp4xx_irq_mask,
 205         .unmask         = ixp4xx_irq_unmask,
 206         .set_type       = ixp4xx_set_irq_type,
 207 };
 208
 209 static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type)
 210 {
 211         switch (type) {
 212         case IXP4XX_IRQ_LEVEL:
 213                 set_irq_chip(irq, &ixp4xx_irq_level_chip);
 214                 set_irq_handler(irq, do_level_IRQ);
 215                 break;
 216         case IXP4XX_IRQ_EDGE:
 217                 set_irq_chip(irq, &ixp4xx_irq_edge_chip);
 218                 set_irq_handler(irq, do_edge_IRQ);
 219                 break;
 220         }
 221         set_irq_flags(irq, IRQF_VALID);
 222 }
 223
 224 void __init ixp4xx_init_irq(void)
 225 {
 226         int i = 0;
 227
 228         /* Route all sources to IRQ instead of FIQ */
 229         *IXP4XX_ICLR = 0x0;
 230
 231         /* Disable all interrupt */
 232         *IXP4XX_ICMR = 0x0;
 233
 234         if (cpu_is_ixp46x()) {
 235                 /* Route upper 32 sources to IRQ instead of FIQ */
 236                 *IXP4XX_ICLR2 = 0x00;
 237
 238                 /* Disable upper 32 interrupts */
 239                 *IXP4XX_ICMR2 = 0x00;
 240         }
 241
 242         /* Default to all level triggered */
 243         for(i = 0; i < NR_IRQS; i++)
 244                 ixp4xx_config_irq(i, IXP4XX_IRQ_LEVEL);
 245 }
 246
 247
 248 /*************************************************************************
 249  * IXP4xx timer tick
 250  * We use OS timer1 on the CPU for the timer tick and the timestamp
 251  * counter as a source of real clock ticks to account for missed jiffies.
 252  *************************************************************************/
 253
 254 static unsigned volatile last_jiffy_time;
 255
 256 #define CLOCK_TICKS_PER_USEC    ((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
 257
 258 /* IRQs are disabled before entering here from do_gettimeofday() */
 259 static unsigned long ixp4xx_gettimeoffset(void)
 260 {
 261         u32 elapsed;
 262
 263         elapsed = *IXP4XX_OSTS - last_jiffy_time;
 264
 265         return elapsed / CLOCK_TICKS_PER_USEC;
 266 }
 267
 268 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 269 {
 270         write_seqlock(&xtime_lock);
 271
 272         /* Clear Pending Interrupt by writing '1' to it */
 273         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 274
 275         /*
 276          * Catch up with the real idea of time
 277          */
 278         while ((signed long)(*IXP4XX_OSTS - last_jiffy_time) >= LATCH) {
 279                 timer_tick(regs);
 280                 last_jiffy_time += LATCH;
 281         }
 282
 283         write_sequnlock(&xtime_lock);
 284
 285         return IRQ_HANDLED;
 286 }
 287
 288 static struct irqaction ixp4xx_timer_irq = {
 289         .name           = "IXP4xx Timer Tick",
 290         .flags          = IRQF_DISABLED | IRQF_TIMER,
 291         .handler        = ixp4xx_timer_interrupt,
 292 };
 293
 294 static void __init ixp4xx_timer_init(void)
 295 {
 296         /* Clear Pending Interrupt by writing '1' to it */
 297         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 298
 299         /* Setup the Timer counter value */
 300         *IXP4XX_OSRT1 = (LATCH & ~IXP4XX_OST_RELOAD_MASK) | IXP4XX_OST_ENABLE;
 301
 302         /* Reset time-stamp counter */
 303         *IXP4XX_OSTS = 0;
 304         last_jiffy_time = 0;
 305
 306         /* Connect the interrupt handler and enable the interrupt */
 307         setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
 308 }
 309
 310 struct sys_timer ixp4xx_timer = {
 311         .init           = ixp4xx_timer_init,
 312         .offset         = ixp4xx_gettimeoffset,
 313 };
 314
 315 static struct resource ixp46x_i2c_resources[] = {
 316         [0] = {
 317                 .start  = 0xc8011000,
 318                 .end    = 0xc801101c,
 319                 .flags  = IORESOURCE_MEM,
 320         },
 321         [1] = {
 322                 .start  = IRQ_IXP4XX_I2C,
 323                 .end    = IRQ_IXP4XX_I2C,
 324                 .flags  = IORESOURCE_IRQ
 325         }
 326 };
 327
 328 /*
 329  * I2C controller. The IXP46x uses the same block as the IOP3xx, so
 330  * we just use the same device name.
 331  */
 332 static struct platform_device ixp46x_i2c_controller = {
 333         .name           = "IOP3xx-I2C",
 334         .id             = 0,
 335         .num_resources  = 2,
 336         .resource       = ixp46x_i2c_resources
 337 };
 338
 339 static struct platform_device *ixp46x_devices[] __initdata = {
 340         &ixp46x_i2c_controller
 341 };
 342
 343 unsigned long ixp4xx_exp_bus_size;
 344 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
 345
 346 void __init ixp4xx_sys_init(void)
 347 {
 348         ixp4xx_exp_bus_size = SZ_16M;
 349
 350         if (cpu_is_ixp46x()) {
 351                 int region;
 352
 353                 platform_add_devices(ixp46x_devices,
 354                                 ARRAY_SIZE(ixp46x_devices));
 355
 356                 for (region = 0; region < 7; region++) {
 357                         if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
 358                                 ixp4xx_exp_bus_size = SZ_32M;
 359                                 break;
 360                         }
 361                 }
 362         }
 363
 364         printk("IXP4xx: Using %luMiB expansion bus window size\n",
 365                         ixp4xx_exp_bus_size >> 20);
 366 }
 367