arch/arm/mach-integrator/integrator_cp.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_cp.c
   3  *
   4  *  Copyright (C) 2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License.
   9  */
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/list.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/slab.h>
  17 #include <linux/string.h>
  18 #include <linux/sysdev.h>
  19 #include <linux/amba/bus.h>
  20 #include <linux/amba/kmi.h>
  21 #include <linux/amba/clcd.h>
  22
  23 #include <asm/hardware.h>
  24 #include <asm/io.h>
  25 #include <asm/irq.h>
  26 #include <asm/setup.h>
  27 #include <asm/mach-types.h>
  28 #include <asm/hardware/icst525.h>
  29
  30 #include <asm/arch/cm.h>
  31 #include <asm/arch/lm.h>
  32
  33 #include <asm/mach/arch.h>
  34 #include <asm/mach/flash.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/mach/mmc.h>
  37 #include <asm/mach/map.h>
  38 #include <asm/mach/time.h>
  39
  40 #include "common.h"
  41 #include "clock.h"
  42
  43 #define INTCP_PA_MMC_BASE               0x1c000000
  44 #define INTCP_PA_AACI_BASE              0x1d000000
  45
  46 #define INTCP_PA_FLASH_BASE             0x24000000
  47 #define INTCP_FLASH_SIZE                SZ_32M
  48
  49 #define INTCP_PA_CLCD_BASE              0xc0000000
  50
  51 #define INTCP_VA_CIC_BASE               0xf1000040
  52 #define INTCP_VA_PIC_BASE               0xf1400000
  53 #define INTCP_VA_SIC_BASE               0xfca00000
  54
  55 #define INTCP_PA_ETH_BASE               0xc8000000
  56 #define INTCP_ETH_SIZE                  0x10
  57
  58 #define INTCP_VA_CTRL_BASE              0xfcb00000
  59 #define INTCP_FLASHPROG                 0x04
  60 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
  61 #define CINTEGRATOR_FLASHPROG_FLWREN    (1 << 1)
  62
  63 /*
  64  * Logical      Physical
  65  * f1000000     10000000        Core module registers
  66  * f1100000     11000000        System controller registers
  67  * f1200000     12000000        EBI registers
  68  * f1300000     13000000        Counter/Timer
  69  * f1400000     14000000        Interrupt controller
  70  * f1600000     16000000        UART 0
  71  * f1700000     17000000        UART 1
  72  * f1a00000     1a000000        Debug LEDs
  73  * f1b00000     1b000000        GPIO
  74  */
  75
  76 static struct map_desc intcp_io_desc[] __initdata = {
  77         {
  78                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
  79                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
  80                 .length         = SZ_4K,
  81                 .type           = MT_DEVICE
  82         }, {
  83                 .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
  84                 .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
  85                 .length         = SZ_4K,
  86                 .type           = MT_DEVICE
  87         }, {
  88                 .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
  89                 .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
  90                 .length         = SZ_4K,
  91                 .type           = MT_DEVICE
  92         }, {
  93                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
  94                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
  95                 .length         = SZ_4K,
  96                 .type           = MT_DEVICE
  97         }, {
  98                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
  99                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
 100                 .length         = SZ_4K,
 101                 .type           = MT_DEVICE
 102         }, {
 103                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
 104                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
 105                 .length         = SZ_4K,
 106                 .type           = MT_DEVICE
 107         }, {
 108                 .virtual        = IO_ADDRESS(INTEGRATOR_UART1_BASE),
 109                 .pfn            = __phys_to_pfn(INTEGRATOR_UART1_BASE),
 110                 .length         = SZ_4K,
 111                 .type           = MT_DEVICE
 112         }, {
 113                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
 114                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
 115                 .length         = SZ_4K,
 116                 .type           = MT_DEVICE
 117         }, {
 118                 .virtual        = IO_ADDRESS(INTEGRATOR_GPIO_BASE),
 119                 .pfn            = __phys_to_pfn(INTEGRATOR_GPIO_BASE),
 120                 .length         = SZ_4K,
 121                 .type           = MT_DEVICE
 122         }, {
 123                 .virtual        = 0xfca00000,
 124                 .pfn            = __phys_to_pfn(0xca000000),
 125                 .length         = SZ_4K,
 126                 .type           = MT_DEVICE
 127         }, {
 128                 .virtual        = 0xfcb00000,
 129                 .pfn            = __phys_to_pfn(0xcb000000),
 130                 .length         = SZ_4K,
 131                 .type           = MT_DEVICE
 132         }
 133 };
 134
 135 static void __init intcp_map_io(void)
 136 {
 137         iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
 138 }
 139
 140 #define cic_writel      __raw_writel
 141 #define cic_readl       __raw_readl
 142 #define pic_writel      __raw_writel
 143 #define pic_readl       __raw_readl
 144 #define sic_writel      __raw_writel
 145 #define sic_readl       __raw_readl
 146
 147 static void cic_mask_irq(unsigned int irq)
 148 {
 149         irq -= IRQ_CIC_START;
 150         cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
 151 }
 152
 153 static void cic_unmask_irq(unsigned int irq)
 154 {
 155         irq -= IRQ_CIC_START;
 156         cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
 157 }
 158
 159 static struct irqchip cic_chip = {
 160         .ack    = cic_mask_irq,
 161         .mask   = cic_mask_irq,
 162         .unmask = cic_unmask_irq,
 163 };
 164
 165 static void pic_mask_irq(unsigned int irq)
 166 {
 167         irq -= IRQ_PIC_START;
 168         pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
 169 }
 170
 171 static void pic_unmask_irq(unsigned int irq)
 172 {
 173         irq -= IRQ_PIC_START;
 174         pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
 175 }
 176
 177 static struct irqchip pic_chip = {
 178         .ack    = pic_mask_irq,
 179         .mask   = pic_mask_irq,
 180         .unmask = pic_unmask_irq,
 181 };
 182
 183 static void sic_mask_irq(unsigned int irq)
 184 {
 185         irq -= IRQ_SIC_START;
 186         sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
 187 }
 188
 189 static void sic_unmask_irq(unsigned int irq)
 190 {
 191         irq -= IRQ_SIC_START;
 192         sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
 193 }
 194
 195 static struct irqchip sic_chip = {
 196         .ack    = sic_mask_irq,
 197         .mask   = sic_mask_irq,
 198         .unmask = sic_unmask_irq,
 199 };
 200
 201 static void
 202 sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
 203 {
 204         unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
 205
 206         if (status == 0) {
 207                 do_bad_IRQ(irq, desc, regs);
 208                 return;
 209         }
 210
 211         do {
 212                 irq = ffs(status) - 1;
 213                 status &= ~(1 << irq);
 214
 215                 irq += IRQ_SIC_START;
 216
 217                 desc = irq_desc + irq;
 218                 desc_handle_irq(irq, desc, regs);
 219         } while (status);
 220 }
 221
 222 static void __init intcp_init_irq(void)
 223 {
 224         unsigned int i;
 225
 226         /*
 227          * Disable all interrupt sources
 228          */
 229         pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
 230         pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
 231
 232         for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
 233                 if (i == 11)
 234                         i = 22;
 235                 if (i == 29)
 236                         break;
 237                 set_irq_chip(i, &pic_chip);
 238                 set_irq_handler(i, do_level_IRQ);
 239                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 240         }
 241
 242         cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
 243         cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
 244
 245         for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
 246                 set_irq_chip(i, &cic_chip);
 247                 set_irq_handler(i, do_level_IRQ);
 248                 set_irq_flags(i, IRQF_VALID);
 249         }
 250
 251         sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
 252         sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
 253
 254         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
 255                 set_irq_chip(i, &sic_chip);
 256                 set_irq_handler(i, do_level_IRQ);
 257                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 258         }
 259
 260         set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
 261 }
 262
 263 /*
 264  * Clock handling
 265  */
 266 #define CM_LOCK (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
 267 #define CM_AUXOSC (IO_ADDRESS(INTEGRATOR_HDR_BASE)+0x1c)
 268
 269 static const struct icst525_params cp_auxvco_params = {
 270         .ref            = 24000,
 271         .vco_max        = 320000,
 272         .vd_min         = 8,
 273         .vd_max         = 263,
 274         .rd_min         = 3,
 275         .rd_max         = 65,
 276 };
 277
 278 static void cp_auxvco_set(struct clk *clk, struct icst525_vco vco)
 279 {
 280         u32 val;
 281
 282         val = readl(CM_AUXOSC) & ~0x7ffff;
 283         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 284
 285         writel(0xa05f, CM_LOCK);
 286         writel(val, CM_AUXOSC);
 287         writel(0, CM_LOCK);
 288 }
 289
 290 static struct clk cp_clcd_clk = {
 291         .name   = "CLCDCLK",
 292         .params = &cp_auxvco_params,
 293         .setvco = cp_auxvco_set,
 294 };
 295
 296 static struct clk cp_mmci_clk = {
 297         .name   = "MCLK",
 298         .rate   = 14745600,
 299 };
 300
 301 /*
 302  * Flash handling.
 303  */
 304 static int intcp_flash_init(void)
 305 {
 306         u32 val;
 307
 308         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 309         val |= CINTEGRATOR_FLASHPROG_FLWREN;
 310         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 311
 312         return 0;
 313 }
 314
 315 static void intcp_flash_exit(void)
 316 {
 317         u32 val;
 318
 319         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 320         val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
 321         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 322 }
 323
 324 static void intcp_flash_set_vpp(int on)
 325 {
 326         u32 val;
 327
 328         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 329         if (on)
 330                 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
 331         else
 332                 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
 333         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 334 }
 335
 336 static struct flash_platform_data intcp_flash_data = {
 337         .map_name       = "cfi_probe",
 338         .width          = 4,
 339         .init           = intcp_flash_init,
 340         .exit           = intcp_flash_exit,
 341         .set_vpp        = intcp_flash_set_vpp,
 342 };
 343
 344 static struct resource intcp_flash_resource = {
 345         .start          = INTCP_PA_FLASH_BASE,
 346         .end            = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
 347         .flags          = IORESOURCE_MEM,
 348 };
 349
 350 static struct platform_device intcp_flash_device = {
 351         .name           = "armflash",
 352         .id             = 0,
 353         .dev            = {
 354                 .platform_data  = &intcp_flash_data,
 355         },
 356         .num_resources  = 1,
 357         .resource       = &intcp_flash_resource,
 358 };
 359
 360 static struct resource smc91x_resources[] = {
 361         [0] = {
 362                 .start  = INTCP_PA_ETH_BASE,
 363                 .end    = INTCP_PA_ETH_BASE + INTCP_ETH_SIZE - 1,
 364                 .flags  = IORESOURCE_MEM,
 365         },
 366         [1] = {
 367                 .start  = IRQ_CP_ETHINT,
 368                 .end    = IRQ_CP_ETHINT,
 369                 .flags  = IORESOURCE_IRQ,
 370         },
 371 };
 372
 373 static struct platform_device smc91x_device = {
 374         .name           = "smc91x",
 375         .id             = 0,
 376         .num_resources  = ARRAY_SIZE(smc91x_resources),
 377         .resource       = smc91x_resources,
 378 };
 379
 380 static struct platform_device *intcp_devs[] __initdata = {
 381         &intcp_flash_device,
 382         &smc91x_device,
 383 };
 384
 385 /*
 386  * It seems that the card insertion interrupt remains active after
 387  * we've acknowledged it.  We therefore ignore the interrupt, and
 388  * rely on reading it from the SIC.  This also means that we must
 389  * clear the latched interrupt.
 390  */
 391 static unsigned int mmc_status(struct device *dev)
 392 {
 393         unsigned int status = readl(0xfca00004);
 394         writel(8, 0xfcb00008);
 395
 396         return status & 8;
 397 }
 398
 399 static struct mmc_platform_data mmc_data = {
 400         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 401         .status         = mmc_status,
 402 };
 403
 404 static struct amba_device mmc_device = {
 405         .dev            = {
 406                 .bus_id = "mb:1c",
 407                 .platform_data = &mmc_data,
 408         },
 409         .res            = {
 410                 .start  = INTCP_PA_MMC_BASE,
 411                 .end    = INTCP_PA_MMC_BASE + SZ_4K - 1,
 412                 .flags  = IORESOURCE_MEM,
 413         },
 414         .irq            = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
 415         .periphid       = 0,
 416 };
 417
 418 static struct amba_device aaci_device = {
 419         .dev            = {
 420                 .bus_id = "mb:1d",
 421         },
 422         .res            = {
 423                 .start  = INTCP_PA_AACI_BASE,
 424                 .end    = INTCP_PA_AACI_BASE + SZ_4K - 1,
 425                 .flags  = IORESOURCE_MEM,
 426         },
 427         .irq            = { IRQ_CP_AACIINT, NO_IRQ },
 428         .periphid       = 0,
 429 };
 430
 431
 432 /*
 433  * CLCD support
 434  */
 435 static struct clcd_panel vga = {
 436         .mode           = {
 437                 .name           = "VGA",
 438                 .refresh        = 60,
 439                 .xres           = 640,
 440                 .yres           = 480,
 441                 .pixclock       = 39721,
 442                 .left_margin    = 40,
 443                 .right_margin   = 24,
 444                 .upper_margin   = 32,
 445                 .lower_margin   = 11,
 446                 .hsync_len      = 96,
 447                 .vsync_len      = 2,
 448                 .sync           = 0,
 449                 .vmode          = FB_VMODE_NONINTERLACED,
 450         },
 451         .width          = -1,
 452         .height         = -1,
 453         .tim2           = TIM2_BCD | TIM2_IPC,
 454         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 455         .bpp            = 16,
 456         .grayscale      = 0,
 457 };
 458
 459 /*
 460  * Ensure VGA is selected.
 461  */
 462 static void cp_clcd_enable(struct clcd_fb *fb)
 463 {
 464         u32 val;
 465
 466         if (fb->fb.var.bits_per_pixel <= 8)
 467                 val = CM_CTRL_LCDMUXSEL_VGA_8421BPP;
 468         else if (fb->fb.var.bits_per_pixel <= 16)
 469                 val = CM_CTRL_LCDMUXSEL_VGA_16BPP
 470                         | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1
 471                         | CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
 472         else
 473                 val = 0; /* no idea for this, don't trust the docs */
 474
 475         cm_control(CM_CTRL_LCDMUXSEL_MASK|
 476                    CM_CTRL_LCDEN0|
 477                    CM_CTRL_LCDEN1|
 478                    CM_CTRL_STATIC1|
 479                    CM_CTRL_STATIC2|
 480                    CM_CTRL_STATIC|
 481                    CM_CTRL_n24BITEN, val);
 482 }
 483
 484 static unsigned long framesize = SZ_1M;
 485
 486 static int cp_clcd_setup(struct clcd_fb *fb)
 487 {
 488         dma_addr_t dma;
 489
 490         fb->panel = &vga;
 491
 492         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 493                                                     &dma, GFP_KERNEL);
 494         if (!fb->fb.screen_base) {
 495                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 496                 return -ENOMEM;
 497         }
 498
 499         fb->fb.fix.smem_start   = dma;
 500         fb->fb.fix.smem_len     = framesize;
 501
 502         return 0;
 503 }
 504
 505 static int cp_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 506 {
 507         return dma_mmap_writecombine(&fb->dev->dev, vma,
 508                                      fb->fb.screen_base,
 509                                      fb->fb.fix.smem_start,
 510                                      fb->fb.fix.smem_len);
 511 }
 512
 513 static void cp_clcd_remove(struct clcd_fb *fb)
 514 {
 515         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 516                               fb->fb.screen_base, fb->fb.fix.smem_start);
 517 }
 518
 519 static struct clcd_board clcd_data = {
 520         .name           = "Integrator/CP",
 521         .check          = clcdfb_check,
 522         .decode         = clcdfb_decode,
 523         .enable         = cp_clcd_enable,
 524         .setup          = cp_clcd_setup,
 525         .mmap           = cp_clcd_mmap,
 526         .remove         = cp_clcd_remove,
 527 };
 528
 529 static struct amba_device clcd_device = {
 530         .dev            = {
 531                 .bus_id = "mb:c0",
 532                 .coherent_dma_mask = ~0,
 533                 .platform_data = &clcd_data,
 534         },
 535         .res            = {
 536                 .start  = INTCP_PA_CLCD_BASE,
 537                 .end    = INTCP_PA_CLCD_BASE + SZ_4K - 1,
 538                 .flags  = IORESOURCE_MEM,
 539         },
 540         .dma_mask       = ~0,
 541         .irq            = { IRQ_CP_CLCDCINT, NO_IRQ },
 542         .periphid       = 0,
 543 };
 544
 545 static struct amba_device *amba_devs[] __initdata = {
 546         &mmc_device,
 547         &aaci_device,
 548         &clcd_device,
 549 };
 550
 551 static void __init intcp_init(void)
 552 {
 553         int i;
 554
 555         clk_register(&cp_clcd_clk);
 556         clk_register(&cp_mmci_clk);
 557
 558         platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
 559
 560         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 561                 struct amba_device *d = amba_devs[i];
 562                 amba_device_register(d, &iomem_resource);
 563         }
 564 }
 565
 566 #define TIMER_CTRL_IE   (1 << 5)                        /* Interrupt Enable */
 567
 568 static void __init intcp_timer_init(void)
 569 {
 570         integrator_time_init(1000000 / HZ, TIMER_CTRL_IE);
 571 }
 572
 573 static struct sys_timer cp_timer = {
 574         .init           = intcp_timer_init,
 575         .offset         = integrator_gettimeoffset,
 576 };
 577
 578 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
 579         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 580         .phys_io        = 0x16000000,
 581         .io_pg_offst    = ((0xf1600000) >> 18) & 0xfffc,
 582         .boot_params    = 0x00000100,
 583         .map_io         = intcp_map_io,
 584         .init_irq       = intcp_init_irq,
 585         .timer          = &cp_timer,
 586         .init_machine   = intcp_init,
 587 MACHINE_END