arch/arm/mach-exynos4/dev-sysmmu.c

   1 /* linux/arch/arm/mach-exynos4/dev-sysmmu.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * EXYNOS4 - System MMU support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/dma-mapping.h>
  15
  16 #include <mach/map.h>
  17 #include <mach/irqs.h>
  18 #include <mach/sysmmu.h>
  19 #include <plat/s5p-clock.h>
  20
  21 /* These names must be equal to the clock names in mach-exynos4/clock.c */
  22 const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM] = {
  23         "SYSMMU_MDMA"   ,
  24         "SYSMMU_SSS"    ,
  25         "SYSMMU_FIMC0"  ,
  26         "SYSMMU_FIMC1"  ,
  27         "SYSMMU_FIMC2"  ,
  28         "SYSMMU_FIMC3"  ,
  29         "SYSMMU_JPEG"   ,
  30         "SYSMMU_FIMD0"  ,
  31         "SYSMMU_FIMD1"  ,
  32         "SYSMMU_PCIe"   ,
  33         "SYSMMU_G2D"    ,
  34         "SYSMMU_ROTATOR",
  35         "SYSMMU_MDMA2"  ,
  36         "SYSMMU_TV"     ,
  37         "SYSMMU_MFC_L"  ,
  38         "SYSMMU_MFC_R"  ,
  39 };
  40
  41 static struct resource exynos4_sysmmu_resource[] = {
  42         [0] = {
  43                 .start  = EXYNOS4_PA_SYSMMU_MDMA,
  44                 .end    = EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1,
  45                 .flags  = IORESOURCE_MEM,
  46         },
  47         [1] = {
  48                 .start  = IRQ_SYSMMU_MDMA0_0,
  49                 .end    = IRQ_SYSMMU_MDMA0_0,
  50                 .flags  = IORESOURCE_IRQ,
  51         },
  52         [2] = {
  53                 .start  = EXYNOS4_PA_SYSMMU_SSS,
  54                 .end    = EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1,
  55                 .flags  = IORESOURCE_MEM,
  56         },
  57         [3] = {
  58                 .start  = IRQ_SYSMMU_SSS_0,
  59                 .end    = IRQ_SYSMMU_SSS_0,
  60                 .flags  = IORESOURCE_IRQ,
  61         },
  62         [4] = {
  63                 .start  = EXYNOS4_PA_SYSMMU_FIMC0,
  64                 .end    = EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1,
  65                 .flags  = IORESOURCE_MEM,
  66         },
  67         [5] = {
  68                 .start  = IRQ_SYSMMU_FIMC0_0,
  69                 .end    = IRQ_SYSMMU_FIMC0_0,
  70                 .flags  = IORESOURCE_IRQ,
  71         },
  72         [6] = {
  73                 .start  = EXYNOS4_PA_SYSMMU_FIMC1,
  74                 .end    = EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1,
  75                 .flags  = IORESOURCE_MEM,
  76         },
  77         [7] = {
  78                 .start  = IRQ_SYSMMU_FIMC1_0,
  79                 .end    = IRQ_SYSMMU_FIMC1_0,
  80                 .flags  = IORESOURCE_IRQ,
  81         },
  82         [8] = {
  83                 .start  = EXYNOS4_PA_SYSMMU_FIMC2,
  84                 .end    = EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1,
  85                 .flags  = IORESOURCE_MEM,
  86         },
  87         [9] = {
  88                 .start  = IRQ_SYSMMU_FIMC2_0,
  89                 .end    = IRQ_SYSMMU_FIMC2_0,
  90                 .flags  = IORESOURCE_IRQ,
  91         },
  92         [10] = {
  93                 .start  = EXYNOS4_PA_SYSMMU_FIMC3,
  94                 .end    = EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1,
  95                 .flags  = IORESOURCE_MEM,
  96         },
  97         [11] = {
  98                 .start  = IRQ_SYSMMU_FIMC3_0,
  99                 .end    = IRQ_SYSMMU_FIMC3_0,
 100                 .flags  = IORESOURCE_IRQ,
 101         },
 102         [12] = {
 103                 .start  = EXYNOS4_PA_SYSMMU_JPEG,
 104                 .end    = EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1,
 105                 .flags  = IORESOURCE_MEM,
 106         },
 107         [13] = {
 108                 .start  = IRQ_SYSMMU_JPEG_0,
 109                 .end    = IRQ_SYSMMU_JPEG_0,
 110                 .flags  = IORESOURCE_IRQ,
 111         },
 112         [14] = {
 113                 .start  = EXYNOS4_PA_SYSMMU_FIMD0,
 114                 .end    = EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1,
 115                 .flags  = IORESOURCE_MEM,
 116         },
 117         [15] = {
 118                 .start  = IRQ_SYSMMU_LCD0_M0_0,
 119                 .end    = IRQ_SYSMMU_LCD0_M0_0,
 120                 .flags  = IORESOURCE_IRQ,
 121         },
 122         [16] = {
 123                 .start  = EXYNOS4_PA_SYSMMU_FIMD1,
 124                 .end    = EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1,
 125                 .flags  = IORESOURCE_MEM,
 126         },
 127         [17] = {
 128                 .start  = IRQ_SYSMMU_LCD1_M1_0,
 129                 .end    = IRQ_SYSMMU_LCD1_M1_0,
 130                 .flags  = IORESOURCE_IRQ,
 131         },
 132         [18] = {
 133                 .start  = EXYNOS4_PA_SYSMMU_PCIe,
 134                 .end    = EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1,
 135                 .flags  = IORESOURCE_MEM,
 136         },
 137         [19] = {
 138                 .start  = IRQ_SYSMMU_PCIE_0,
 139                 .end    = IRQ_SYSMMU_PCIE_0,
 140                 .flags  = IORESOURCE_IRQ,
 141         },
 142         [20] = {
 143                 .start  = EXYNOS4_PA_SYSMMU_G2D,
 144                 .end    = EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1,
 145                 .flags  = IORESOURCE_MEM,
 146         },
 147         [21] = {
 148                 .start  = IRQ_SYSMMU_2D_0,
 149                 .end    = IRQ_SYSMMU_2D_0,
 150                 .flags  = IORESOURCE_IRQ,
 151         },
 152         [22] = {
 153                 .start  = EXYNOS4_PA_SYSMMU_ROTATOR,
 154                 .end    = EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1,
 155                 .flags  = IORESOURCE_MEM,
 156         },
 157         [23] = {
 158                 .start  = IRQ_SYSMMU_ROTATOR_0,
 159                 .end    = IRQ_SYSMMU_ROTATOR_0,
 160                 .flags  = IORESOURCE_IRQ,
 161         },
 162         [24] = {
 163                 .start  = EXYNOS4_PA_SYSMMU_MDMA2,
 164                 .end    = EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1,
 165                 .flags  = IORESOURCE_MEM,
 166         },
 167         [25] = {
 168                 .start  = IRQ_SYSMMU_MDMA1_0,
 169                 .end    = IRQ_SYSMMU_MDMA1_0,
 170                 .flags  = IORESOURCE_IRQ,
 171         },
 172         [26] = {
 173                 .start  = EXYNOS4_PA_SYSMMU_TV,
 174                 .end    = EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1,
 175                 .flags  = IORESOURCE_MEM,
 176         },
 177         [27] = {
 178                 .start  = IRQ_SYSMMU_TV_M0_0,
 179                 .end    = IRQ_SYSMMU_TV_M0_0,
 180                 .flags  = IORESOURCE_IRQ,
 181         },
 182         [28] = {
 183                 .start  = EXYNOS4_PA_SYSMMU_MFC_L,
 184                 .end    = EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1,
 185                 .flags  = IORESOURCE_MEM,
 186         },
 187         [29] = {
 188                 .start  = IRQ_SYSMMU_MFC_M0_0,
 189                 .end    = IRQ_SYSMMU_MFC_M0_0,
 190                 .flags  = IORESOURCE_IRQ,
 191         },
 192         [30] = {
 193                 .start  = EXYNOS4_PA_SYSMMU_MFC_R,
 194                 .end    = EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1,
 195                 .flags  = IORESOURCE_MEM,
 196         },
 197         [31] = {
 198                 .start  = IRQ_SYSMMU_MFC_M1_0,
 199                 .end    = IRQ_SYSMMU_MFC_M1_0,
 200                 .flags  = IORESOURCE_IRQ,
 201         },
 202 };
 203
 204 struct platform_device exynos4_device_sysmmu = {
 205         .name           = "s5p-sysmmu",
 206         .id             = 32,
 207         .num_resources  = ARRAY_SIZE(exynos4_sysmmu_resource),
 208         .resource       = exynos4_sysmmu_resource,
 209 };
 210 EXPORT_SYMBOL(exynos4_device_sysmmu);
 211
 212 static struct clk *sysmmu_clk[S5P_SYSMMU_TOTAL_IPNUM];
 213 void sysmmu_clk_init(struct device *dev, sysmmu_ips ips)
 214 {
 215         sysmmu_clk[ips] = clk_get(dev, sysmmu_ips_name[ips]);
 216         if (IS_ERR(sysmmu_clk[ips]))
 217                 sysmmu_clk[ips] = NULL;
 218         else
 219                 clk_put(sysmmu_clk[ips]);
 220 }
 221
 222 void sysmmu_clk_enable(sysmmu_ips ips)
 223 {
 224         if (sysmmu_clk[ips])
 225                 clk_enable(sysmmu_clk[ips]);
 226 }
 227
 228 void sysmmu_clk_disable(sysmmu_ips ips)
 229 {
 230         if (sysmmu_clk[ips])
 231                 clk_disable(sysmmu_clk[ips]);
 232 }