arch/arm/mach-exynos4/cpufreq.c

   1 /* linux/arch/arm/mach-exynos4/cpufreq.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * EXYNOS4 - CPU frequency scaling support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/types.h>
  14 #include <linux/kernel.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <linux/slab.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/cpufreq.h>
  21
  22 #include <mach/map.h>
  23 #include <mach/regs-clock.h>
  24 #include <mach/regs-mem.h>
  25
  26 #include <plat/clock.h>
  27 #include <plat/pm.h>
  28
  29 static struct clk *cpu_clk;
  30 static struct clk *moutcore;
  31 static struct clk *mout_mpll;
  32 static struct clk *mout_apll;
  33
  34 static struct regulator *arm_regulator;
  35 static struct regulator *int_regulator;
  36
  37 static struct cpufreq_freqs freqs;
  38 static unsigned int memtype;
  39
  40 enum exynos4_memory_type {
  41         DDR2 = 4,
  42         LPDDR2,
  43         DDR3,
  44 };
  45
  46 enum cpufreq_level_index {
  47         L0, L1, L2, L3, CPUFREQ_LEVEL_END,
  48 };
  49
  50 static struct cpufreq_frequency_table exynos4_freq_table[] = {
  51         {L0, 1000*1000},
  52         {L1, 800*1000},
  53         {L2, 400*1000},
  54         {L3, 100*1000},
  55         {0, CPUFREQ_TABLE_END},
  56 };
  57
  58 static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
  59         /*
  60          * Clock divider value for following
  61          * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
  62          *              DIVATB, DIVPCLK_DBG, DIVAPLL }
  63          */
  64
  65         /* ARM L0: 1000MHz */
  66         { 0, 3, 7, 3, 3, 0, 1 },
  67
  68         /* ARM L1: 800MHz */
  69         { 0, 3, 7, 3, 3, 0, 1 },
  70
  71         /* ARM L2: 400MHz */
  72         { 0, 1, 3, 1, 3, 0, 1 },
  73
  74         /* ARM L3: 100MHz */
  75         { 0, 0, 1, 0, 3, 1, 1 },
  76 };
  77
  78 static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
  79         /*
  80          * Clock divider value for following
  81          * { DIVCOPY, DIVHPM }
  82          */
  83
  84          /* ARM L0: 1000MHz */
  85         { 3, 0 },
  86
  87         /* ARM L1: 800MHz */
  88         { 3, 0 },
  89
  90         /* ARM L2: 400MHz */
  91         { 3, 0 },
  92
  93         /* ARM L3: 100MHz */
  94         { 3, 0 },
  95 };
  96
  97 static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = {
  98         /*
  99          * Clock divider value for following
 100          * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
 101          *              DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
 102          */
 103
 104         /* DMC L0: 400MHz */
 105         { 3, 1, 1, 1, 1, 1, 3, 1 },
 106
 107         /* DMC L1: 400MHz */
 108         { 3, 1, 1, 1, 1, 1, 3, 1 },
 109
 110         /* DMC L2: 266.7MHz */
 111         { 7, 1, 1, 2, 1, 1, 3, 1 },
 112
 113         /* DMC L3: 200MHz */
 114         { 7, 1, 1, 3, 1, 1, 3, 1 },
 115 };
 116
 117 static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = {
 118         /*
 119          * Clock divider value for following
 120          * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
 121          */
 122
 123         /* ACLK200 L0: 200MHz */
 124         { 3, 7, 4, 5, 1 },
 125
 126         /* ACLK200 L1: 200MHz */
 127         { 3, 7, 4, 5, 1 },
 128
 129         /* ACLK200 L2: 160MHz */
 130         { 4, 7, 5, 7, 1 },
 131
 132         /* ACLK200 L3: 133.3MHz */
 133         { 5, 7, 7, 7, 1 },
 134 };
 135
 136 static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = {
 137         /*
 138          * Clock divider value for following
 139          * { DIVGDL/R, DIVGPL/R }
 140          */
 141
 142         /* ACLK_GDL/R L0: 200MHz */
 143         { 3, 1 },
 144
 145         /* ACLK_GDL/R L1: 200MHz */
 146         { 3, 1 },
 147
 148         /* ACLK_GDL/R L2: 160MHz */
 149         { 4, 1 },
 150
 151         /* ACLK_GDL/R L3: 133.3MHz */
 152         { 5, 1 },
 153 };
 154
 155 struct cpufreq_voltage_table {
 156         unsigned int    index;          /* any */
 157         unsigned int    arm_volt;       /* uV */
 158         unsigned int    int_volt;
 159 };
 160
 161 static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
 162         {
 163                 .index          = L0,
 164                 .arm_volt       = 1200000,
 165                 .int_volt       = 1100000,
 166         }, {
 167                 .index          = L1,
 168                 .arm_volt       = 1100000,
 169                 .int_volt       = 1100000,
 170         }, {
 171                 .index          = L2,
 172                 .arm_volt       = 1000000,
 173                 .int_volt       = 1000000,
 174         }, {
 175                 .index          = L3,
 176                 .arm_volt       = 900000,
 177                 .int_volt       = 1000000,
 178         },
 179 };
 180
 181 static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
 182         /* APLL FOUT L0: 1000MHz */
 183         ((250 << 16) | (6 << 8) | 1),
 184
 185         /* APLL FOUT L1: 800MHz */
 186         ((200 << 16) | (6 << 8) | 1),
 187
 188         /* APLL FOUT L2 : 400MHz */
 189         ((200 << 16) | (6 << 8) | 2),
 190
 191         /* APLL FOUT L3: 100MHz */
 192         ((200 << 16) | (6 << 8) | 4),
 193 };
 194
 195 int exynos4_verify_speed(struct cpufreq_policy *policy)
 196 {
 197         return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
 198 }
 199
 200 unsigned int exynos4_getspeed(unsigned int cpu)
 201 {
 202         return clk_get_rate(cpu_clk) / 1000;
 203 }
 204
 205 void exynos4_set_clkdiv(unsigned int div_index)
 206 {
 207         unsigned int tmp;
 208
 209         /* Change Divider - CPU0 */
 210
 211         tmp = __raw_readl(S5P_CLKDIV_CPU);
 212
 213         tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK |
 214                 S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK |
 215                 S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK |
 216                 S5P_CLKDIV_CPU0_APLL_MASK);
 217
 218         tmp |= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
 219                 (clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
 220                 (clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
 221                 (clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
 222                 (clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
 223                 (clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
 224                 (clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
 225
 226         __raw_writel(tmp, S5P_CLKDIV_CPU);
 227
 228         do {
 229                 tmp = __raw_readl(S5P_CLKDIV_STATCPU);
 230         } while (tmp & 0x1111111);
 231
 232         /* Change Divider - CPU1 */
 233
 234         tmp = __raw_readl(S5P_CLKDIV_CPU1);
 235
 236         tmp &= ~((0x7 << 4) | 0x7);
 237
 238         tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
 239                 (clkdiv_cpu1[div_index][1] << 0));
 240
 241         __raw_writel(tmp, S5P_CLKDIV_CPU1);
 242
 243         do {
 244                 tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
 245         } while (tmp & 0x11);
 246
 247         /* Change Divider - DMC0 */
 248
 249         tmp = __raw_readl(S5P_CLKDIV_DMC0);
 250
 251         tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | S5P_CLKDIV_DMC0_ACPPCLK_MASK |
 252                 S5P_CLKDIV_DMC0_DPHY_MASK | S5P_CLKDIV_DMC0_DMC_MASK |
 253                 S5P_CLKDIV_DMC0_DMCD_MASK | S5P_CLKDIV_DMC0_DMCP_MASK |
 254                 S5P_CLKDIV_DMC0_COPY2_MASK | S5P_CLKDIV_DMC0_CORETI_MASK);
 255
 256         tmp |= ((clkdiv_dmc0[div_index][0] << S5P_CLKDIV_DMC0_ACP_SHIFT) |
 257                 (clkdiv_dmc0[div_index][1] << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
 258                 (clkdiv_dmc0[div_index][2] << S5P_CLKDIV_DMC0_DPHY_SHIFT) |
 259                 (clkdiv_dmc0[div_index][3] << S5P_CLKDIV_DMC0_DMC_SHIFT) |
 260                 (clkdiv_dmc0[div_index][4] << S5P_CLKDIV_DMC0_DMCD_SHIFT) |
 261                 (clkdiv_dmc0[div_index][5] << S5P_CLKDIV_DMC0_DMCP_SHIFT) |
 262                 (clkdiv_dmc0[div_index][6] << S5P_CLKDIV_DMC0_COPY2_SHIFT) |
 263                 (clkdiv_dmc0[div_index][7] << S5P_CLKDIV_DMC0_CORETI_SHIFT));
 264
 265         __raw_writel(tmp, S5P_CLKDIV_DMC0);
 266
 267         do {
 268                 tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
 269         } while (tmp & 0x11111111);
 270
 271         /* Change Divider - TOP */
 272
 273         tmp = __raw_readl(S5P_CLKDIV_TOP);
 274
 275         tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | S5P_CLKDIV_TOP_ACLK100_MASK |
 276                 S5P_CLKDIV_TOP_ACLK160_MASK | S5P_CLKDIV_TOP_ACLK133_MASK |
 277                 S5P_CLKDIV_TOP_ONENAND_MASK);
 278
 279         tmp |= ((clkdiv_top[div_index][0] << S5P_CLKDIV_TOP_ACLK200_SHIFT) |
 280                 (clkdiv_top[div_index][1] << S5P_CLKDIV_TOP_ACLK100_SHIFT) |
 281                 (clkdiv_top[div_index][2] << S5P_CLKDIV_TOP_ACLK160_SHIFT) |
 282                 (clkdiv_top[div_index][3] << S5P_CLKDIV_TOP_ACLK133_SHIFT) |
 283                 (clkdiv_top[div_index][4] << S5P_CLKDIV_TOP_ONENAND_SHIFT));
 284
 285         __raw_writel(tmp, S5P_CLKDIV_TOP);
 286
 287         do {
 288                 tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
 289         } while (tmp & 0x11111);
 290
 291         /* Change Divider - LEFTBUS */
 292
 293         tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
 294
 295         tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
 296
 297         tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
 298                 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
 299
 300         __raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
 301
 302         do {
 303                 tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
 304         } while (tmp & 0x11);
 305
 306         /* Change Divider - RIGHTBUS */
 307
 308         tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
 309
 310         tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
 311
 312         tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
 313                 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
 314
 315         __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
 316
 317         do {
 318                 tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
 319         } while (tmp & 0x11);
 320 }
 321
 322 static void exynos4_set_apll(unsigned int index)
 323 {
 324         unsigned int tmp;
 325
 326         /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
 327         clk_set_parent(moutcore, mout_mpll);
 328
 329         do {
 330                 tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
 331                         >> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
 332                 tmp &= 0x7;
 333         } while (tmp != 0x2);
 334
 335         /* 2. Set APLL Lock time */
 336         __raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);
 337
 338         /* 3. Change PLL PMS values */
 339         tmp = __raw_readl(S5P_APLL_CON0);
 340         tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
 341         tmp |= exynos4_apll_pms_table[index];
 342         __raw_writel(tmp, S5P_APLL_CON0);
 343
 344         /* 4. wait_lock_time */
 345         do {
 346                 tmp = __raw_readl(S5P_APLL_CON0);
 347         } while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));
 348
 349         /* 5. MUX_CORE_SEL = APLL */
 350         clk_set_parent(moutcore, mout_apll);
 351
 352         do {
 353                 tmp = __raw_readl(S5P_CLKMUX_STATCPU);
 354                 tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
 355         } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
 356 }
 357
 358 static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)
 359 {
 360         unsigned int tmp;
 361
 362         if (old_index > new_index) {
 363                 /* The frequency changing to L0 needs to change apll */
 364                 if (freqs.new == exynos4_freq_table[L0].frequency) {
 365                         /* 1. Change the system clock divider values */
 366                         exynos4_set_clkdiv(new_index);
 367
 368                         /* 2. Change the apll m,p,s value */
 369                         exynos4_set_apll(new_index);
 370                 } else {
 371                         /* 1. Change the system clock divider values */
 372                         exynos4_set_clkdiv(new_index);
 373
 374                         /* 2. Change just s value in apll m,p,s value */
 375                         tmp = __raw_readl(S5P_APLL_CON0);
 376                         tmp &= ~(0x7 << 0);
 377                         tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
 378                         __raw_writel(tmp, S5P_APLL_CON0);
 379                 }
 380         }
 381
 382         else if (old_index < new_index) {
 383                 /* The frequency changing from L0 needs to change apll */
 384                 if (freqs.old == exynos4_freq_table[L0].frequency) {
 385                         /* 1. Change the apll m,p,s value */
 386                         exynos4_set_apll(new_index);
 387
 388                         /* 2. Change the system clock divider values */
 389                         exynos4_set_clkdiv(new_index);
 390                 } else {
 391                         /* 1. Change just s value in apll m,p,s value */
 392                         tmp = __raw_readl(S5P_APLL_CON0);
 393                         tmp &= ~(0x7 << 0);
 394                         tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
 395                         __raw_writel(tmp, S5P_APLL_CON0);
 396
 397                         /* 2. Change the system clock divider values */
 398                         exynos4_set_clkdiv(new_index);
 399                 }
 400         }
 401 }
 402
 403 static int exynos4_target(struct cpufreq_policy *policy,
 404                           unsigned int target_freq,
 405                           unsigned int relation)
 406 {
 407         unsigned int index, old_index;
 408         unsigned int arm_volt, int_volt;
 409
 410         freqs.old = exynos4_getspeed(policy->cpu);
 411
 412         if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
 413                                            freqs.old, relation, &old_index))
 414                 return -EINVAL;
 415
 416         if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
 417                                            target_freq, relation, &index))
 418                 return -EINVAL;
 419
 420         freqs.new = exynos4_freq_table[index].frequency;
 421         freqs.cpu = policy->cpu;
 422
 423         if (freqs.new == freqs.old)
 424                 return 0;
 425
 426         /* get the voltage value */
 427         arm_volt = exynos4_volt_table[index].arm_volt;
 428         int_volt = exynos4_volt_table[index].int_volt;
 429
 430         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 431
 432         /* control regulator */
 433         if (freqs.new > freqs.old) {
 434                 /* Voltage up */
 435                 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
 436                 regulator_set_voltage(int_regulator, int_volt, int_volt);
 437         }
 438
 439         /* Clock Configuration Procedure */
 440         exynos4_set_frequency(old_index, index);
 441
 442         /* control regulator */
 443         if (freqs.new < freqs.old) {
 444                 /* Voltage down */
 445                 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
 446                 regulator_set_voltage(int_regulator, int_volt, int_volt);
 447         }
 448
 449         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 450
 451         return 0;
 452 }
 453
 454 #ifdef CONFIG_PM
 455 static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy)
 456 {
 457         return 0;
 458 }
 459
 460 static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
 461 {
 462         return 0;
 463 }
 464 #endif
 465
 466 static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
 467 {
 468         policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);
 469
 470         cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
 471
 472         /* set the transition latency value */
 473         policy->cpuinfo.transition_latency = 100000;
 474
 475         /*
 476          * EXYNOS4 multi-core processors has 2 cores
 477          * that the frequency cannot be set independently.
 478          * Each cpu is bound to the same speed.
 479          * So the affected cpu is all of the cpus.
 480          */
 481         cpumask_setall(policy->cpus);
 482
 483         return cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
 484 }
 485
 486 static struct cpufreq_driver exynos4_driver = {
 487         .flags          = CPUFREQ_STICKY,
 488         .verify         = exynos4_verify_speed,
 489         .target         = exynos4_target,
 490         .get            = exynos4_getspeed,
 491         .init           = exynos4_cpufreq_cpu_init,
 492         .name           = "exynos4_cpufreq",
 493 #ifdef CONFIG_PM
 494         .suspend        = exynos4_cpufreq_suspend,
 495         .resume         = exynos4_cpufreq_resume,
 496 #endif
 497 };
 498
 499 static int __init exynos4_cpufreq_init(void)
 500 {
 501         cpu_clk = clk_get(NULL, "armclk");
 502         if (IS_ERR(cpu_clk))
 503                 return PTR_ERR(cpu_clk);
 504
 505         moutcore = clk_get(NULL, "moutcore");
 506         if (IS_ERR(moutcore))
 507                 goto out;
 508
 509         mout_mpll = clk_get(NULL, "mout_mpll");
 510         if (IS_ERR(mout_mpll))
 511                 goto out;
 512
 513         mout_apll = clk_get(NULL, "mout_apll");
 514         if (IS_ERR(mout_apll))
 515                 goto out;
 516
 517         arm_regulator = regulator_get(NULL, "vdd_arm");
 518         if (IS_ERR(arm_regulator)) {
 519                 printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
 520                 goto out;
 521         }
 522
 523         int_regulator = regulator_get(NULL, "vdd_int");
 524         if (IS_ERR(int_regulator)) {
 525                 printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
 526                 goto out;
 527         }
 528
 529         /*
 530          * Check DRAM type.
 531          * Because DVFS level is different according to DRAM type.
 532          */
 533         memtype = __raw_readl(S5P_VA_DMC0 + S5P_DMC0_MEMCON_OFFSET);
 534         memtype = (memtype >> S5P_DMC0_MEMTYPE_SHIFT);
 535         memtype &= S5P_DMC0_MEMTYPE_MASK;
 536
 537         if ((memtype < DDR2) && (memtype > DDR3)) {
 538                 printk(KERN_ERR "%s: wrong memtype= 0x%x\n", __func__, memtype);
 539                 goto out;
 540         } else {
 541                 printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
 542         }
 543
 544         return cpufreq_register_driver(&exynos4_driver);
 545
 546 out:
 547         if (!IS_ERR(cpu_clk))
 548                 clk_put(cpu_clk);
 549
 550         if (!IS_ERR(moutcore))
 551                 clk_put(moutcore);
 552
 553         if (!IS_ERR(mout_mpll))
 554                 clk_put(mout_mpll);
 555
 556         if (!IS_ERR(mout_apll))
 557                 clk_put(mout_apll);
 558
 559         if (!IS_ERR(arm_regulator))
 560                 regulator_put(arm_regulator);
 561
 562         if (!IS_ERR(int_regulator))
 563                 regulator_put(int_regulator);
 564
 565         printk(KERN_ERR "%s: failed initialization\n", __func__);
 566
 567         return -EINVAL;
 568 }
 569 late_initcall(exynos4_cpufreq_init);