arch/arm/mach-exynos4/cpu.c

   1 /* linux/arch/arm/mach-exynos4/cpu.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/sched.h>
  12 #include <linux/sysdev.h>
  13
  14 #include <asm/mach/map.h>
  15 #include <asm/mach/irq.h>
  16
  17 #include <asm/proc-fns.h>
  18 #include <asm/hardware/cache-l2x0.h>
  19
  20 #include <plat/cpu.h>
  21 #include <plat/clock.h>
  22 #include <plat/exynos4.h>
  23 #include <plat/sdhci.h>
  24 #include <plat/devs.h>
  25 #include <plat/fimc-core.h>
  26 #include <plat/iic-core.h>
  27
  28 #include <mach/regs-irq.h>
  29
  30 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
  31                          unsigned int irq_start);
  32 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
  33
  34 /* Initial IO mappings */
  35 static struct map_desc exynos4_iodesc[] __initdata = {
  36         {
  37                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
  38                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
  39                 .length         = SZ_4K,
  40                 .type           = MT_DEVICE,
  41         }, {
  42                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
  43                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
  44                 .length         = SZ_4K,
  45                 .type           = MT_DEVICE,
  46         }, {
  47                 .virtual        = (unsigned long)S5P_VA_CMU,
  48                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
  49                 .length         = SZ_128K,
  50                 .type           = MT_DEVICE,
  51         }, {
  52                 .virtual        = (unsigned long)S5P_VA_PMU,
  53                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
  54                 .length         = SZ_64K,
  55                 .type           = MT_DEVICE,
  56         }, {
  57                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
  58                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
  59                 .length         = SZ_4K,
  60                 .type           = MT_DEVICE,
  61         }, {
  62                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
  63                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
  64                 .length         = SZ_8K,
  65                 .type           = MT_DEVICE,
  66         }, {
  67                 .virtual        = (unsigned long)S5P_VA_L2CC,
  68                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
  69                 .length         = SZ_4K,
  70                 .type           = MT_DEVICE,
  71         }, {
  72                 .virtual        = (unsigned long)S5P_VA_GPIO1,
  73                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
  74                 .length         = SZ_4K,
  75                 .type           = MT_DEVICE,
  76         }, {
  77                 .virtual        = (unsigned long)S5P_VA_GPIO2,
  78                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
  79                 .length         = SZ_4K,
  80                 .type           = MT_DEVICE,
  81         }, {
  82                 .virtual        = (unsigned long)S5P_VA_GPIO3,
  83                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
  84                 .length         = SZ_256,
  85                 .type           = MT_DEVICE,
  86         }, {
  87                 .virtual        = (unsigned long)S5P_VA_DMC0,
  88                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
  89                 .length         = SZ_4K,
  90                 .type           = MT_DEVICE,
  91         }, {
  92                 .virtual        = (unsigned long)S3C_VA_UART,
  93                 .pfn            = __phys_to_pfn(S3C_PA_UART),
  94                 .length         = SZ_512K,
  95                 .type           = MT_DEVICE,
  96         }, {
  97                 .virtual        = (unsigned long)S5P_VA_SROMC,
  98                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
  99                 .length         = SZ_4K,
 100                 .type           = MT_DEVICE,
 101         }, {
 102                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 103                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 104                 .length         = SZ_4K,
 105                 .type           = MT_DEVICE,
 106         }
 107 };
 108
 109 static void exynos4_idle(void)
 110 {
 111         if (!need_resched())
 112                 cpu_do_idle();
 113
 114         local_irq_enable();
 115 }
 116
 117 /*
 118  * exynos4_map_io
 119  *
 120  * register the standard cpu IO areas
 121  */
 122 void __init exynos4_map_io(void)
 123 {
 124         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 125
 126         /* initialize device information early */
 127         exynos4_default_sdhci0();
 128         exynos4_default_sdhci1();
 129         exynos4_default_sdhci2();
 130         exynos4_default_sdhci3();
 131
 132         s3c_fimc_setname(0, "exynos4-fimc");
 133         s3c_fimc_setname(1, "exynos4-fimc");
 134         s3c_fimc_setname(2, "exynos4-fimc");
 135         s3c_fimc_setname(3, "exynos4-fimc");
 136
 137         /* The I2C bus controllers are directly compatible with s3c2440 */
 138         s3c_i2c0_setname("s3c2440-i2c");
 139         s3c_i2c1_setname("s3c2440-i2c");
 140         s3c_i2c2_setname("s3c2440-i2c");
 141 }
 142
 143 void __init exynos4_init_clocks(int xtal)
 144 {
 145         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 146
 147         s3c24xx_register_baseclocks(xtal);
 148         s5p_register_clocks(xtal);
 149         exynos4_register_clocks();
 150         exynos4_setup_clocks();
 151 }
 152
 153 void __init exynos4_init_irq(void)
 154 {
 155         int irq;
 156
 157         gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
 158
 159         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
 160
 161                 /*
 162                  * From SPI(0) to SPI(39) and SPI(51), SPI(53) are
 163                  * connected to the interrupt combiner. These irqs
 164                  * should be initialized to support cascade interrupt.
 165                  */
 166                 if ((irq >= 40) && !(irq == 51) && !(irq == 53))
 167                         continue;
 168
 169                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
 170                                 COMBINER_IRQ(irq, 0));
 171                 combiner_cascade_irq(irq, IRQ_SPI(irq));
 172         }
 173
 174         /* The parameters of s5p_init_irq() are for VIC init.
 175          * Theses parameters should be NULL and 0 because EXYNOS4
 176          * uses GIC instead of VIC.
 177          */
 178         s5p_init_irq(NULL, 0);
 179 }
 180
 181 struct sysdev_class exynos4_sysclass = {
 182         .name   = "exynos4-core",
 183 };
 184
 185 static struct sys_device exynos4_sysdev = {
 186         .cls    = &exynos4_sysclass,
 187 };
 188
 189 static int __init exynos4_core_init(void)
 190 {
 191         return sysdev_class_register(&exynos4_sysclass);
 192 }
 193
 194 core_initcall(exynos4_core_init);
 195
 196 #ifdef CONFIG_CACHE_L2X0
 197 static int __init exynos4_l2x0_cache_init(void)
 198 {
 199         /* TAG, Data Latency Control: 2cycle */
 200         __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 201         __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 202
 203         /* L2X0 Prefetch Control */
 204         __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 205
 206         /* L2X0 Power Control */
 207         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
 208                      S5P_VA_L2CC + L2X0_POWER_CTRL);
 209
 210         l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
 211
 212         return 0;
 213 }
 214
 215 early_initcall(exynos4_l2x0_cache_init);
 216 #endif
 217
 218 int __init exynos4_init(void)
 219 {
 220         printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
 221
 222         /* set idle function */
 223         pm_idle = exynos4_idle;
 224
 225         return sysdev_register(&exynos4_sysdev);
 226 }