arch/arm/mach-exynos4/cpu.c

   1 /* linux/arch/arm/mach-exynos4/cpu.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/sched.h>
  12 #include <linux/sysdev.h>
  13
  14 #include <asm/mach/map.h>
  15 #include <asm/mach/irq.h>
  16
  17 #include <asm/proc-fns.h>
  18 #include <asm/hardware/cache-l2x0.h>
  19 #include <asm/hardware/gic.h>
  20
  21 #include <plat/cpu.h>
  22 #include <plat/clock.h>
  23 #include <plat/devs.h>
  24 #include <plat/exynos4.h>
  25 #include <plat/adc-core.h>
  26 #include <plat/sdhci.h>
  27 #include <plat/fb-core.h>
  28 #include <plat/fimc-core.h>
  29 #include <plat/iic-core.h>
  30 #include <plat/reset.h>
  31
  32 #include <mach/regs-irq.h>
  33 #include <mach/regs-pmu.h>
  34
  35 unsigned int gic_bank_offset __read_mostly;
  36
  37 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
  38                          unsigned int irq_start);
  39 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
  40
  41 /* Initial IO mappings */
  42 static struct map_desc exynos4_iodesc[] __initdata = {
  43         {
  44                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
  45                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
  46                 .length         = SZ_4K,
  47                 .type           = MT_DEVICE,
  48         }, {
  49                 .virtual        = (unsigned long)S5P_VA_CMU,
  50                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
  51                 .length         = SZ_128K,
  52                 .type           = MT_DEVICE,
  53         }, {
  54                 .virtual        = (unsigned long)S5P_VA_PMU,
  55                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
  56                 .length         = SZ_64K,
  57                 .type           = MT_DEVICE,
  58         }, {
  59                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
  60                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
  61                 .length         = SZ_4K,
  62                 .type           = MT_DEVICE,
  63         }, {
  64                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
  65                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
  66                 .length         = SZ_8K,
  67                 .type           = MT_DEVICE,
  68         }, {
  69                 .virtual        = (unsigned long)S5P_VA_L2CC,
  70                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
  71                 .length         = SZ_4K,
  72                 .type           = MT_DEVICE,
  73         }, {
  74                 .virtual        = (unsigned long)S5P_VA_GPIO1,
  75                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
  76                 .length         = SZ_4K,
  77                 .type           = MT_DEVICE,
  78         }, {
  79                 .virtual        = (unsigned long)S5P_VA_GPIO2,
  80                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
  81                 .length         = SZ_4K,
  82                 .type           = MT_DEVICE,
  83         }, {
  84                 .virtual        = (unsigned long)S5P_VA_GPIO3,
  85                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
  86                 .length         = SZ_256,
  87                 .type           = MT_DEVICE,
  88         }, {
  89                 .virtual        = (unsigned long)S5P_VA_DMC0,
  90                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
  91                 .length         = SZ_4K,
  92                 .type           = MT_DEVICE,
  93         }, {
  94                 .virtual        = (unsigned long)S3C_VA_UART,
  95                 .pfn            = __phys_to_pfn(S3C_PA_UART),
  96                 .length         = SZ_512K,
  97                 .type           = MT_DEVICE,
  98         }, {
  99                 .virtual        = (unsigned long)S5P_VA_SROMC,
 100                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 101                 .length         = SZ_4K,
 102                 .type           = MT_DEVICE,
 103         }, {
 104                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 105                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 106                 .length         = SZ_4K,
 107                 .type           = MT_DEVICE,
 108         }, {
 109                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 110                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 111                 .length         = SZ_64K,
 112                 .type           = MT_DEVICE,
 113         }, {
 114                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 115                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 116                 .length         = SZ_64K,
 117                 .type           = MT_DEVICE,
 118         },
 119 };
 120
 121 static struct map_desc exynos4_iodesc0[] __initdata = {
 122         {
 123                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 124                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 125                 .length         = SZ_4K,
 126                 .type           = MT_DEVICE,
 127         },
 128 };
 129
 130 static struct map_desc exynos4_iodesc1[] __initdata = {
 131         {
 132                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 133                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 134                 .length         = SZ_4K,
 135                 .type           = MT_DEVICE,
 136         },
 137 };
 138
 139 static void exynos4_idle(void)
 140 {
 141         if (!need_resched())
 142                 cpu_do_idle();
 143
 144         local_irq_enable();
 145 }
 146
 147 static void exynos4_sw_reset(void)
 148 {
 149         __raw_writel(0x1, S5P_SWRESET);
 150 }
 151
 152 /*
 153  * exynos4_map_io
 154  *
 155  * register the standard cpu IO areas
 156  */
 157 void __init exynos4_map_io(void)
 158 {
 159         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 160
 161         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 162                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 163         else
 164                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 165
 166         /* initialize device information early */
 167         exynos4_default_sdhci0();
 168         exynos4_default_sdhci1();
 169         exynos4_default_sdhci2();
 170         exynos4_default_sdhci3();
 171
 172         s3c_adc_setname("samsung-adc-v3");
 173
 174         s3c_fimc_setname(0, "exynos4-fimc");
 175         s3c_fimc_setname(1, "exynos4-fimc");
 176         s3c_fimc_setname(2, "exynos4-fimc");
 177         s3c_fimc_setname(3, "exynos4-fimc");
 178
 179         /* The I2C bus controllers are directly compatible with s3c2440 */
 180         s3c_i2c0_setname("s3c2440-i2c");
 181         s3c_i2c1_setname("s3c2440-i2c");
 182         s3c_i2c2_setname("s3c2440-i2c");
 183
 184         s5p_fb_setname(0, "exynos4-fb");
 185 }
 186
 187 void __init exynos4_init_clocks(int xtal)
 188 {
 189         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 190
 191         s3c24xx_register_baseclocks(xtal);
 192         s5p_register_clocks(xtal);
 193
 194         if (soc_is_exynos4210())
 195                 exynos4210_register_clocks();
 196         else if (soc_is_exynos4212() || soc_is_exynos4412())
 197                 exynos4212_register_clocks();
 198
 199         exynos4_register_clocks();
 200         exynos4_setup_clocks();
 201 }
 202
 203 static void exynos4_gic_irq_fix_base(struct irq_data *d)
 204 {
 205         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 206
 207         gic_data->cpu_base = S5P_VA_GIC_CPU +
 208                             (gic_bank_offset * smp_processor_id());
 209
 210         gic_data->dist_base = S5P_VA_GIC_DIST +
 211                             (gic_bank_offset * smp_processor_id());
 212 }
 213
 214 void __init exynos4_init_irq(void)
 215 {
 216         int irq;
 217
 218         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 219
 220         gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
 221         gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
 222         gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
 223         gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
 224
 225         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
 226
 227                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
 228                                 COMBINER_IRQ(irq, 0));
 229                 combiner_cascade_irq(irq, IRQ_SPI(irq));
 230         }
 231
 232         /* The parameters of s5p_init_irq() are for VIC init.
 233          * Theses parameters should be NULL and 0 because EXYNOS4
 234          * uses GIC instead of VIC.
 235          */
 236         s5p_init_irq(NULL, 0);
 237 }
 238
 239 struct sysdev_class exynos4_sysclass = {
 240         .name   = "exynos4-core",
 241 };
 242
 243 static struct sys_device exynos4_sysdev = {
 244         .cls    = &exynos4_sysclass,
 245 };
 246
 247 static int __init exynos4_core_init(void)
 248 {
 249         return sysdev_class_register(&exynos4_sysclass);
 250 }
 251
 252 core_initcall(exynos4_core_init);
 253
 254 #ifdef CONFIG_CACHE_L2X0
 255 static int __init exynos4_l2x0_cache_init(void)
 256 {
 257         /* TAG, Data Latency Control: 2cycle */
 258         __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 259
 260         if (soc_is_exynos4210())
 261                 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 262         else if (soc_is_exynos4212() || soc_is_exynos4412())
 263                 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 264
 265         /* L2X0 Prefetch Control */
 266         __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 267
 268         /* L2X0 Power Control */
 269         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
 270                      S5P_VA_L2CC + L2X0_POWER_CTRL);
 271
 272         l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
 273
 274         return 0;
 275 }
 276
 277 early_initcall(exynos4_l2x0_cache_init);
 278 #endif
 279
 280 int __init exynos4_init(void)
 281 {
 282         printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
 283
 284         /* set idle function */
 285         pm_idle = exynos4_idle;
 286
 287         /* set sw_reset function */
 288         s5p_reset_hook = exynos4_sw_reset;
 289
 290         return sysdev_register(&exynos4_sysdev);
 291 }