arch/arm/mach-exynos4/cpu.c

   1 /* linux/arch/arm/mach-exynos4/cpu.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/sched.h>
  12 #include <linux/sysdev.h>
  13
  14 #include <asm/mach/map.h>
  15 #include <asm/mach/irq.h>
  16
  17 #include <asm/proc-fns.h>
  18 #include <asm/hardware/cache-l2x0.h>
  19 #include <asm/hardware/gic.h>
  20
  21 #include <plat/cpu.h>
  22 #include <plat/clock.h>
  23 #include <plat/devs.h>
  24 #include <plat/exynos4.h>
  25 #include <plat/adc-core.h>
  26 #include <plat/sdhci.h>
  27 #include <plat/devs.h>
  28 #include <plat/fb-core.h>
  29 #include <plat/fimc-core.h>
  30 #include <plat/iic-core.h>
  31
  32 #include <mach/regs-irq.h>
  33
  34 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
  35                          unsigned int irq_start);
  36 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
  37
  38 /* Initial IO mappings */
  39 static struct map_desc exynos4_iodesc[] __initdata = {
  40         {
  41                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
  42                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
  43                 .length         = SZ_4K,
  44                 .type           = MT_DEVICE,
  45         }, {
  46                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
  47                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
  48                 .length         = SZ_4K,
  49                 .type           = MT_DEVICE,
  50         }, {
  51                 .virtual        = (unsigned long)S5P_VA_CMU,
  52                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
  53                 .length         = SZ_128K,
  54                 .type           = MT_DEVICE,
  55         }, {
  56                 .virtual        = (unsigned long)S5P_VA_PMU,
  57                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
  58                 .length         = SZ_64K,
  59                 .type           = MT_DEVICE,
  60         }, {
  61                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
  62                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
  63                 .length         = SZ_4K,
  64                 .type           = MT_DEVICE,
  65         }, {
  66                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
  67                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
  68                 .length         = SZ_8K,
  69                 .type           = MT_DEVICE,
  70         }, {
  71                 .virtual        = (unsigned long)S5P_VA_L2CC,
  72                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
  73                 .length         = SZ_4K,
  74                 .type           = MT_DEVICE,
  75         }, {
  76                 .virtual        = (unsigned long)S5P_VA_GPIO1,
  77                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
  78                 .length         = SZ_4K,
  79                 .type           = MT_DEVICE,
  80         }, {
  81                 .virtual        = (unsigned long)S5P_VA_GPIO2,
  82                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
  83                 .length         = SZ_4K,
  84                 .type           = MT_DEVICE,
  85         }, {
  86                 .virtual        = (unsigned long)S5P_VA_GPIO3,
  87                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
  88                 .length         = SZ_256,
  89                 .type           = MT_DEVICE,
  90         }, {
  91                 .virtual        = (unsigned long)S5P_VA_DMC0,
  92                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
  93                 .length         = SZ_4K,
  94                 .type           = MT_DEVICE,
  95         }, {
  96                 .virtual        = (unsigned long)S3C_VA_UART,
  97                 .pfn            = __phys_to_pfn(S3C_PA_UART),
  98                 .length         = SZ_512K,
  99                 .type           = MT_DEVICE,
 100         }, {
 101                 .virtual        = (unsigned long)S5P_VA_SROMC,
 102                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 103                 .length         = SZ_4K,
 104                 .type           = MT_DEVICE,
 105         }, {
 106                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 107                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 108                 .length         = SZ_4K,
 109                 .type           = MT_DEVICE,
 110         }, {
 111                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 112                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 113                 .length         = SZ_64K,
 114                 .type           = MT_DEVICE,
 115         }, {
 116                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 117                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 118                 .length         = SZ_64K,
 119                 .type           = MT_DEVICE,
 120         },
 121 };
 122
 123 static void exynos4_idle(void)
 124 {
 125         if (!need_resched())
 126                 cpu_do_idle();
 127
 128         local_irq_enable();
 129 }
 130
 131 /*
 132  * exynos4_map_io
 133  *
 134  * register the standard cpu IO areas
 135  */
 136 void __init exynos4_map_io(void)
 137 {
 138         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 139
 140         /* initialize device information early */
 141         exynos4_default_sdhci0();
 142         exynos4_default_sdhci1();
 143         exynos4_default_sdhci2();
 144         exynos4_default_sdhci3();
 145
 146         s3c_adc_setname("samsung-adc-v3");
 147
 148         s3c_fimc_setname(0, "exynos4-fimc");
 149         s3c_fimc_setname(1, "exynos4-fimc");
 150         s3c_fimc_setname(2, "exynos4-fimc");
 151         s3c_fimc_setname(3, "exynos4-fimc");
 152
 153         /* The I2C bus controllers are directly compatible with s3c2440 */
 154         s3c_i2c0_setname("s3c2440-i2c");
 155         s3c_i2c1_setname("s3c2440-i2c");
 156         s3c_i2c2_setname("s3c2440-i2c");
 157
 158         s5p_fb_setname(0, "exynos4-fb");
 159 }
 160
 161 void __init exynos4_init_clocks(int xtal)
 162 {
 163         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 164
 165         s3c24xx_register_baseclocks(xtal);
 166         s5p_register_clocks(xtal);
 167         exynos4_register_clocks();
 168         exynos4_setup_clocks();
 169 }
 170
 171 static void exynos4_gic_irq_eoi(struct irq_data *d)
 172 {
 173         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 174
 175         gic_data->cpu_base = S5P_VA_GIC_CPU +
 176                             (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
 177 }
 178
 179 void __init exynos4_init_irq(void)
 180 {
 181         int irq;
 182
 183         gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
 184         gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
 185
 186         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
 187
 188                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
 189                                 COMBINER_IRQ(irq, 0));
 190                 combiner_cascade_irq(irq, IRQ_SPI(irq));
 191         }
 192
 193         /* The parameters of s5p_init_irq() are for VIC init.
 194          * Theses parameters should be NULL and 0 because EXYNOS4
 195          * uses GIC instead of VIC.
 196          */
 197         s5p_init_irq(NULL, 0);
 198 }
 199
 200 struct sysdev_class exynos4_sysclass = {
 201         .name   = "exynos4-core",
 202 };
 203
 204 static struct sys_device exynos4_sysdev = {
 205         .cls    = &exynos4_sysclass,
 206 };
 207
 208 static int __init exynos4_core_init(void)
 209 {
 210         return sysdev_class_register(&exynos4_sysclass);
 211 }
 212
 213 core_initcall(exynos4_core_init);
 214
 215 #ifdef CONFIG_CACHE_L2X0
 216 static int __init exynos4_l2x0_cache_init(void)
 217 {
 218         /* TAG, Data Latency Control: 2cycle */
 219         __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 220         __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 221
 222         /* L2X0 Prefetch Control */
 223         __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 224
 225         /* L2X0 Power Control */
 226         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
 227                      S5P_VA_L2CC + L2X0_POWER_CTRL);
 228
 229         l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
 230
 231         return 0;
 232 }
 233
 234 early_initcall(exynos4_l2x0_cache_init);
 235 #endif
 236
 237 int __init exynos4_init(void)
 238 {
 239         printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
 240
 241         /* set idle function */
 242         pm_idle = exynos4_idle;
 243
 244         return sysdev_register(&exynos4_sysdev);
 245 }