Merge branch 'next' of git://git.infradead.org/users/vkoul/slave-dma
[pandora-kernel.git] / arch / arm / mach-exynos4 / clock.c
1 /* linux/arch/arm/mach-exynos4/clock.c
2  *
3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4  *              http://www.samsung.com
5  *
6  * EXYNOS4 - Clock support
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/err.h>
15 #include <linux/io.h>
16 #include <linux/syscore_ops.h>
17
18 #include <plat/cpu-freq.h>
19 #include <plat/clock.h>
20 #include <plat/cpu.h>
21 #include <plat/pll.h>
22 #include <plat/s5p-clock.h>
23 #include <plat/clock-clksrc.h>
24 #include <plat/exynos4.h>
25 #include <plat/pm.h>
26
27 #include <mach/map.h>
28 #include <mach/regs-clock.h>
29 #include <mach/sysmmu.h>
30 #include <mach/exynos4-clock.h>
31
32 static struct sleep_save exynos4_clock_save[] = {
33         SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
34         SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
35         SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
36         SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
37         SAVE_ITEM(S5P_CLKSRC_TOP0),
38         SAVE_ITEM(S5P_CLKSRC_TOP1),
39         SAVE_ITEM(S5P_CLKSRC_CAM),
40         SAVE_ITEM(S5P_CLKSRC_TV),
41         SAVE_ITEM(S5P_CLKSRC_MFC),
42         SAVE_ITEM(S5P_CLKSRC_G3D),
43         SAVE_ITEM(S5P_CLKSRC_LCD0),
44         SAVE_ITEM(S5P_CLKSRC_MAUDIO),
45         SAVE_ITEM(S5P_CLKSRC_FSYS),
46         SAVE_ITEM(S5P_CLKSRC_PERIL0),
47         SAVE_ITEM(S5P_CLKSRC_PERIL1),
48         SAVE_ITEM(S5P_CLKDIV_CAM),
49         SAVE_ITEM(S5P_CLKDIV_TV),
50         SAVE_ITEM(S5P_CLKDIV_MFC),
51         SAVE_ITEM(S5P_CLKDIV_G3D),
52         SAVE_ITEM(S5P_CLKDIV_LCD0),
53         SAVE_ITEM(S5P_CLKDIV_MAUDIO),
54         SAVE_ITEM(S5P_CLKDIV_FSYS0),
55         SAVE_ITEM(S5P_CLKDIV_FSYS1),
56         SAVE_ITEM(S5P_CLKDIV_FSYS2),
57         SAVE_ITEM(S5P_CLKDIV_FSYS3),
58         SAVE_ITEM(S5P_CLKDIV_PERIL0),
59         SAVE_ITEM(S5P_CLKDIV_PERIL1),
60         SAVE_ITEM(S5P_CLKDIV_PERIL2),
61         SAVE_ITEM(S5P_CLKDIV_PERIL3),
62         SAVE_ITEM(S5P_CLKDIV_PERIL4),
63         SAVE_ITEM(S5P_CLKDIV_PERIL5),
64         SAVE_ITEM(S5P_CLKDIV_TOP),
65         SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
66         SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
67         SAVE_ITEM(S5P_CLKSRC_MASK_TV),
68         SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
69         SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
70         SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
71         SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
72         SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
73         SAVE_ITEM(S5P_CLKDIV2_RATIO),
74         SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
75         SAVE_ITEM(S5P_CLKGATE_IP_CAM),
76         SAVE_ITEM(S5P_CLKGATE_IP_TV),
77         SAVE_ITEM(S5P_CLKGATE_IP_MFC),
78         SAVE_ITEM(S5P_CLKGATE_IP_G3D),
79         SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
80         SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
81         SAVE_ITEM(S5P_CLKGATE_IP_GPS),
82         SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
83         SAVE_ITEM(S5P_CLKGATE_BLOCK),
84         SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
85         SAVE_ITEM(S5P_CLKSRC_DMC),
86         SAVE_ITEM(S5P_CLKDIV_DMC0),
87         SAVE_ITEM(S5P_CLKDIV_DMC1),
88         SAVE_ITEM(S5P_CLKGATE_IP_DMC),
89         SAVE_ITEM(S5P_CLKSRC_CPU),
90         SAVE_ITEM(S5P_CLKDIV_CPU),
91         SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
92         SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
93         SAVE_ITEM(S5P_CLKGATE_IP_CPU),
94 };
95
96 struct clk clk_sclk_hdmi27m = {
97         .name           = "sclk_hdmi27m",
98         .rate           = 27000000,
99 };
100
101 struct clk clk_sclk_hdmiphy = {
102         .name           = "sclk_hdmiphy",
103 };
104
105 struct clk clk_sclk_usbphy0 = {
106         .name           = "sclk_usbphy0",
107         .rate           = 27000000,
108 };
109
110 struct clk clk_sclk_usbphy1 = {
111         .name           = "sclk_usbphy1",
112 };
113
114 static struct clk dummy_apb_pclk = {
115         .name           = "apb_pclk",
116         .id             = -1,
117 };
118
119 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
120 {
121         return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
122 }
123
124 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
125 {
126         return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
127 }
128
129 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
130 {
131         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
132 }
133
134 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
135 {
136         return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
137 }
138
139 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
140 {
141         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
142 }
143
144 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
145 {
146         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
147 }
148
149 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
150 {
151         return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
152 }
153
154 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
155 {
156         return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
157 }
158
159 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
160 {
161         return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
162 }
163
164 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
165 {
166         return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
167 }
168
169 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
170 {
171         return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
172 }
173
174 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
175 {
176         return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
177 }
178
179 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
180 {
181         return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
182 }
183
184 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
185 {
186         return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
187 }
188
189 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
190 {
191         return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
192 }
193
194 /* Core list of CMU_CPU side */
195
196 static struct clksrc_clk clk_mout_apll = {
197         .clk    = {
198                 .name           = "mout_apll",
199         },
200         .sources        = &clk_src_apll,
201         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
202 };
203
204 struct clksrc_clk clk_sclk_apll = {
205         .clk    = {
206                 .name           = "sclk_apll",
207                 .parent         = &clk_mout_apll.clk,
208         },
209         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
210 };
211
212 struct clksrc_clk clk_mout_epll = {
213         .clk    = {
214                 .name           = "mout_epll",
215         },
216         .sources        = &clk_src_epll,
217         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
218 };
219
220 struct clksrc_clk clk_mout_mpll = {
221         .clk = {
222                 .name           = "mout_mpll",
223         },
224         .sources        = &clk_src_mpll,
225
226         /* reg_src will be added in each SoCs' clock */
227 };
228
229 static struct clk *clkset_moutcore_list[] = {
230         [0] = &clk_mout_apll.clk,
231         [1] = &clk_mout_mpll.clk,
232 };
233
234 static struct clksrc_sources clkset_moutcore = {
235         .sources        = clkset_moutcore_list,
236         .nr_sources     = ARRAY_SIZE(clkset_moutcore_list),
237 };
238
239 static struct clksrc_clk clk_moutcore = {
240         .clk    = {
241                 .name           = "moutcore",
242         },
243         .sources        = &clkset_moutcore,
244         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
245 };
246
247 static struct clksrc_clk clk_coreclk = {
248         .clk    = {
249                 .name           = "core_clk",
250                 .parent         = &clk_moutcore.clk,
251         },
252         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
253 };
254
255 static struct clksrc_clk clk_armclk = {
256         .clk    = {
257                 .name           = "armclk",
258                 .parent         = &clk_coreclk.clk,
259         },
260 };
261
262 static struct clksrc_clk clk_aclk_corem0 = {
263         .clk    = {
264                 .name           = "aclk_corem0",
265                 .parent         = &clk_coreclk.clk,
266         },
267         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
268 };
269
270 static struct clksrc_clk clk_aclk_cores = {
271         .clk    = {
272                 .name           = "aclk_cores",
273                 .parent         = &clk_coreclk.clk,
274         },
275         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
276 };
277
278 static struct clksrc_clk clk_aclk_corem1 = {
279         .clk    = {
280                 .name           = "aclk_corem1",
281                 .parent         = &clk_coreclk.clk,
282         },
283         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
284 };
285
286 static struct clksrc_clk clk_periphclk = {
287         .clk    = {
288                 .name           = "periphclk",
289                 .parent         = &clk_coreclk.clk,
290         },
291         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
292 };
293
294 /* Core list of CMU_CORE side */
295
296 struct clk *clkset_corebus_list[] = {
297         [0] = &clk_mout_mpll.clk,
298         [1] = &clk_sclk_apll.clk,
299 };
300
301 struct clksrc_sources clkset_mout_corebus = {
302         .sources        = clkset_corebus_list,
303         .nr_sources     = ARRAY_SIZE(clkset_corebus_list),
304 };
305
306 static struct clksrc_clk clk_mout_corebus = {
307         .clk    = {
308                 .name           = "mout_corebus",
309         },
310         .sources        = &clkset_mout_corebus,
311         .reg_src        = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
312 };
313
314 static struct clksrc_clk clk_sclk_dmc = {
315         .clk    = {
316                 .name           = "sclk_dmc",
317                 .parent         = &clk_mout_corebus.clk,
318         },
319         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
320 };
321
322 static struct clksrc_clk clk_aclk_cored = {
323         .clk    = {
324                 .name           = "aclk_cored",
325                 .parent         = &clk_sclk_dmc.clk,
326         },
327         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
328 };
329
330 static struct clksrc_clk clk_aclk_corep = {
331         .clk    = {
332                 .name           = "aclk_corep",
333                 .parent         = &clk_aclk_cored.clk,
334         },
335         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
336 };
337
338 static struct clksrc_clk clk_aclk_acp = {
339         .clk    = {
340                 .name           = "aclk_acp",
341                 .parent         = &clk_mout_corebus.clk,
342         },
343         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
344 };
345
346 static struct clksrc_clk clk_pclk_acp = {
347         .clk    = {
348                 .name           = "pclk_acp",
349                 .parent         = &clk_aclk_acp.clk,
350         },
351         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
352 };
353
354 /* Core list of CMU_TOP side */
355
356 struct clk *clkset_aclk_top_list[] = {
357         [0] = &clk_mout_mpll.clk,
358         [1] = &clk_sclk_apll.clk,
359 };
360
361 struct clksrc_sources clkset_aclk = {
362         .sources        = clkset_aclk_top_list,
363         .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
364 };
365
366 static struct clksrc_clk clk_aclk_200 = {
367         .clk    = {
368                 .name           = "aclk_200",
369         },
370         .sources        = &clkset_aclk,
371         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
372         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
373 };
374
375 static struct clksrc_clk clk_aclk_100 = {
376         .clk    = {
377                 .name           = "aclk_100",
378         },
379         .sources        = &clkset_aclk,
380         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
381         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
382 };
383
384 static struct clksrc_clk clk_aclk_160 = {
385         .clk    = {
386                 .name           = "aclk_160",
387         },
388         .sources        = &clkset_aclk,
389         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
390         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
391 };
392
393 struct clksrc_clk clk_aclk_133 = {
394         .clk    = {
395                 .name           = "aclk_133",
396         },
397         .sources        = &clkset_aclk,
398         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
399         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
400 };
401
402 static struct clk *clkset_vpllsrc_list[] = {
403         [0] = &clk_fin_vpll,
404         [1] = &clk_sclk_hdmi27m,
405 };
406
407 static struct clksrc_sources clkset_vpllsrc = {
408         .sources        = clkset_vpllsrc_list,
409         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
410 };
411
412 static struct clksrc_clk clk_vpllsrc = {
413         .clk    = {
414                 .name           = "vpll_src",
415                 .enable         = exynos4_clksrc_mask_top_ctrl,
416                 .ctrlbit        = (1 << 0),
417         },
418         .sources        = &clkset_vpllsrc,
419         .reg_src        = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
420 };
421
422 static struct clk *clkset_sclk_vpll_list[] = {
423         [0] = &clk_vpllsrc.clk,
424         [1] = &clk_fout_vpll,
425 };
426
427 static struct clksrc_sources clkset_sclk_vpll = {
428         .sources        = clkset_sclk_vpll_list,
429         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
430 };
431
432 struct clksrc_clk clk_sclk_vpll = {
433         .clk    = {
434                 .name           = "sclk_vpll",
435         },
436         .sources        = &clkset_sclk_vpll,
437         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
438 };
439
440 static struct clk init_clocks_off[] = {
441         {
442                 .name           = "timers",
443                 .parent         = &clk_aclk_100.clk,
444                 .enable         = exynos4_clk_ip_peril_ctrl,
445                 .ctrlbit        = (1<<24),
446         }, {
447                 .name           = "csis",
448                 .devname        = "s5p-mipi-csis.0",
449                 .enable         = exynos4_clk_ip_cam_ctrl,
450                 .ctrlbit        = (1 << 4),
451         }, {
452                 .name           = "csis",
453                 .devname        = "s5p-mipi-csis.1",
454                 .enable         = exynos4_clk_ip_cam_ctrl,
455                 .ctrlbit        = (1 << 5),
456         }, {
457                 .name           = "fimc",
458                 .devname        = "exynos4-fimc.0",
459                 .enable         = exynos4_clk_ip_cam_ctrl,
460                 .ctrlbit        = (1 << 0),
461         }, {
462                 .name           = "fimc",
463                 .devname        = "exynos4-fimc.1",
464                 .enable         = exynos4_clk_ip_cam_ctrl,
465                 .ctrlbit        = (1 << 1),
466         }, {
467                 .name           = "fimc",
468                 .devname        = "exynos4-fimc.2",
469                 .enable         = exynos4_clk_ip_cam_ctrl,
470                 .ctrlbit        = (1 << 2),
471         }, {
472                 .name           = "fimc",
473                 .devname        = "exynos4-fimc.3",
474                 .enable         = exynos4_clk_ip_cam_ctrl,
475                 .ctrlbit        = (1 << 3),
476         }, {
477                 .name           = "fimd",
478                 .devname        = "exynos4-fb.0",
479                 .enable         = exynos4_clk_ip_lcd0_ctrl,
480                 .ctrlbit        = (1 << 0),
481         }, {
482                 .name           = "hsmmc",
483                 .devname        = "s3c-sdhci.0",
484                 .parent         = &clk_aclk_133.clk,
485                 .enable         = exynos4_clk_ip_fsys_ctrl,
486                 .ctrlbit        = (1 << 5),
487         }, {
488                 .name           = "hsmmc",
489                 .devname        = "s3c-sdhci.1",
490                 .parent         = &clk_aclk_133.clk,
491                 .enable         = exynos4_clk_ip_fsys_ctrl,
492                 .ctrlbit        = (1 << 6),
493         }, {
494                 .name           = "hsmmc",
495                 .devname        = "s3c-sdhci.2",
496                 .parent         = &clk_aclk_133.clk,
497                 .enable         = exynos4_clk_ip_fsys_ctrl,
498                 .ctrlbit        = (1 << 7),
499         }, {
500                 .name           = "hsmmc",
501                 .devname        = "s3c-sdhci.3",
502                 .parent         = &clk_aclk_133.clk,
503                 .enable         = exynos4_clk_ip_fsys_ctrl,
504                 .ctrlbit        = (1 << 8),
505         }, {
506                 .name           = "dwmmc",
507                 .parent         = &clk_aclk_133.clk,
508                 .enable         = exynos4_clk_ip_fsys_ctrl,
509                 .ctrlbit        = (1 << 9),
510         }, {
511                 .name           = "dma",
512                 .devname        = "s3c-pl330.0",
513                 .enable         = exynos4_clk_ip_fsys_ctrl,
514                 .ctrlbit        = (1 << 0),
515         }, {
516                 .name           = "dma",
517                 .devname        = "s3c-pl330.1",
518                 .enable         = exynos4_clk_ip_fsys_ctrl,
519                 .ctrlbit        = (1 << 1),
520         }, {
521                 .name           = "adc",
522                 .enable         = exynos4_clk_ip_peril_ctrl,
523                 .ctrlbit        = (1 << 15),
524         }, {
525                 .name           = "keypad",
526                 .enable         = exynos4_clk_ip_perir_ctrl,
527                 .ctrlbit        = (1 << 16),
528         }, {
529                 .name           = "rtc",
530                 .enable         = exynos4_clk_ip_perir_ctrl,
531                 .ctrlbit        = (1 << 15),
532         }, {
533                 .name           = "watchdog",
534                 .parent         = &clk_aclk_100.clk,
535                 .enable         = exynos4_clk_ip_perir_ctrl,
536                 .ctrlbit        = (1 << 14),
537         }, {
538                 .name           = "usbhost",
539                 .enable         = exynos4_clk_ip_fsys_ctrl ,
540                 .ctrlbit        = (1 << 12),
541         }, {
542                 .name           = "otg",
543                 .enable         = exynos4_clk_ip_fsys_ctrl,
544                 .ctrlbit        = (1 << 13),
545         }, {
546                 .name           = "spi",
547                 .devname        = "s3c64xx-spi.0",
548                 .enable         = exynos4_clk_ip_peril_ctrl,
549                 .ctrlbit        = (1 << 16),
550         }, {
551                 .name           = "spi",
552                 .devname        = "s3c64xx-spi.1",
553                 .enable         = exynos4_clk_ip_peril_ctrl,
554                 .ctrlbit        = (1 << 17),
555         }, {
556                 .name           = "spi",
557                 .devname        = "s3c64xx-spi.2",
558                 .enable         = exynos4_clk_ip_peril_ctrl,
559                 .ctrlbit        = (1 << 18),
560         }, {
561                 .name           = "iis",
562                 .devname        = "samsung-i2s.0",
563                 .enable         = exynos4_clk_ip_peril_ctrl,
564                 .ctrlbit        = (1 << 19),
565         }, {
566                 .name           = "iis",
567                 .devname        = "samsung-i2s.1",
568                 .enable         = exynos4_clk_ip_peril_ctrl,
569                 .ctrlbit        = (1 << 20),
570         }, {
571                 .name           = "iis",
572                 .devname        = "samsung-i2s.2",
573                 .enable         = exynos4_clk_ip_peril_ctrl,
574                 .ctrlbit        = (1 << 21),
575         }, {
576                 .name           = "ac97",
577                 .devname        = "samsung-ac97",
578                 .enable         = exynos4_clk_ip_peril_ctrl,
579                 .ctrlbit        = (1 << 27),
580         }, {
581                 .name           = "fimg2d",
582                 .enable         = exynos4_clk_ip_image_ctrl,
583                 .ctrlbit        = (1 << 0),
584         }, {
585                 .name           = "mfc",
586                 .devname        = "s5p-mfc",
587                 .enable         = exynos4_clk_ip_mfc_ctrl,
588                 .ctrlbit        = (1 << 0),
589         }, {
590                 .name           = "i2c",
591                 .devname        = "s3c2440-i2c.0",
592                 .parent         = &clk_aclk_100.clk,
593                 .enable         = exynos4_clk_ip_peril_ctrl,
594                 .ctrlbit        = (1 << 6),
595         }, {
596                 .name           = "i2c",
597                 .devname        = "s3c2440-i2c.1",
598                 .parent         = &clk_aclk_100.clk,
599                 .enable         = exynos4_clk_ip_peril_ctrl,
600                 .ctrlbit        = (1 << 7),
601         }, {
602                 .name           = "i2c",
603                 .devname        = "s3c2440-i2c.2",
604                 .parent         = &clk_aclk_100.clk,
605                 .enable         = exynos4_clk_ip_peril_ctrl,
606                 .ctrlbit        = (1 << 8),
607         }, {
608                 .name           = "i2c",
609                 .devname        = "s3c2440-i2c.3",
610                 .parent         = &clk_aclk_100.clk,
611                 .enable         = exynos4_clk_ip_peril_ctrl,
612                 .ctrlbit        = (1 << 9),
613         }, {
614                 .name           = "i2c",
615                 .devname        = "s3c2440-i2c.4",
616                 .parent         = &clk_aclk_100.clk,
617                 .enable         = exynos4_clk_ip_peril_ctrl,
618                 .ctrlbit        = (1 << 10),
619         }, {
620                 .name           = "i2c",
621                 .devname        = "s3c2440-i2c.5",
622                 .parent         = &clk_aclk_100.clk,
623                 .enable         = exynos4_clk_ip_peril_ctrl,
624                 .ctrlbit        = (1 << 11),
625         }, {
626                 .name           = "i2c",
627                 .devname        = "s3c2440-i2c.6",
628                 .parent         = &clk_aclk_100.clk,
629                 .enable         = exynos4_clk_ip_peril_ctrl,
630                 .ctrlbit        = (1 << 12),
631         }, {
632                 .name           = "i2c",
633                 .devname        = "s3c2440-i2c.7",
634                 .parent         = &clk_aclk_100.clk,
635                 .enable         = exynos4_clk_ip_peril_ctrl,
636                 .ctrlbit        = (1 << 13),
637         }, {
638                 .name           = "SYSMMU_MDMA",
639                 .enable         = exynos4_clk_ip_image_ctrl,
640                 .ctrlbit        = (1 << 5),
641         }, {
642                 .name           = "SYSMMU_FIMC0",
643                 .enable         = exynos4_clk_ip_cam_ctrl,
644                 .ctrlbit        = (1 << 7),
645         }, {
646                 .name           = "SYSMMU_FIMC1",
647                 .enable         = exynos4_clk_ip_cam_ctrl,
648                 .ctrlbit        = (1 << 8),
649         }, {
650                 .name           = "SYSMMU_FIMC2",
651                 .enable         = exynos4_clk_ip_cam_ctrl,
652                 .ctrlbit        = (1 << 9),
653         }, {
654                 .name           = "SYSMMU_FIMC3",
655                 .enable         = exynos4_clk_ip_cam_ctrl,
656                 .ctrlbit        = (1 << 10),
657         }, {
658                 .name           = "SYSMMU_JPEG",
659                 .enable         = exynos4_clk_ip_cam_ctrl,
660                 .ctrlbit        = (1 << 11),
661         }, {
662                 .name           = "SYSMMU_FIMD0",
663                 .enable         = exynos4_clk_ip_lcd0_ctrl,
664                 .ctrlbit        = (1 << 4),
665         }, {
666                 .name           = "SYSMMU_FIMD1",
667                 .enable         = exynos4_clk_ip_lcd1_ctrl,
668                 .ctrlbit        = (1 << 4),
669         }, {
670                 .name           = "SYSMMU_PCIe",
671                 .enable         = exynos4_clk_ip_fsys_ctrl,
672                 .ctrlbit        = (1 << 18),
673         }, {
674                 .name           = "SYSMMU_G2D",
675                 .enable         = exynos4_clk_ip_image_ctrl,
676                 .ctrlbit        = (1 << 3),
677         }, {
678                 .name           = "SYSMMU_ROTATOR",
679                 .enable         = exynos4_clk_ip_image_ctrl,
680                 .ctrlbit        = (1 << 4),
681         }, {
682                 .name           = "SYSMMU_TV",
683                 .enable         = exynos4_clk_ip_tv_ctrl,
684                 .ctrlbit        = (1 << 4),
685         }, {
686                 .name           = "SYSMMU_MFC_L",
687                 .enable         = exynos4_clk_ip_mfc_ctrl,
688                 .ctrlbit        = (1 << 1),
689         }, {
690                 .name           = "SYSMMU_MFC_R",
691                 .enable         = exynos4_clk_ip_mfc_ctrl,
692                 .ctrlbit        = (1 << 2),
693         }
694 };
695
696 static struct clk init_clocks[] = {
697         {
698                 .name           = "uart",
699                 .devname        = "s5pv210-uart.0",
700                 .enable         = exynos4_clk_ip_peril_ctrl,
701                 .ctrlbit        = (1 << 0),
702         }, {
703                 .name           = "uart",
704                 .devname        = "s5pv210-uart.1",
705                 .enable         = exynos4_clk_ip_peril_ctrl,
706                 .ctrlbit        = (1 << 1),
707         }, {
708                 .name           = "uart",
709                 .devname        = "s5pv210-uart.2",
710                 .enable         = exynos4_clk_ip_peril_ctrl,
711                 .ctrlbit        = (1 << 2),
712         }, {
713                 .name           = "uart",
714                 .devname        = "s5pv210-uart.3",
715                 .enable         = exynos4_clk_ip_peril_ctrl,
716                 .ctrlbit        = (1 << 3),
717         }, {
718                 .name           = "uart",
719                 .devname        = "s5pv210-uart.4",
720                 .enable         = exynos4_clk_ip_peril_ctrl,
721                 .ctrlbit        = (1 << 4),
722         }, {
723                 .name           = "uart",
724                 .devname        = "s5pv210-uart.5",
725                 .enable         = exynos4_clk_ip_peril_ctrl,
726                 .ctrlbit        = (1 << 5),
727         }
728 };
729
730 struct clk *clkset_group_list[] = {
731         [0] = &clk_ext_xtal_mux,
732         [1] = &clk_xusbxti,
733         [2] = &clk_sclk_hdmi27m,
734         [3] = &clk_sclk_usbphy0,
735         [4] = &clk_sclk_usbphy1,
736         [5] = &clk_sclk_hdmiphy,
737         [6] = &clk_mout_mpll.clk,
738         [7] = &clk_mout_epll.clk,
739         [8] = &clk_sclk_vpll.clk,
740 };
741
742 struct clksrc_sources clkset_group = {
743         .sources        = clkset_group_list,
744         .nr_sources     = ARRAY_SIZE(clkset_group_list),
745 };
746
747 static struct clk *clkset_mout_g2d0_list[] = {
748         [0] = &clk_mout_mpll.clk,
749         [1] = &clk_sclk_apll.clk,
750 };
751
752 static struct clksrc_sources clkset_mout_g2d0 = {
753         .sources        = clkset_mout_g2d0_list,
754         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d0_list),
755 };
756
757 static struct clksrc_clk clk_mout_g2d0 = {
758         .clk    = {
759                 .name           = "mout_g2d0",
760         },
761         .sources        = &clkset_mout_g2d0,
762         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
763 };
764
765 static struct clk *clkset_mout_g2d1_list[] = {
766         [0] = &clk_mout_epll.clk,
767         [1] = &clk_sclk_vpll.clk,
768 };
769
770 static struct clksrc_sources clkset_mout_g2d1 = {
771         .sources        = clkset_mout_g2d1_list,
772         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d1_list),
773 };
774
775 static struct clksrc_clk clk_mout_g2d1 = {
776         .clk    = {
777                 .name           = "mout_g2d1",
778         },
779         .sources        = &clkset_mout_g2d1,
780         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
781 };
782
783 static struct clk *clkset_mout_g2d_list[] = {
784         [0] = &clk_mout_g2d0.clk,
785         [1] = &clk_mout_g2d1.clk,
786 };
787
788 static struct clksrc_sources clkset_mout_g2d = {
789         .sources        = clkset_mout_g2d_list,
790         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d_list),
791 };
792
793 static struct clk *clkset_mout_mfc0_list[] = {
794         [0] = &clk_mout_mpll.clk,
795         [1] = &clk_sclk_apll.clk,
796 };
797
798 static struct clksrc_sources clkset_mout_mfc0 = {
799         .sources        = clkset_mout_mfc0_list,
800         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc0_list),
801 };
802
803 static struct clksrc_clk clk_mout_mfc0 = {
804         .clk    = {
805                 .name           = "mout_mfc0",
806         },
807         .sources        = &clkset_mout_mfc0,
808         .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
809 };
810
811 static struct clk *clkset_mout_mfc1_list[] = {
812         [0] = &clk_mout_epll.clk,
813         [1] = &clk_sclk_vpll.clk,
814 };
815
816 static struct clksrc_sources clkset_mout_mfc1 = {
817         .sources        = clkset_mout_mfc1_list,
818         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc1_list),
819 };
820
821 static struct clksrc_clk clk_mout_mfc1 = {
822         .clk    = {
823                 .name           = "mout_mfc1",
824         },
825         .sources        = &clkset_mout_mfc1,
826         .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
827 };
828
829 static struct clk *clkset_mout_mfc_list[] = {
830         [0] = &clk_mout_mfc0.clk,
831         [1] = &clk_mout_mfc1.clk,
832 };
833
834 static struct clksrc_sources clkset_mout_mfc = {
835         .sources        = clkset_mout_mfc_list,
836         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc_list),
837 };
838
839 static struct clksrc_clk clk_dout_mmc0 = {
840         .clk            = {
841                 .name           = "dout_mmc0",
842         },
843         .sources = &clkset_group,
844         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
845         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
846 };
847
848 static struct clksrc_clk clk_dout_mmc1 = {
849         .clk            = {
850                 .name           = "dout_mmc1",
851         },
852         .sources = &clkset_group,
853         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
854         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
855 };
856
857 static struct clksrc_clk clk_dout_mmc2 = {
858         .clk            = {
859                 .name           = "dout_mmc2",
860         },
861         .sources = &clkset_group,
862         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
863         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
864 };
865
866 static struct clksrc_clk clk_dout_mmc3 = {
867         .clk            = {
868                 .name           = "dout_mmc3",
869         },
870         .sources = &clkset_group,
871         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
872         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
873 };
874
875 static struct clksrc_clk clk_dout_mmc4 = {
876         .clk            = {
877                 .name           = "dout_mmc4",
878         },
879         .sources = &clkset_group,
880         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
881         .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
882 };
883
884 static struct clksrc_clk clksrcs[] = {
885         {
886                 .clk    = {
887                         .name           = "uclk1",
888                         .devname        = "s5pv210-uart.0",
889                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
890                         .ctrlbit        = (1 << 0),
891                 },
892                 .sources = &clkset_group,
893                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
894                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
895         }, {
896                 .clk            = {
897                         .name           = "uclk1",
898                         .devname        = "s5pv210-uart.1",
899                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
900                         .ctrlbit        = (1 << 4),
901                 },
902                 .sources = &clkset_group,
903                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
904                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
905         }, {
906                 .clk            = {
907                         .name           = "uclk1",
908                         .devname        = "s5pv210-uart.2",
909                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
910                         .ctrlbit        = (1 << 8),
911                 },
912                 .sources = &clkset_group,
913                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
914                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
915         }, {
916                 .clk            = {
917                         .name           = "uclk1",
918                         .devname        = "s5pv210-uart.3",
919                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
920                         .ctrlbit        = (1 << 12),
921                 },
922                 .sources = &clkset_group,
923                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
924                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
925         }, {
926                 .clk            = {
927                         .name           = "sclk_pwm",
928                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
929                         .ctrlbit        = (1 << 24),
930                 },
931                 .sources = &clkset_group,
932                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
933                 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
934         }, {
935                 .clk            = {
936                         .name           = "sclk_csis",
937                         .devname        = "s5p-mipi-csis.0",
938                         .enable         = exynos4_clksrc_mask_cam_ctrl,
939                         .ctrlbit        = (1 << 24),
940                 },
941                 .sources = &clkset_group,
942                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
943                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
944         }, {
945                 .clk            = {
946                         .name           = "sclk_csis",
947                         .devname        = "s5p-mipi-csis.1",
948                         .enable         = exynos4_clksrc_mask_cam_ctrl,
949                         .ctrlbit        = (1 << 28),
950                 },
951                 .sources = &clkset_group,
952                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
953                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
954         }, {
955                 .clk            = {
956                         .name           = "sclk_cam0",
957                         .enable         = exynos4_clksrc_mask_cam_ctrl,
958                         .ctrlbit        = (1 << 16),
959                 },
960                 .sources = &clkset_group,
961                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
962                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
963         }, {
964                 .clk            = {
965                         .name           = "sclk_cam1",
966                         .enable         = exynos4_clksrc_mask_cam_ctrl,
967                         .ctrlbit        = (1 << 20),
968                 },
969                 .sources = &clkset_group,
970                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
971                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
972         }, {
973                 .clk            = {
974                         .name           = "sclk_fimc",
975                         .devname        = "exynos4-fimc.0",
976                         .enable         = exynos4_clksrc_mask_cam_ctrl,
977                         .ctrlbit        = (1 << 0),
978                 },
979                 .sources = &clkset_group,
980                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
981                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
982         }, {
983                 .clk            = {
984                         .name           = "sclk_fimc",
985                         .devname        = "exynos4-fimc.1",
986                         .enable         = exynos4_clksrc_mask_cam_ctrl,
987                         .ctrlbit        = (1 << 4),
988                 },
989                 .sources = &clkset_group,
990                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
991                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
992         }, {
993                 .clk            = {
994                         .name           = "sclk_fimc",
995                         .devname        = "exynos4-fimc.2",
996                         .enable         = exynos4_clksrc_mask_cam_ctrl,
997                         .ctrlbit        = (1 << 8),
998                 },
999                 .sources = &clkset_group,
1000                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
1001                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
1002         }, {
1003                 .clk            = {
1004                         .name           = "sclk_fimc",
1005                         .devname        = "exynos4-fimc.3",
1006                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1007                         .ctrlbit        = (1 << 12),
1008                 },
1009                 .sources = &clkset_group,
1010                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
1011                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
1012         }, {
1013                 .clk            = {
1014                         .name           = "sclk_fimd",
1015                         .devname        = "exynos4-fb.0",
1016                         .enable         = exynos4_clksrc_mask_lcd0_ctrl,
1017                         .ctrlbit        = (1 << 0),
1018                 },
1019                 .sources = &clkset_group,
1020                 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
1021                 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
1022         }, {
1023                 .clk            = {
1024                         .name           = "sclk_spi",
1025                         .devname        = "s3c64xx-spi.0",
1026                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
1027                         .ctrlbit        = (1 << 16),
1028                 },
1029                 .sources = &clkset_group,
1030                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1031                 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1032         }, {
1033                 .clk            = {
1034                         .name           = "sclk_spi",
1035                         .devname        = "s3c64xx-spi.1",
1036                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
1037                         .ctrlbit        = (1 << 20),
1038                 },
1039                 .sources = &clkset_group,
1040                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1041                 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1042         }, {
1043                 .clk            = {
1044                         .name           = "sclk_spi",
1045                         .devname        = "s3c64xx-spi.2",
1046                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
1047                         .ctrlbit        = (1 << 24),
1048                 },
1049                 .sources = &clkset_group,
1050                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1051                 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1052         }, {
1053                 .clk            = {
1054                         .name           = "sclk_fimg2d",
1055                 },
1056                 .sources = &clkset_mout_g2d,
1057                 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1058                 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1059         }, {
1060                 .clk            = {
1061                         .name           = "sclk_mfc",
1062                         .devname        = "s5p-mfc",
1063                 },
1064                 .sources = &clkset_mout_mfc,
1065                 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1066                 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1067         }, {
1068                 .clk            = {
1069                         .name           = "sclk_mmc",
1070                         .devname        = "s3c-sdhci.0",
1071                         .parent         = &clk_dout_mmc0.clk,
1072                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1073                         .ctrlbit        = (1 << 0),
1074                 },
1075                 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1076         }, {
1077                 .clk            = {
1078                         .name           = "sclk_mmc",
1079                         .devname        = "s3c-sdhci.1",
1080                         .parent         = &clk_dout_mmc1.clk,
1081                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1082                         .ctrlbit        = (1 << 4),
1083                 },
1084                 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1085         }, {
1086                 .clk            = {
1087                         .name           = "sclk_mmc",
1088                         .devname        = "s3c-sdhci.2",
1089                         .parent         = &clk_dout_mmc2.clk,
1090                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1091                         .ctrlbit        = (1 << 8),
1092                 },
1093                 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1094         }, {
1095                 .clk            = {
1096                         .name           = "sclk_mmc",
1097                         .devname        = "s3c-sdhci.3",
1098                         .parent         = &clk_dout_mmc3.clk,
1099                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1100                         .ctrlbit        = (1 << 12),
1101                 },
1102                 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1103         }, {
1104                 .clk            = {
1105                         .name           = "sclk_dwmmc",
1106                         .parent         = &clk_dout_mmc4.clk,
1107                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1108                         .ctrlbit        = (1 << 16),
1109                 },
1110                 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1111         }
1112 };
1113
1114 /* Clock initialization code */
1115 static struct clksrc_clk *sysclks[] = {
1116         &clk_mout_apll,
1117         &clk_sclk_apll,
1118         &clk_mout_epll,
1119         &clk_mout_mpll,
1120         &clk_moutcore,
1121         &clk_coreclk,
1122         &clk_armclk,
1123         &clk_aclk_corem0,
1124         &clk_aclk_cores,
1125         &clk_aclk_corem1,
1126         &clk_periphclk,
1127         &clk_mout_corebus,
1128         &clk_sclk_dmc,
1129         &clk_aclk_cored,
1130         &clk_aclk_corep,
1131         &clk_aclk_acp,
1132         &clk_pclk_acp,
1133         &clk_vpllsrc,
1134         &clk_sclk_vpll,
1135         &clk_aclk_200,
1136         &clk_aclk_100,
1137         &clk_aclk_160,
1138         &clk_aclk_133,
1139         &clk_dout_mmc0,
1140         &clk_dout_mmc1,
1141         &clk_dout_mmc2,
1142         &clk_dout_mmc3,
1143         &clk_dout_mmc4,
1144         &clk_mout_mfc0,
1145         &clk_mout_mfc1,
1146 };
1147
1148 static int xtal_rate;
1149
1150 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1151 {
1152         if (soc_is_exynos4210())
1153                 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
1154                                         pll_4508);
1155         else if (soc_is_exynos4212() || soc_is_exynos4412())
1156                 return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
1157         else
1158                 return 0;
1159 }
1160
1161 static struct clk_ops exynos4_fout_apll_ops = {
1162         .get_rate = exynos4_fout_apll_get_rate,
1163 };
1164
1165 void __init_or_cpufreq exynos4_setup_clocks(void)
1166 {
1167         struct clk *xtal_clk;
1168         unsigned long apll = 0;
1169         unsigned long mpll = 0;
1170         unsigned long epll = 0;
1171         unsigned long vpll = 0;
1172         unsigned long vpllsrc;
1173         unsigned long xtal;
1174         unsigned long armclk;
1175         unsigned long sclk_dmc;
1176         unsigned long aclk_200;
1177         unsigned long aclk_100;
1178         unsigned long aclk_160;
1179         unsigned long aclk_133;
1180         unsigned int ptr;
1181
1182         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1183
1184         xtal_clk = clk_get(NULL, "xtal");
1185         BUG_ON(IS_ERR(xtal_clk));
1186
1187         xtal = clk_get_rate(xtal_clk);
1188
1189         xtal_rate = xtal;
1190
1191         clk_put(xtal_clk);
1192
1193         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1194
1195         if (soc_is_exynos4210()) {
1196                 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
1197                                         pll_4508);
1198                 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
1199                                         pll_4508);
1200                 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1201                                         __raw_readl(S5P_EPLL_CON1), pll_4600);
1202
1203                 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1204                 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1205                                         __raw_readl(S5P_VPLL_CON1), pll_4650c);
1206         } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1207                 apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
1208                 mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
1209                 epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
1210                                         __raw_readl(S5P_EPLL_CON1));
1211
1212                 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1213                 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1214                                         __raw_readl(S5P_VPLL_CON1));
1215         } else {
1216                 /* nothing */
1217         }
1218
1219         clk_fout_apll.ops = &exynos4_fout_apll_ops;
1220         clk_fout_mpll.rate = mpll;
1221         clk_fout_epll.rate = epll;
1222         clk_fout_vpll.rate = vpll;
1223
1224         printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1225                         apll, mpll, epll, vpll);
1226
1227         armclk = clk_get_rate(&clk_armclk.clk);
1228         sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1229
1230         aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1231         aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1232         aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1233         aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1234
1235         printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1236                          "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1237                         armclk, sclk_dmc, aclk_200,
1238                         aclk_100, aclk_160, aclk_133);
1239
1240         clk_f.rate = armclk;
1241         clk_h.rate = sclk_dmc;
1242         clk_p.rate = aclk_100;
1243
1244         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1245                 s3c_set_clksrc(&clksrcs[ptr], true);
1246 }
1247
1248 static struct clk *clks[] __initdata = {
1249         /* Nothing here yet */
1250 };
1251
1252 #ifdef CONFIG_PM_SLEEP
1253 static int exynos4_clock_suspend(void)
1254 {
1255         s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1256         return 0;
1257 }
1258
1259 static void exynos4_clock_resume(void)
1260 {
1261         s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1262 }
1263
1264 #else
1265 #define exynos4_clock_suspend NULL
1266 #define exynos4_clock_resume NULL
1267 #endif
1268
1269 struct syscore_ops exynos4_clock_syscore_ops = {
1270         .suspend        = exynos4_clock_suspend,
1271         .resume         = exynos4_clock_resume,
1272 };
1273
1274 void __init exynos4_register_clocks(void)
1275 {
1276         int ptr;
1277
1278         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1279
1280         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1281                 s3c_register_clksrc(sysclks[ptr], 1);
1282
1283         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1284         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1285
1286         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1287         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1288
1289 <<<<<<< HEAD
1290         register_syscore_ops(&exynos4_clock_syscore_ops);
1291 =======
1292         s3c24xx_register_clock(&dummy_apb_pclk);
1293
1294 >>>>>>> 4598fc2c94b68740e0269db03c98a1e7ad5af773
1295         s3c_pwmclk_init();
1296 }