1 /* linux/arch/arm/mach-exynos4/clock.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * EXYNOS4 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/err.h>
16 #include <linux/syscore_ops.h>
18 #include <plat/cpu-freq.h>
19 #include <plat/clock.h>
22 #include <plat/s5p-clock.h>
23 #include <plat/clock-clksrc.h>
24 #include <plat/exynos4.h>
28 #include <mach/regs-clock.h>
29 #include <mach/sysmmu.h>
30 #include <mach/exynos4-clock.h>
32 static struct sleep_save exynos4_clock_save[] = {
33 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
34 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
35 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
36 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
37 SAVE_ITEM(S5P_CLKSRC_TOP0),
38 SAVE_ITEM(S5P_CLKSRC_TOP1),
39 SAVE_ITEM(S5P_CLKSRC_CAM),
40 SAVE_ITEM(S5P_CLKSRC_TV),
41 SAVE_ITEM(S5P_CLKSRC_MFC),
42 SAVE_ITEM(S5P_CLKSRC_G3D),
43 SAVE_ITEM(S5P_CLKSRC_LCD0),
44 SAVE_ITEM(S5P_CLKSRC_MAUDIO),
45 SAVE_ITEM(S5P_CLKSRC_FSYS),
46 SAVE_ITEM(S5P_CLKSRC_PERIL0),
47 SAVE_ITEM(S5P_CLKSRC_PERIL1),
48 SAVE_ITEM(S5P_CLKDIV_CAM),
49 SAVE_ITEM(S5P_CLKDIV_TV),
50 SAVE_ITEM(S5P_CLKDIV_MFC),
51 SAVE_ITEM(S5P_CLKDIV_G3D),
52 SAVE_ITEM(S5P_CLKDIV_LCD0),
53 SAVE_ITEM(S5P_CLKDIV_MAUDIO),
54 SAVE_ITEM(S5P_CLKDIV_FSYS0),
55 SAVE_ITEM(S5P_CLKDIV_FSYS1),
56 SAVE_ITEM(S5P_CLKDIV_FSYS2),
57 SAVE_ITEM(S5P_CLKDIV_FSYS3),
58 SAVE_ITEM(S5P_CLKDIV_PERIL0),
59 SAVE_ITEM(S5P_CLKDIV_PERIL1),
60 SAVE_ITEM(S5P_CLKDIV_PERIL2),
61 SAVE_ITEM(S5P_CLKDIV_PERIL3),
62 SAVE_ITEM(S5P_CLKDIV_PERIL4),
63 SAVE_ITEM(S5P_CLKDIV_PERIL5),
64 SAVE_ITEM(S5P_CLKDIV_TOP),
65 SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
66 SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
67 SAVE_ITEM(S5P_CLKSRC_MASK_TV),
68 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
69 SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
70 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
71 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
72 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
73 SAVE_ITEM(S5P_CLKDIV2_RATIO),
74 SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
75 SAVE_ITEM(S5P_CLKGATE_IP_CAM),
76 SAVE_ITEM(S5P_CLKGATE_IP_TV),
77 SAVE_ITEM(S5P_CLKGATE_IP_MFC),
78 SAVE_ITEM(S5P_CLKGATE_IP_G3D),
79 SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
80 SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
81 SAVE_ITEM(S5P_CLKGATE_IP_GPS),
82 SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
83 SAVE_ITEM(S5P_CLKGATE_BLOCK),
84 SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
85 SAVE_ITEM(S5P_CLKSRC_DMC),
86 SAVE_ITEM(S5P_CLKDIV_DMC0),
87 SAVE_ITEM(S5P_CLKDIV_DMC1),
88 SAVE_ITEM(S5P_CLKGATE_IP_DMC),
89 SAVE_ITEM(S5P_CLKSRC_CPU),
90 SAVE_ITEM(S5P_CLKDIV_CPU),
91 SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
92 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
93 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
96 struct clk clk_sclk_hdmi27m = {
97 .name = "sclk_hdmi27m",
101 struct clk clk_sclk_hdmiphy = {
102 .name = "sclk_hdmiphy",
105 struct clk clk_sclk_usbphy0 = {
106 .name = "sclk_usbphy0",
110 struct clk clk_sclk_usbphy1 = {
111 .name = "sclk_usbphy1",
114 static struct clk dummy_apb_pclk = {
119 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
121 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
124 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
126 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
129 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
131 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
134 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
136 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
139 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
141 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
144 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
146 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
149 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
151 return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
154 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
156 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
159 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
161 return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
164 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
166 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
169 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
171 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
174 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
176 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
179 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
181 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
184 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
186 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
189 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
191 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
194 /* Core list of CMU_CPU side */
196 static struct clksrc_clk clk_mout_apll = {
200 .sources = &clk_src_apll,
201 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
204 struct clksrc_clk clk_sclk_apll = {
207 .parent = &clk_mout_apll.clk,
209 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
212 struct clksrc_clk clk_mout_epll = {
216 .sources = &clk_src_epll,
217 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
220 struct clksrc_clk clk_mout_mpll = {
224 .sources = &clk_src_mpll,
226 /* reg_src will be added in each SoCs' clock */
229 static struct clk *clkset_moutcore_list[] = {
230 [0] = &clk_mout_apll.clk,
231 [1] = &clk_mout_mpll.clk,
234 static struct clksrc_sources clkset_moutcore = {
235 .sources = clkset_moutcore_list,
236 .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
239 static struct clksrc_clk clk_moutcore = {
243 .sources = &clkset_moutcore,
244 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
247 static struct clksrc_clk clk_coreclk = {
250 .parent = &clk_moutcore.clk,
252 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
255 static struct clksrc_clk clk_armclk = {
258 .parent = &clk_coreclk.clk,
262 static struct clksrc_clk clk_aclk_corem0 = {
264 .name = "aclk_corem0",
265 .parent = &clk_coreclk.clk,
267 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
270 static struct clksrc_clk clk_aclk_cores = {
272 .name = "aclk_cores",
273 .parent = &clk_coreclk.clk,
275 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
278 static struct clksrc_clk clk_aclk_corem1 = {
280 .name = "aclk_corem1",
281 .parent = &clk_coreclk.clk,
283 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
286 static struct clksrc_clk clk_periphclk = {
289 .parent = &clk_coreclk.clk,
291 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
294 /* Core list of CMU_CORE side */
296 struct clk *clkset_corebus_list[] = {
297 [0] = &clk_mout_mpll.clk,
298 [1] = &clk_sclk_apll.clk,
301 struct clksrc_sources clkset_mout_corebus = {
302 .sources = clkset_corebus_list,
303 .nr_sources = ARRAY_SIZE(clkset_corebus_list),
306 static struct clksrc_clk clk_mout_corebus = {
308 .name = "mout_corebus",
310 .sources = &clkset_mout_corebus,
311 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
314 static struct clksrc_clk clk_sclk_dmc = {
317 .parent = &clk_mout_corebus.clk,
319 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
322 static struct clksrc_clk clk_aclk_cored = {
324 .name = "aclk_cored",
325 .parent = &clk_sclk_dmc.clk,
327 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
330 static struct clksrc_clk clk_aclk_corep = {
332 .name = "aclk_corep",
333 .parent = &clk_aclk_cored.clk,
335 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
338 static struct clksrc_clk clk_aclk_acp = {
341 .parent = &clk_mout_corebus.clk,
343 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
346 static struct clksrc_clk clk_pclk_acp = {
349 .parent = &clk_aclk_acp.clk,
351 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
354 /* Core list of CMU_TOP side */
356 struct clk *clkset_aclk_top_list[] = {
357 [0] = &clk_mout_mpll.clk,
358 [1] = &clk_sclk_apll.clk,
361 struct clksrc_sources clkset_aclk = {
362 .sources = clkset_aclk_top_list,
363 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
366 static struct clksrc_clk clk_aclk_200 = {
370 .sources = &clkset_aclk,
371 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
372 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
375 static struct clksrc_clk clk_aclk_100 = {
379 .sources = &clkset_aclk,
380 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
381 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
384 static struct clksrc_clk clk_aclk_160 = {
388 .sources = &clkset_aclk,
389 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
390 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
393 struct clksrc_clk clk_aclk_133 = {
397 .sources = &clkset_aclk,
398 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
399 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
402 static struct clk *clkset_vpllsrc_list[] = {
404 [1] = &clk_sclk_hdmi27m,
407 static struct clksrc_sources clkset_vpllsrc = {
408 .sources = clkset_vpllsrc_list,
409 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
412 static struct clksrc_clk clk_vpllsrc = {
415 .enable = exynos4_clksrc_mask_top_ctrl,
418 .sources = &clkset_vpllsrc,
419 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
422 static struct clk *clkset_sclk_vpll_list[] = {
423 [0] = &clk_vpllsrc.clk,
424 [1] = &clk_fout_vpll,
427 static struct clksrc_sources clkset_sclk_vpll = {
428 .sources = clkset_sclk_vpll_list,
429 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
432 struct clksrc_clk clk_sclk_vpll = {
436 .sources = &clkset_sclk_vpll,
437 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
440 static struct clk init_clocks_off[] = {
443 .parent = &clk_aclk_100.clk,
444 .enable = exynos4_clk_ip_peril_ctrl,
448 .devname = "s5p-mipi-csis.0",
449 .enable = exynos4_clk_ip_cam_ctrl,
453 .devname = "s5p-mipi-csis.1",
454 .enable = exynos4_clk_ip_cam_ctrl,
458 .devname = "exynos4-fimc.0",
459 .enable = exynos4_clk_ip_cam_ctrl,
463 .devname = "exynos4-fimc.1",
464 .enable = exynos4_clk_ip_cam_ctrl,
468 .devname = "exynos4-fimc.2",
469 .enable = exynos4_clk_ip_cam_ctrl,
473 .devname = "exynos4-fimc.3",
474 .enable = exynos4_clk_ip_cam_ctrl,
478 .devname = "exynos4-fb.0",
479 .enable = exynos4_clk_ip_lcd0_ctrl,
483 .devname = "s3c-sdhci.0",
484 .parent = &clk_aclk_133.clk,
485 .enable = exynos4_clk_ip_fsys_ctrl,
489 .devname = "s3c-sdhci.1",
490 .parent = &clk_aclk_133.clk,
491 .enable = exynos4_clk_ip_fsys_ctrl,
495 .devname = "s3c-sdhci.2",
496 .parent = &clk_aclk_133.clk,
497 .enable = exynos4_clk_ip_fsys_ctrl,
501 .devname = "s3c-sdhci.3",
502 .parent = &clk_aclk_133.clk,
503 .enable = exynos4_clk_ip_fsys_ctrl,
507 .parent = &clk_aclk_133.clk,
508 .enable = exynos4_clk_ip_fsys_ctrl,
512 .devname = "s3c-pl330.0",
513 .enable = exynos4_clk_ip_fsys_ctrl,
517 .devname = "s3c-pl330.1",
518 .enable = exynos4_clk_ip_fsys_ctrl,
522 .enable = exynos4_clk_ip_peril_ctrl,
523 .ctrlbit = (1 << 15),
526 .enable = exynos4_clk_ip_perir_ctrl,
527 .ctrlbit = (1 << 16),
530 .enable = exynos4_clk_ip_perir_ctrl,
531 .ctrlbit = (1 << 15),
534 .parent = &clk_aclk_100.clk,
535 .enable = exynos4_clk_ip_perir_ctrl,
536 .ctrlbit = (1 << 14),
539 .enable = exynos4_clk_ip_fsys_ctrl ,
540 .ctrlbit = (1 << 12),
543 .enable = exynos4_clk_ip_fsys_ctrl,
544 .ctrlbit = (1 << 13),
547 .devname = "s3c64xx-spi.0",
548 .enable = exynos4_clk_ip_peril_ctrl,
549 .ctrlbit = (1 << 16),
552 .devname = "s3c64xx-spi.1",
553 .enable = exynos4_clk_ip_peril_ctrl,
554 .ctrlbit = (1 << 17),
557 .devname = "s3c64xx-spi.2",
558 .enable = exynos4_clk_ip_peril_ctrl,
559 .ctrlbit = (1 << 18),
562 .devname = "samsung-i2s.0",
563 .enable = exynos4_clk_ip_peril_ctrl,
564 .ctrlbit = (1 << 19),
567 .devname = "samsung-i2s.1",
568 .enable = exynos4_clk_ip_peril_ctrl,
569 .ctrlbit = (1 << 20),
572 .devname = "samsung-i2s.2",
573 .enable = exynos4_clk_ip_peril_ctrl,
574 .ctrlbit = (1 << 21),
577 .devname = "samsung-ac97",
578 .enable = exynos4_clk_ip_peril_ctrl,
579 .ctrlbit = (1 << 27),
582 .enable = exynos4_clk_ip_image_ctrl,
586 .devname = "s5p-mfc",
587 .enable = exynos4_clk_ip_mfc_ctrl,
591 .devname = "s3c2440-i2c.0",
592 .parent = &clk_aclk_100.clk,
593 .enable = exynos4_clk_ip_peril_ctrl,
597 .devname = "s3c2440-i2c.1",
598 .parent = &clk_aclk_100.clk,
599 .enable = exynos4_clk_ip_peril_ctrl,
603 .devname = "s3c2440-i2c.2",
604 .parent = &clk_aclk_100.clk,
605 .enable = exynos4_clk_ip_peril_ctrl,
609 .devname = "s3c2440-i2c.3",
610 .parent = &clk_aclk_100.clk,
611 .enable = exynos4_clk_ip_peril_ctrl,
615 .devname = "s3c2440-i2c.4",
616 .parent = &clk_aclk_100.clk,
617 .enable = exynos4_clk_ip_peril_ctrl,
618 .ctrlbit = (1 << 10),
621 .devname = "s3c2440-i2c.5",
622 .parent = &clk_aclk_100.clk,
623 .enable = exynos4_clk_ip_peril_ctrl,
624 .ctrlbit = (1 << 11),
627 .devname = "s3c2440-i2c.6",
628 .parent = &clk_aclk_100.clk,
629 .enable = exynos4_clk_ip_peril_ctrl,
630 .ctrlbit = (1 << 12),
633 .devname = "s3c2440-i2c.7",
634 .parent = &clk_aclk_100.clk,
635 .enable = exynos4_clk_ip_peril_ctrl,
636 .ctrlbit = (1 << 13),
638 .name = "SYSMMU_MDMA",
639 .enable = exynos4_clk_ip_image_ctrl,
642 .name = "SYSMMU_FIMC0",
643 .enable = exynos4_clk_ip_cam_ctrl,
646 .name = "SYSMMU_FIMC1",
647 .enable = exynos4_clk_ip_cam_ctrl,
650 .name = "SYSMMU_FIMC2",
651 .enable = exynos4_clk_ip_cam_ctrl,
654 .name = "SYSMMU_FIMC3",
655 .enable = exynos4_clk_ip_cam_ctrl,
656 .ctrlbit = (1 << 10),
658 .name = "SYSMMU_JPEG",
659 .enable = exynos4_clk_ip_cam_ctrl,
660 .ctrlbit = (1 << 11),
662 .name = "SYSMMU_FIMD0",
663 .enable = exynos4_clk_ip_lcd0_ctrl,
666 .name = "SYSMMU_FIMD1",
667 .enable = exynos4_clk_ip_lcd1_ctrl,
670 .name = "SYSMMU_PCIe",
671 .enable = exynos4_clk_ip_fsys_ctrl,
672 .ctrlbit = (1 << 18),
674 .name = "SYSMMU_G2D",
675 .enable = exynos4_clk_ip_image_ctrl,
678 .name = "SYSMMU_ROTATOR",
679 .enable = exynos4_clk_ip_image_ctrl,
683 .enable = exynos4_clk_ip_tv_ctrl,
686 .name = "SYSMMU_MFC_L",
687 .enable = exynos4_clk_ip_mfc_ctrl,
690 .name = "SYSMMU_MFC_R",
691 .enable = exynos4_clk_ip_mfc_ctrl,
696 static struct clk init_clocks[] = {
699 .devname = "s5pv210-uart.0",
700 .enable = exynos4_clk_ip_peril_ctrl,
704 .devname = "s5pv210-uart.1",
705 .enable = exynos4_clk_ip_peril_ctrl,
709 .devname = "s5pv210-uart.2",
710 .enable = exynos4_clk_ip_peril_ctrl,
714 .devname = "s5pv210-uart.3",
715 .enable = exynos4_clk_ip_peril_ctrl,
719 .devname = "s5pv210-uart.4",
720 .enable = exynos4_clk_ip_peril_ctrl,
724 .devname = "s5pv210-uart.5",
725 .enable = exynos4_clk_ip_peril_ctrl,
730 struct clk *clkset_group_list[] = {
731 [0] = &clk_ext_xtal_mux,
733 [2] = &clk_sclk_hdmi27m,
734 [3] = &clk_sclk_usbphy0,
735 [4] = &clk_sclk_usbphy1,
736 [5] = &clk_sclk_hdmiphy,
737 [6] = &clk_mout_mpll.clk,
738 [7] = &clk_mout_epll.clk,
739 [8] = &clk_sclk_vpll.clk,
742 struct clksrc_sources clkset_group = {
743 .sources = clkset_group_list,
744 .nr_sources = ARRAY_SIZE(clkset_group_list),
747 static struct clk *clkset_mout_g2d0_list[] = {
748 [0] = &clk_mout_mpll.clk,
749 [1] = &clk_sclk_apll.clk,
752 static struct clksrc_sources clkset_mout_g2d0 = {
753 .sources = clkset_mout_g2d0_list,
754 .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
757 static struct clksrc_clk clk_mout_g2d0 = {
761 .sources = &clkset_mout_g2d0,
762 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
765 static struct clk *clkset_mout_g2d1_list[] = {
766 [0] = &clk_mout_epll.clk,
767 [1] = &clk_sclk_vpll.clk,
770 static struct clksrc_sources clkset_mout_g2d1 = {
771 .sources = clkset_mout_g2d1_list,
772 .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
775 static struct clksrc_clk clk_mout_g2d1 = {
779 .sources = &clkset_mout_g2d1,
780 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
783 static struct clk *clkset_mout_g2d_list[] = {
784 [0] = &clk_mout_g2d0.clk,
785 [1] = &clk_mout_g2d1.clk,
788 static struct clksrc_sources clkset_mout_g2d = {
789 .sources = clkset_mout_g2d_list,
790 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
793 static struct clk *clkset_mout_mfc0_list[] = {
794 [0] = &clk_mout_mpll.clk,
795 [1] = &clk_sclk_apll.clk,
798 static struct clksrc_sources clkset_mout_mfc0 = {
799 .sources = clkset_mout_mfc0_list,
800 .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list),
803 static struct clksrc_clk clk_mout_mfc0 = {
807 .sources = &clkset_mout_mfc0,
808 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
811 static struct clk *clkset_mout_mfc1_list[] = {
812 [0] = &clk_mout_epll.clk,
813 [1] = &clk_sclk_vpll.clk,
816 static struct clksrc_sources clkset_mout_mfc1 = {
817 .sources = clkset_mout_mfc1_list,
818 .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list),
821 static struct clksrc_clk clk_mout_mfc1 = {
825 .sources = &clkset_mout_mfc1,
826 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
829 static struct clk *clkset_mout_mfc_list[] = {
830 [0] = &clk_mout_mfc0.clk,
831 [1] = &clk_mout_mfc1.clk,
834 static struct clksrc_sources clkset_mout_mfc = {
835 .sources = clkset_mout_mfc_list,
836 .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
839 static struct clksrc_clk clk_dout_mmc0 = {
843 .sources = &clkset_group,
844 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
845 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
848 static struct clksrc_clk clk_dout_mmc1 = {
852 .sources = &clkset_group,
853 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
854 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
857 static struct clksrc_clk clk_dout_mmc2 = {
861 .sources = &clkset_group,
862 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
863 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
866 static struct clksrc_clk clk_dout_mmc3 = {
870 .sources = &clkset_group,
871 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
872 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
875 static struct clksrc_clk clk_dout_mmc4 = {
879 .sources = &clkset_group,
880 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
881 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
884 static struct clksrc_clk clksrcs[] = {
888 .devname = "s5pv210-uart.0",
889 .enable = exynos4_clksrc_mask_peril0_ctrl,
892 .sources = &clkset_group,
893 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
894 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
898 .devname = "s5pv210-uart.1",
899 .enable = exynos4_clksrc_mask_peril0_ctrl,
902 .sources = &clkset_group,
903 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
904 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
908 .devname = "s5pv210-uart.2",
909 .enable = exynos4_clksrc_mask_peril0_ctrl,
912 .sources = &clkset_group,
913 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
914 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
918 .devname = "s5pv210-uart.3",
919 .enable = exynos4_clksrc_mask_peril0_ctrl,
920 .ctrlbit = (1 << 12),
922 .sources = &clkset_group,
923 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
924 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
928 .enable = exynos4_clksrc_mask_peril0_ctrl,
929 .ctrlbit = (1 << 24),
931 .sources = &clkset_group,
932 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
933 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
937 .devname = "s5p-mipi-csis.0",
938 .enable = exynos4_clksrc_mask_cam_ctrl,
939 .ctrlbit = (1 << 24),
941 .sources = &clkset_group,
942 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
943 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
947 .devname = "s5p-mipi-csis.1",
948 .enable = exynos4_clksrc_mask_cam_ctrl,
949 .ctrlbit = (1 << 28),
951 .sources = &clkset_group,
952 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
953 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
957 .enable = exynos4_clksrc_mask_cam_ctrl,
958 .ctrlbit = (1 << 16),
960 .sources = &clkset_group,
961 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
962 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
966 .enable = exynos4_clksrc_mask_cam_ctrl,
967 .ctrlbit = (1 << 20),
969 .sources = &clkset_group,
970 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
971 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
975 .devname = "exynos4-fimc.0",
976 .enable = exynos4_clksrc_mask_cam_ctrl,
979 .sources = &clkset_group,
980 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
981 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
985 .devname = "exynos4-fimc.1",
986 .enable = exynos4_clksrc_mask_cam_ctrl,
989 .sources = &clkset_group,
990 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
991 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
995 .devname = "exynos4-fimc.2",
996 .enable = exynos4_clksrc_mask_cam_ctrl,
999 .sources = &clkset_group,
1000 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
1001 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
1004 .name = "sclk_fimc",
1005 .devname = "exynos4-fimc.3",
1006 .enable = exynos4_clksrc_mask_cam_ctrl,
1007 .ctrlbit = (1 << 12),
1009 .sources = &clkset_group,
1010 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
1011 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
1014 .name = "sclk_fimd",
1015 .devname = "exynos4-fb.0",
1016 .enable = exynos4_clksrc_mask_lcd0_ctrl,
1017 .ctrlbit = (1 << 0),
1019 .sources = &clkset_group,
1020 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
1021 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
1025 .devname = "s3c64xx-spi.0",
1026 .enable = exynos4_clksrc_mask_peril1_ctrl,
1027 .ctrlbit = (1 << 16),
1029 .sources = &clkset_group,
1030 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1031 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1035 .devname = "s3c64xx-spi.1",
1036 .enable = exynos4_clksrc_mask_peril1_ctrl,
1037 .ctrlbit = (1 << 20),
1039 .sources = &clkset_group,
1040 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1041 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1045 .devname = "s3c64xx-spi.2",
1046 .enable = exynos4_clksrc_mask_peril1_ctrl,
1047 .ctrlbit = (1 << 24),
1049 .sources = &clkset_group,
1050 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1051 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1054 .name = "sclk_fimg2d",
1056 .sources = &clkset_mout_g2d,
1057 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1058 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1062 .devname = "s5p-mfc",
1064 .sources = &clkset_mout_mfc,
1065 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1066 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1070 .devname = "s3c-sdhci.0",
1071 .parent = &clk_dout_mmc0.clk,
1072 .enable = exynos4_clksrc_mask_fsys_ctrl,
1073 .ctrlbit = (1 << 0),
1075 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1079 .devname = "s3c-sdhci.1",
1080 .parent = &clk_dout_mmc1.clk,
1081 .enable = exynos4_clksrc_mask_fsys_ctrl,
1082 .ctrlbit = (1 << 4),
1084 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1088 .devname = "s3c-sdhci.2",
1089 .parent = &clk_dout_mmc2.clk,
1090 .enable = exynos4_clksrc_mask_fsys_ctrl,
1091 .ctrlbit = (1 << 8),
1093 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1097 .devname = "s3c-sdhci.3",
1098 .parent = &clk_dout_mmc3.clk,
1099 .enable = exynos4_clksrc_mask_fsys_ctrl,
1100 .ctrlbit = (1 << 12),
1102 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1105 .name = "sclk_dwmmc",
1106 .parent = &clk_dout_mmc4.clk,
1107 .enable = exynos4_clksrc_mask_fsys_ctrl,
1108 .ctrlbit = (1 << 16),
1110 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1114 /* Clock initialization code */
1115 static struct clksrc_clk *sysclks[] = {
1148 static int xtal_rate;
1150 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1152 if (soc_is_exynos4210())
1153 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
1155 else if (soc_is_exynos4212() || soc_is_exynos4412())
1156 return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
1161 static struct clk_ops exynos4_fout_apll_ops = {
1162 .get_rate = exynos4_fout_apll_get_rate,
1165 void __init_or_cpufreq exynos4_setup_clocks(void)
1167 struct clk *xtal_clk;
1168 unsigned long apll = 0;
1169 unsigned long mpll = 0;
1170 unsigned long epll = 0;
1171 unsigned long vpll = 0;
1172 unsigned long vpllsrc;
1174 unsigned long armclk;
1175 unsigned long sclk_dmc;
1176 unsigned long aclk_200;
1177 unsigned long aclk_100;
1178 unsigned long aclk_160;
1179 unsigned long aclk_133;
1182 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1184 xtal_clk = clk_get(NULL, "xtal");
1185 BUG_ON(IS_ERR(xtal_clk));
1187 xtal = clk_get_rate(xtal_clk);
1193 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1195 if (soc_is_exynos4210()) {
1196 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
1198 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
1200 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1201 __raw_readl(S5P_EPLL_CON1), pll_4600);
1203 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1204 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1205 __raw_readl(S5P_VPLL_CON1), pll_4650c);
1206 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1207 apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
1208 mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
1209 epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
1210 __raw_readl(S5P_EPLL_CON1));
1212 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1213 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1214 __raw_readl(S5P_VPLL_CON1));
1219 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1220 clk_fout_mpll.rate = mpll;
1221 clk_fout_epll.rate = epll;
1222 clk_fout_vpll.rate = vpll;
1224 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1225 apll, mpll, epll, vpll);
1227 armclk = clk_get_rate(&clk_armclk.clk);
1228 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1230 aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1231 aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1232 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1233 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1235 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1236 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1237 armclk, sclk_dmc, aclk_200,
1238 aclk_100, aclk_160, aclk_133);
1240 clk_f.rate = armclk;
1241 clk_h.rate = sclk_dmc;
1242 clk_p.rate = aclk_100;
1244 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1245 s3c_set_clksrc(&clksrcs[ptr], true);
1248 static struct clk *clks[] __initdata = {
1249 /* Nothing here yet */
1252 #ifdef CONFIG_PM_SLEEP
1253 static int exynos4_clock_suspend(void)
1255 s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1259 static void exynos4_clock_resume(void)
1261 s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1265 #define exynos4_clock_suspend NULL
1266 #define exynos4_clock_resume NULL
1269 struct syscore_ops exynos4_clock_syscore_ops = {
1270 .suspend = exynos4_clock_suspend,
1271 .resume = exynos4_clock_resume,
1274 void __init exynos4_register_clocks(void)
1278 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1280 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1281 s3c_register_clksrc(sysclks[ptr], 1);
1283 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1284 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1286 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1287 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1289 register_syscore_ops(&exynos4_clock_syscore_ops);
1290 s3c24xx_register_clock(&dummy_apb_pclk);