arch/arm/mach-exynos4/clock.c

   1 /* linux/arch/arm/mach-exynos4/clock.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * EXYNOS4 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/err.h>
  15 #include <linux/io.h>
  16 #include <linux/syscore_ops.h>
  17
  18 #include <plat/cpu-freq.h>
  19 #include <plat/clock.h>
  20 #include <plat/cpu.h>
  21 #include <plat/pll.h>
  22 #include <plat/s5p-clock.h>
  23 #include <plat/clock-clksrc.h>
  24 #include <plat/exynos4.h>
  25 #include <plat/pm.h>
  26
  27 #include <mach/map.h>
  28 #include <mach/regs-clock.h>
  29 #include <mach/sysmmu.h>
  30 #include <mach/exynos4-clock.h>
  31
  32 static struct sleep_save exynos4_clock_save[] = {
  33         SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
  34         SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
  35         SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
  36         SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
  37         SAVE_ITEM(S5P_CLKSRC_TOP0),
  38         SAVE_ITEM(S5P_CLKSRC_TOP1),
  39         SAVE_ITEM(S5P_CLKSRC_CAM),
  40         SAVE_ITEM(S5P_CLKSRC_TV),
  41         SAVE_ITEM(S5P_CLKSRC_MFC),
  42         SAVE_ITEM(S5P_CLKSRC_G3D),
  43         SAVE_ITEM(S5P_CLKSRC_LCD0),
  44         SAVE_ITEM(S5P_CLKSRC_MAUDIO),
  45         SAVE_ITEM(S5P_CLKSRC_FSYS),
  46         SAVE_ITEM(S5P_CLKSRC_PERIL0),
  47         SAVE_ITEM(S5P_CLKSRC_PERIL1),
  48         SAVE_ITEM(S5P_CLKDIV_CAM),
  49         SAVE_ITEM(S5P_CLKDIV_TV),
  50         SAVE_ITEM(S5P_CLKDIV_MFC),
  51         SAVE_ITEM(S5P_CLKDIV_G3D),
  52         SAVE_ITEM(S5P_CLKDIV_LCD0),
  53         SAVE_ITEM(S5P_CLKDIV_MAUDIO),
  54         SAVE_ITEM(S5P_CLKDIV_FSYS0),
  55         SAVE_ITEM(S5P_CLKDIV_FSYS1),
  56         SAVE_ITEM(S5P_CLKDIV_FSYS2),
  57         SAVE_ITEM(S5P_CLKDIV_FSYS3),
  58         SAVE_ITEM(S5P_CLKDIV_PERIL0),
  59         SAVE_ITEM(S5P_CLKDIV_PERIL1),
  60         SAVE_ITEM(S5P_CLKDIV_PERIL2),
  61         SAVE_ITEM(S5P_CLKDIV_PERIL3),
  62         SAVE_ITEM(S5P_CLKDIV_PERIL4),
  63         SAVE_ITEM(S5P_CLKDIV_PERIL5),
  64         SAVE_ITEM(S5P_CLKDIV_TOP),
  65         SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
  66         SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
  67         SAVE_ITEM(S5P_CLKSRC_MASK_TV),
  68         SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
  69         SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
  70         SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
  71         SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
  72         SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
  73         SAVE_ITEM(S5P_CLKDIV2_RATIO),
  74         SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
  75         SAVE_ITEM(S5P_CLKGATE_IP_CAM),
  76         SAVE_ITEM(S5P_CLKGATE_IP_TV),
  77         SAVE_ITEM(S5P_CLKGATE_IP_MFC),
  78         SAVE_ITEM(S5P_CLKGATE_IP_G3D),
  79         SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
  80         SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
  81         SAVE_ITEM(S5P_CLKGATE_IP_GPS),
  82         SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
  83         SAVE_ITEM(S5P_CLKGATE_BLOCK),
  84         SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
  85         SAVE_ITEM(S5P_CLKSRC_DMC),
  86         SAVE_ITEM(S5P_CLKDIV_DMC0),
  87         SAVE_ITEM(S5P_CLKDIV_DMC1),
  88         SAVE_ITEM(S5P_CLKGATE_IP_DMC),
  89         SAVE_ITEM(S5P_CLKSRC_CPU),
  90         SAVE_ITEM(S5P_CLKDIV_CPU),
  91         SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
  92         SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
  93         SAVE_ITEM(S5P_CLKGATE_IP_CPU),
  94 };
  95
  96 struct clk clk_sclk_hdmi27m = {
  97         .name           = "sclk_hdmi27m",
  98         .rate           = 27000000,
  99 };
 100
 101 struct clk clk_sclk_hdmiphy = {
 102         .name           = "sclk_hdmiphy",
 103 };
 104
 105 struct clk clk_sclk_usbphy0 = {
 106         .name           = "sclk_usbphy0",
 107         .rate           = 27000000,
 108 };
 109
 110 struct clk clk_sclk_usbphy1 = {
 111         .name           = "sclk_usbphy1",
 112 };
 113
 114 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 115 {
 116         return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
 117 }
 118
 119 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
 120 {
 121         return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
 122 }
 123
 124 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
 125 {
 126         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
 127 }
 128
 129 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 130 {
 131         return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
 132 }
 133
 134 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
 135 {
 136         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
 137 }
 138
 139 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
 140 {
 141         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
 142 }
 143
 144 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 145 {
 146         return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
 147 }
 148
 149 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
 150 {
 151         return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
 152 }
 153
 154 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
 155 {
 156         return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
 157 }
 158
 159 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
 160 {
 161         return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
 162 }
 163
 164 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
 165 {
 166         return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
 167 }
 168
 169 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 170 {
 171         return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
 172 }
 173
 174 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 175 {
 176         return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
 177 }
 178
 179 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
 180 {
 181         return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
 182 }
 183
 184 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
 185 {
 186         return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
 187 }
 188
 189 /* Core list of CMU_CPU side */
 190
 191 static struct clksrc_clk clk_mout_apll = {
 192         .clk    = {
 193                 .name           = "mout_apll",
 194         },
 195         .sources        = &clk_src_apll,
 196         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
 197 };
 198
 199 struct clksrc_clk clk_sclk_apll = {
 200         .clk    = {
 201                 .name           = "sclk_apll",
 202                 .parent         = &clk_mout_apll.clk,
 203         },
 204         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
 205 };
 206
 207 struct clksrc_clk clk_mout_epll = {
 208         .clk    = {
 209                 .name           = "mout_epll",
 210         },
 211         .sources        = &clk_src_epll,
 212         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
 213 };
 214
 215 struct clksrc_clk clk_mout_mpll = {
 216         .clk = {
 217                 .name           = "mout_mpll",
 218         },
 219         .sources        = &clk_src_mpll,
 220
 221         /* reg_src will be added in each SoCs' clock */
 222 };
 223
 224 static struct clk *clkset_moutcore_list[] = {
 225         [0] = &clk_mout_apll.clk,
 226         [1] = &clk_mout_mpll.clk,
 227 };
 228
 229 static struct clksrc_sources clkset_moutcore = {
 230         .sources        = clkset_moutcore_list,
 231         .nr_sources     = ARRAY_SIZE(clkset_moutcore_list),
 232 };
 233
 234 static struct clksrc_clk clk_moutcore = {
 235         .clk    = {
 236                 .name           = "moutcore",
 237         },
 238         .sources        = &clkset_moutcore,
 239         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
 240 };
 241
 242 static struct clksrc_clk clk_coreclk = {
 243         .clk    = {
 244                 .name           = "core_clk",
 245                 .parent         = &clk_moutcore.clk,
 246         },
 247         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
 248 };
 249
 250 static struct clksrc_clk clk_armclk = {
 251         .clk    = {
 252                 .name           = "armclk",
 253                 .parent         = &clk_coreclk.clk,
 254         },
 255 };
 256
 257 static struct clksrc_clk clk_aclk_corem0 = {
 258         .clk    = {
 259                 .name           = "aclk_corem0",
 260                 .parent         = &clk_coreclk.clk,
 261         },
 262         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 263 };
 264
 265 static struct clksrc_clk clk_aclk_cores = {
 266         .clk    = {
 267                 .name           = "aclk_cores",
 268                 .parent         = &clk_coreclk.clk,
 269         },
 270         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 271 };
 272
 273 static struct clksrc_clk clk_aclk_corem1 = {
 274         .clk    = {
 275                 .name           = "aclk_corem1",
 276                 .parent         = &clk_coreclk.clk,
 277         },
 278         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
 279 };
 280
 281 static struct clksrc_clk clk_periphclk = {
 282         .clk    = {
 283                 .name           = "periphclk",
 284                 .parent         = &clk_coreclk.clk,
 285         },
 286         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
 287 };
 288
 289 /* Core list of CMU_CORE side */
 290
 291 struct clk *clkset_corebus_list[] = {
 292         [0] = &clk_mout_mpll.clk,
 293         [1] = &clk_sclk_apll.clk,
 294 };
 295
 296 struct clksrc_sources clkset_mout_corebus = {
 297         .sources        = clkset_corebus_list,
 298         .nr_sources     = ARRAY_SIZE(clkset_corebus_list),
 299 };
 300
 301 static struct clksrc_clk clk_mout_corebus = {
 302         .clk    = {
 303                 .name           = "mout_corebus",
 304         },
 305         .sources        = &clkset_mout_corebus,
 306         .reg_src        = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
 307 };
 308
 309 static struct clksrc_clk clk_sclk_dmc = {
 310         .clk    = {
 311                 .name           = "sclk_dmc",
 312                 .parent         = &clk_mout_corebus.clk,
 313         },
 314         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
 315 };
 316
 317 static struct clksrc_clk clk_aclk_cored = {
 318         .clk    = {
 319                 .name           = "aclk_cored",
 320                 .parent         = &clk_sclk_dmc.clk,
 321         },
 322         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
 323 };
 324
 325 static struct clksrc_clk clk_aclk_corep = {
 326         .clk    = {
 327                 .name           = "aclk_corep",
 328                 .parent         = &clk_aclk_cored.clk,
 329         },
 330         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
 331 };
 332
 333 static struct clksrc_clk clk_aclk_acp = {
 334         .clk    = {
 335                 .name           = "aclk_acp",
 336                 .parent         = &clk_mout_corebus.clk,
 337         },
 338         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
 339 };
 340
 341 static struct clksrc_clk clk_pclk_acp = {
 342         .clk    = {
 343                 .name           = "pclk_acp",
 344                 .parent         = &clk_aclk_acp.clk,
 345         },
 346         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
 347 };
 348
 349 /* Core list of CMU_TOP side */
 350
 351 struct clk *clkset_aclk_top_list[] = {
 352         [0] = &clk_mout_mpll.clk,
 353         [1] = &clk_sclk_apll.clk,
 354 };
 355
 356 struct clksrc_sources clkset_aclk = {
 357         .sources        = clkset_aclk_top_list,
 358         .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
 359 };
 360
 361 static struct clksrc_clk clk_aclk_200 = {
 362         .clk    = {
 363                 .name           = "aclk_200",
 364         },
 365         .sources        = &clkset_aclk,
 366         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
 367         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
 368 };
 369
 370 static struct clksrc_clk clk_aclk_100 = {
 371         .clk    = {
 372                 .name           = "aclk_100",
 373         },
 374         .sources        = &clkset_aclk,
 375         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
 376         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
 377 };
 378
 379 static struct clksrc_clk clk_aclk_160 = {
 380         .clk    = {
 381                 .name           = "aclk_160",
 382         },
 383         .sources        = &clkset_aclk,
 384         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
 385         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
 386 };
 387
 388 struct clksrc_clk clk_aclk_133 = {
 389         .clk    = {
 390                 .name           = "aclk_133",
 391         },
 392         .sources        = &clkset_aclk,
 393         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
 394         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
 395 };
 396
 397 static struct clk *clkset_vpllsrc_list[] = {
 398         [0] = &clk_fin_vpll,
 399         [1] = &clk_sclk_hdmi27m,
 400 };
 401
 402 static struct clksrc_sources clkset_vpllsrc = {
 403         .sources        = clkset_vpllsrc_list,
 404         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
 405 };
 406
 407 static struct clksrc_clk clk_vpllsrc = {
 408         .clk    = {
 409                 .name           = "vpll_src",
 410                 .enable         = exynos4_clksrc_mask_top_ctrl,
 411                 .ctrlbit        = (1 << 0),
 412         },
 413         .sources        = &clkset_vpllsrc,
 414         .reg_src        = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
 415 };
 416
 417 static struct clk *clkset_sclk_vpll_list[] = {
 418         [0] = &clk_vpllsrc.clk,
 419         [1] = &clk_fout_vpll,
 420 };
 421
 422 static struct clksrc_sources clkset_sclk_vpll = {
 423         .sources        = clkset_sclk_vpll_list,
 424         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 425 };
 426
 427 struct clksrc_clk clk_sclk_vpll = {
 428         .clk    = {
 429                 .name           = "sclk_vpll",
 430         },
 431         .sources        = &clkset_sclk_vpll,
 432         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
 433 };
 434
 435 static struct clk init_clocks_off[] = {
 436         {
 437                 .name           = "timers",
 438                 .parent         = &clk_aclk_100.clk,
 439                 .enable         = exynos4_clk_ip_peril_ctrl,
 440                 .ctrlbit        = (1<<24),
 441         }, {
 442                 .name           = "csis",
 443                 .devname        = "s5p-mipi-csis.0",
 444                 .enable         = exynos4_clk_ip_cam_ctrl,
 445                 .ctrlbit        = (1 << 4),
 446         }, {
 447                 .name           = "csis",
 448                 .devname        = "s5p-mipi-csis.1",
 449                 .enable         = exynos4_clk_ip_cam_ctrl,
 450                 .ctrlbit        = (1 << 5),
 451         }, {
 452                 .name           = "fimc",
 453                 .devname        = "exynos4-fimc.0",
 454                 .enable         = exynos4_clk_ip_cam_ctrl,
 455                 .ctrlbit        = (1 << 0),
 456         }, {
 457                 .name           = "fimc",
 458                 .devname        = "exynos4-fimc.1",
 459                 .enable         = exynos4_clk_ip_cam_ctrl,
 460                 .ctrlbit        = (1 << 1),
 461         }, {
 462                 .name           = "fimc",
 463                 .devname        = "exynos4-fimc.2",
 464                 .enable         = exynos4_clk_ip_cam_ctrl,
 465                 .ctrlbit        = (1 << 2),
 466         }, {
 467                 .name           = "fimc",
 468                 .devname        = "exynos4-fimc.3",
 469                 .enable         = exynos4_clk_ip_cam_ctrl,
 470                 .ctrlbit        = (1 << 3),
 471         }, {
 472                 .name           = "fimd",
 473                 .devname        = "exynos4-fb.0",
 474                 .enable         = exynos4_clk_ip_lcd0_ctrl,
 475                 .ctrlbit        = (1 << 0),
 476         }, {
 477                 .name           = "hsmmc",
 478                 .devname        = "s3c-sdhci.0",
 479                 .parent         = &clk_aclk_133.clk,
 480                 .enable         = exynos4_clk_ip_fsys_ctrl,
 481                 .ctrlbit        = (1 << 5),
 482         }, {
 483                 .name           = "hsmmc",
 484                 .devname        = "s3c-sdhci.1",
 485                 .parent         = &clk_aclk_133.clk,
 486                 .enable         = exynos4_clk_ip_fsys_ctrl,
 487                 .ctrlbit        = (1 << 6),
 488         }, {
 489                 .name           = "hsmmc",
 490                 .devname        = "s3c-sdhci.2",
 491                 .parent         = &clk_aclk_133.clk,
 492                 .enable         = exynos4_clk_ip_fsys_ctrl,
 493                 .ctrlbit        = (1 << 7),
 494         }, {
 495                 .name           = "hsmmc",
 496                 .devname        = "s3c-sdhci.3",
 497                 .parent         = &clk_aclk_133.clk,
 498                 .enable         = exynos4_clk_ip_fsys_ctrl,
 499                 .ctrlbit        = (1 << 8),
 500         }, {
 501                 .name           = "dwmmc",
 502                 .parent         = &clk_aclk_133.clk,
 503                 .enable         = exynos4_clk_ip_fsys_ctrl,
 504                 .ctrlbit        = (1 << 9),
 505         }, {
 506                 .name           = "pdma",
 507                 .devname        = "s3c-pl330.0",
 508                 .enable         = exynos4_clk_ip_fsys_ctrl,
 509                 .ctrlbit        = (1 << 0),
 510         }, {
 511                 .name           = "pdma",
 512                 .devname        = "s3c-pl330.1",
 513                 .enable         = exynos4_clk_ip_fsys_ctrl,
 514                 .ctrlbit        = (1 << 1),
 515         }, {
 516                 .name           = "adc",
 517                 .enable         = exynos4_clk_ip_peril_ctrl,
 518                 .ctrlbit        = (1 << 15),
 519         }, {
 520                 .name           = "keypad",
 521                 .enable         = exynos4_clk_ip_perir_ctrl,
 522                 .ctrlbit        = (1 << 16),
 523         }, {
 524                 .name           = "rtc",
 525                 .enable         = exynos4_clk_ip_perir_ctrl,
 526                 .ctrlbit        = (1 << 15),
 527         }, {
 528                 .name           = "watchdog",
 529                 .parent         = &clk_aclk_100.clk,
 530                 .enable         = exynos4_clk_ip_perir_ctrl,
 531                 .ctrlbit        = (1 << 14),
 532         }, {
 533                 .name           = "usbhost",
 534                 .enable         = exynos4_clk_ip_fsys_ctrl ,
 535                 .ctrlbit        = (1 << 12),
 536         }, {
 537                 .name           = "otg",
 538                 .enable         = exynos4_clk_ip_fsys_ctrl,
 539                 .ctrlbit        = (1 << 13),
 540         }, {
 541                 .name           = "spi",
 542                 .devname        = "s3c64xx-spi.0",
 543                 .enable         = exynos4_clk_ip_peril_ctrl,
 544                 .ctrlbit        = (1 << 16),
 545         }, {
 546                 .name           = "spi",
 547                 .devname        = "s3c64xx-spi.1",
 548                 .enable         = exynos4_clk_ip_peril_ctrl,
 549                 .ctrlbit        = (1 << 17),
 550         }, {
 551                 .name           = "spi",
 552                 .devname        = "s3c64xx-spi.2",
 553                 .enable         = exynos4_clk_ip_peril_ctrl,
 554                 .ctrlbit        = (1 << 18),
 555         }, {
 556                 .name           = "iis",
 557                 .devname        = "samsung-i2s.0",
 558                 .enable         = exynos4_clk_ip_peril_ctrl,
 559                 .ctrlbit        = (1 << 19),
 560         }, {
 561                 .name           = "iis",
 562                 .devname        = "samsung-i2s.1",
 563                 .enable         = exynos4_clk_ip_peril_ctrl,
 564                 .ctrlbit        = (1 << 20),
 565         }, {
 566                 .name           = "iis",
 567                 .devname        = "samsung-i2s.2",
 568                 .enable         = exynos4_clk_ip_peril_ctrl,
 569                 .ctrlbit        = (1 << 21),
 570         }, {
 571                 .name           = "ac97",
 572                 .devname        = "samsung-ac97",
 573                 .enable         = exynos4_clk_ip_peril_ctrl,
 574                 .ctrlbit        = (1 << 27),
 575         }, {
 576                 .name           = "fimg2d",
 577                 .enable         = exynos4_clk_ip_image_ctrl,
 578                 .ctrlbit        = (1 << 0),
 579         }, {
 580                 .name           = "mfc",
 581                 .devname        = "s5p-mfc",
 582                 .enable         = exynos4_clk_ip_mfc_ctrl,
 583                 .ctrlbit        = (1 << 0),
 584         }, {
 585                 .name           = "i2c",
 586                 .devname        = "s3c2440-i2c.0",
 587                 .parent         = &clk_aclk_100.clk,
 588                 .enable         = exynos4_clk_ip_peril_ctrl,
 589                 .ctrlbit        = (1 << 6),
 590         }, {
 591                 .name           = "i2c",
 592                 .devname        = "s3c2440-i2c.1",
 593                 .parent         = &clk_aclk_100.clk,
 594                 .enable         = exynos4_clk_ip_peril_ctrl,
 595                 .ctrlbit        = (1 << 7),
 596         }, {
 597                 .name           = "i2c",
 598                 .devname        = "s3c2440-i2c.2",
 599                 .parent         = &clk_aclk_100.clk,
 600                 .enable         = exynos4_clk_ip_peril_ctrl,
 601                 .ctrlbit        = (1 << 8),
 602         }, {
 603                 .name           = "i2c",
 604                 .devname        = "s3c2440-i2c.3",
 605                 .parent         = &clk_aclk_100.clk,
 606                 .enable         = exynos4_clk_ip_peril_ctrl,
 607                 .ctrlbit        = (1 << 9),
 608         }, {
 609                 .name           = "i2c",
 610                 .devname        = "s3c2440-i2c.4",
 611                 .parent         = &clk_aclk_100.clk,
 612                 .enable         = exynos4_clk_ip_peril_ctrl,
 613                 .ctrlbit        = (1 << 10),
 614         }, {
 615                 .name           = "i2c",
 616                 .devname        = "s3c2440-i2c.5",
 617                 .parent         = &clk_aclk_100.clk,
 618                 .enable         = exynos4_clk_ip_peril_ctrl,
 619                 .ctrlbit        = (1 << 11),
 620         }, {
 621                 .name           = "i2c",
 622                 .devname        = "s3c2440-i2c.6",
 623                 .parent         = &clk_aclk_100.clk,
 624                 .enable         = exynos4_clk_ip_peril_ctrl,
 625                 .ctrlbit        = (1 << 12),
 626         }, {
 627                 .name           = "i2c",
 628                 .devname        = "s3c2440-i2c.7",
 629                 .parent         = &clk_aclk_100.clk,
 630                 .enable         = exynos4_clk_ip_peril_ctrl,
 631                 .ctrlbit        = (1 << 13),
 632         }, {
 633                 .name           = "SYSMMU_MDMA",
 634                 .enable         = exynos4_clk_ip_image_ctrl,
 635                 .ctrlbit        = (1 << 5),
 636         }, {
 637                 .name           = "SYSMMU_FIMC0",
 638                 .enable         = exynos4_clk_ip_cam_ctrl,
 639                 .ctrlbit        = (1 << 7),
 640         }, {
 641                 .name           = "SYSMMU_FIMC1",
 642                 .enable         = exynos4_clk_ip_cam_ctrl,
 643                 .ctrlbit        = (1 << 8),
 644         }, {
 645                 .name           = "SYSMMU_FIMC2",
 646                 .enable         = exynos4_clk_ip_cam_ctrl,
 647                 .ctrlbit        = (1 << 9),
 648         }, {
 649                 .name           = "SYSMMU_FIMC3",
 650                 .enable         = exynos4_clk_ip_cam_ctrl,
 651                 .ctrlbit        = (1 << 10),
 652         }, {
 653                 .name           = "SYSMMU_JPEG",
 654                 .enable         = exynos4_clk_ip_cam_ctrl,
 655                 .ctrlbit        = (1 << 11),
 656         }, {
 657                 .name           = "SYSMMU_FIMD0",
 658                 .enable         = exynos4_clk_ip_lcd0_ctrl,
 659                 .ctrlbit        = (1 << 4),
 660         }, {
 661                 .name           = "SYSMMU_FIMD1",
 662                 .enable         = exynos4_clk_ip_lcd1_ctrl,
 663                 .ctrlbit        = (1 << 4),
 664         }, {
 665                 .name           = "SYSMMU_PCIe",
 666                 .enable         = exynos4_clk_ip_fsys_ctrl,
 667                 .ctrlbit        = (1 << 18),
 668         }, {
 669                 .name           = "SYSMMU_G2D",
 670                 .enable         = exynos4_clk_ip_image_ctrl,
 671                 .ctrlbit        = (1 << 3),
 672         }, {
 673                 .name           = "SYSMMU_ROTATOR",
 674                 .enable         = exynos4_clk_ip_image_ctrl,
 675                 .ctrlbit        = (1 << 4),
 676         }, {
 677                 .name           = "SYSMMU_TV",
 678                 .enable         = exynos4_clk_ip_tv_ctrl,
 679                 .ctrlbit        = (1 << 4),
 680         }, {
 681                 .name           = "SYSMMU_MFC_L",
 682                 .enable         = exynos4_clk_ip_mfc_ctrl,
 683                 .ctrlbit        = (1 << 1),
 684         }, {
 685                 .name           = "SYSMMU_MFC_R",
 686                 .enable         = exynos4_clk_ip_mfc_ctrl,
 687                 .ctrlbit        = (1 << 2),
 688         }
 689 };
 690
 691 static struct clk init_clocks[] = {
 692         {
 693                 .name           = "uart",
 694                 .devname        = "s5pv210-uart.0",
 695                 .enable         = exynos4_clk_ip_peril_ctrl,
 696                 .ctrlbit        = (1 << 0),
 697         }, {
 698                 .name           = "uart",
 699                 .devname        = "s5pv210-uart.1",
 700                 .enable         = exynos4_clk_ip_peril_ctrl,
 701                 .ctrlbit        = (1 << 1),
 702         }, {
 703                 .name           = "uart",
 704                 .devname        = "s5pv210-uart.2",
 705                 .enable         = exynos4_clk_ip_peril_ctrl,
 706                 .ctrlbit        = (1 << 2),
 707         }, {
 708                 .name           = "uart",
 709                 .devname        = "s5pv210-uart.3",
 710                 .enable         = exynos4_clk_ip_peril_ctrl,
 711                 .ctrlbit        = (1 << 3),
 712         }, {
 713                 .name           = "uart",
 714                 .devname        = "s5pv210-uart.4",
 715                 .enable         = exynos4_clk_ip_peril_ctrl,
 716                 .ctrlbit        = (1 << 4),
 717         }, {
 718                 .name           = "uart",
 719                 .devname        = "s5pv210-uart.5",
 720                 .enable         = exynos4_clk_ip_peril_ctrl,
 721                 .ctrlbit        = (1 << 5),
 722         }
 723 };
 724
 725 struct clk *clkset_group_list[] = {
 726         [0] = &clk_ext_xtal_mux,
 727         [1] = &clk_xusbxti,
 728         [2] = &clk_sclk_hdmi27m,
 729         [3] = &clk_sclk_usbphy0,
 730         [4] = &clk_sclk_usbphy1,
 731         [5] = &clk_sclk_hdmiphy,
 732         [6] = &clk_mout_mpll.clk,
 733         [7] = &clk_mout_epll.clk,
 734         [8] = &clk_sclk_vpll.clk,
 735 };
 736
 737 struct clksrc_sources clkset_group = {
 738         .sources        = clkset_group_list,
 739         .nr_sources     = ARRAY_SIZE(clkset_group_list),
 740 };
 741
 742 static struct clk *clkset_mout_g2d0_list[] = {
 743         [0] = &clk_mout_mpll.clk,
 744         [1] = &clk_sclk_apll.clk,
 745 };
 746
 747 static struct clksrc_sources clkset_mout_g2d0 = {
 748         .sources        = clkset_mout_g2d0_list,
 749         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d0_list),
 750 };
 751
 752 static struct clksrc_clk clk_mout_g2d0 = {
 753         .clk    = {
 754                 .name           = "mout_g2d0",
 755         },
 756         .sources        = &clkset_mout_g2d0,
 757         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
 758 };
 759
 760 static struct clk *clkset_mout_g2d1_list[] = {
 761         [0] = &clk_mout_epll.clk,
 762         [1] = &clk_sclk_vpll.clk,
 763 };
 764
 765 static struct clksrc_sources clkset_mout_g2d1 = {
 766         .sources        = clkset_mout_g2d1_list,
 767         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d1_list),
 768 };
 769
 770 static struct clksrc_clk clk_mout_g2d1 = {
 771         .clk    = {
 772                 .name           = "mout_g2d1",
 773         },
 774         .sources        = &clkset_mout_g2d1,
 775         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
 776 };
 777
 778 static struct clk *clkset_mout_g2d_list[] = {
 779         [0] = &clk_mout_g2d0.clk,
 780         [1] = &clk_mout_g2d1.clk,
 781 };
 782
 783 static struct clksrc_sources clkset_mout_g2d = {
 784         .sources        = clkset_mout_g2d_list,
 785         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d_list),
 786 };
 787
 788 static struct clk *clkset_mout_mfc0_list[] = {
 789         [0] = &clk_mout_mpll.clk,
 790         [1] = &clk_sclk_apll.clk,
 791 };
 792
 793 static struct clksrc_sources clkset_mout_mfc0 = {
 794         .sources        = clkset_mout_mfc0_list,
 795         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc0_list),
 796 };
 797
 798 static struct clksrc_clk clk_mout_mfc0 = {
 799         .clk    = {
 800                 .name           = "mout_mfc0",
 801         },
 802         .sources        = &clkset_mout_mfc0,
 803         .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
 804 };
 805
 806 static struct clk *clkset_mout_mfc1_list[] = {
 807         [0] = &clk_mout_epll.clk,
 808         [1] = &clk_sclk_vpll.clk,
 809 };
 810
 811 static struct clksrc_sources clkset_mout_mfc1 = {
 812         .sources        = clkset_mout_mfc1_list,
 813         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc1_list),
 814 };
 815
 816 static struct clksrc_clk clk_mout_mfc1 = {
 817         .clk    = {
 818                 .name           = "mout_mfc1",
 819         },
 820         .sources        = &clkset_mout_mfc1,
 821         .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
 822 };
 823
 824 static struct clk *clkset_mout_mfc_list[] = {
 825         [0] = &clk_mout_mfc0.clk,
 826         [1] = &clk_mout_mfc1.clk,
 827 };
 828
 829 static struct clksrc_sources clkset_mout_mfc = {
 830         .sources        = clkset_mout_mfc_list,
 831         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc_list),
 832 };
 833
 834 static struct clksrc_clk clk_dout_mmc0 = {
 835         .clk            = {
 836                 .name           = "dout_mmc0",
 837         },
 838         .sources = &clkset_group,
 839         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
 840         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
 841 };
 842
 843 static struct clksrc_clk clk_dout_mmc1 = {
 844         .clk            = {
 845                 .name           = "dout_mmc1",
 846         },
 847         .sources = &clkset_group,
 848         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
 849         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
 850 };
 851
 852 static struct clksrc_clk clk_dout_mmc2 = {
 853         .clk            = {
 854                 .name           = "dout_mmc2",
 855         },
 856         .sources = &clkset_group,
 857         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
 858         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
 859 };
 860
 861 static struct clksrc_clk clk_dout_mmc3 = {
 862         .clk            = {
 863                 .name           = "dout_mmc3",
 864         },
 865         .sources = &clkset_group,
 866         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
 867         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
 868 };
 869
 870 static struct clksrc_clk clk_dout_mmc4 = {
 871         .clk            = {
 872                 .name           = "dout_mmc4",
 873         },
 874         .sources = &clkset_group,
 875         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
 876         .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
 877 };
 878
 879 static struct clksrc_clk clksrcs[] = {
 880         {
 881                 .clk    = {
 882                         .name           = "uclk1",
 883                         .devname        = "s5pv210-uart.0",
 884                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 885                         .ctrlbit        = (1 << 0),
 886                 },
 887                 .sources = &clkset_group,
 888                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
 889                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
 890         }, {
 891                 .clk            = {
 892                         .name           = "uclk1",
 893                         .devname        = "s5pv210-uart.1",
 894                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 895                         .ctrlbit        = (1 << 4),
 896                 },
 897                 .sources = &clkset_group,
 898                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
 899                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
 900         }, {
 901                 .clk            = {
 902                         .name           = "uclk1",
 903                         .devname        = "s5pv210-uart.2",
 904                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 905                         .ctrlbit        = (1 << 8),
 906                 },
 907                 .sources = &clkset_group,
 908                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
 909                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
 910         }, {
 911                 .clk            = {
 912                         .name           = "uclk1",
 913                         .devname        = "s5pv210-uart.3",
 914                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 915                         .ctrlbit        = (1 << 12),
 916                 },
 917                 .sources = &clkset_group,
 918                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
 919                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
 920         }, {
 921                 .clk            = {
 922                         .name           = "sclk_pwm",
 923                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 924                         .ctrlbit        = (1 << 24),
 925                 },
 926                 .sources = &clkset_group,
 927                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
 928                 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
 929         }, {
 930                 .clk            = {
 931                         .name           = "sclk_csis",
 932                         .devname        = "s5p-mipi-csis.0",
 933                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 934                         .ctrlbit        = (1 << 24),
 935                 },
 936                 .sources = &clkset_group,
 937                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
 938                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
 939         }, {
 940                 .clk            = {
 941                         .name           = "sclk_csis",
 942                         .devname        = "s5p-mipi-csis.1",
 943                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 944                         .ctrlbit        = (1 << 28),
 945                 },
 946                 .sources = &clkset_group,
 947                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
 948                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
 949         }, {
 950                 .clk            = {
 951                         .name           = "sclk_cam0",
 952                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 953                         .ctrlbit        = (1 << 16),
 954                 },
 955                 .sources = &clkset_group,
 956                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
 957                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
 958         }, {
 959                 .clk            = {
 960                         .name           = "sclk_cam1",
 961                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 962                         .ctrlbit        = (1 << 20),
 963                 },
 964                 .sources = &clkset_group,
 965                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
 966                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
 967         }, {
 968                 .clk            = {
 969                         .name           = "sclk_fimc",
 970                         .devname        = "exynos4-fimc.0",
 971                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 972                         .ctrlbit        = (1 << 0),
 973                 },
 974                 .sources = &clkset_group,
 975                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
 976                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
 977         }, {
 978                 .clk            = {
 979                         .name           = "sclk_fimc",
 980                         .devname        = "exynos4-fimc.1",
 981                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 982                         .ctrlbit        = (1 << 4),
 983                 },
 984                 .sources = &clkset_group,
 985                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
 986                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
 987         }, {
 988                 .clk            = {
 989                         .name           = "sclk_fimc",
 990                         .devname        = "exynos4-fimc.2",
 991                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 992                         .ctrlbit        = (1 << 8),
 993                 },
 994                 .sources = &clkset_group,
 995                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
 996                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
 997         }, {
 998                 .clk            = {
 999                         .name           = "sclk_fimc",
1000                         .devname        = "exynos4-fimc.3",
1001                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1002                         .ctrlbit        = (1 << 12),
1003                 },
1004                 .sources = &clkset_group,
1005                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
1006                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
1007         }, {
1008                 .clk            = {
1009                         .name           = "sclk_fimd",
1010                         .devname        = "exynos4-fb.0",
1011                         .enable         = exynos4_clksrc_mask_lcd0_ctrl,
1012                         .ctrlbit        = (1 << 0),
1013                 },
1014                 .sources = &clkset_group,
1015                 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
1016                 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
1017         }, {
1018                 .clk            = {
1019                         .name           = "sclk_spi",
1020                         .devname        = "s3c64xx-spi.0",
1021                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
1022                         .ctrlbit        = (1 << 16),
1023                 },
1024                 .sources = &clkset_group,
1025                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1026                 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1027         }, {
1028                 .clk            = {
1029                         .name           = "sclk_spi",
1030                         .devname        = "s3c64xx-spi.1",
1031                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
1032                         .ctrlbit        = (1 << 20),
1033                 },
1034                 .sources = &clkset_group,
1035                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1036                 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1037         }, {
1038                 .clk            = {
1039                         .name           = "sclk_spi",
1040                         .devname        = "s3c64xx-spi.2",
1041                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
1042                         .ctrlbit        = (1 << 24),
1043                 },
1044                 .sources = &clkset_group,
1045                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1046                 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1047         }, {
1048                 .clk            = {
1049                         .name           = "sclk_fimg2d",
1050                 },
1051                 .sources = &clkset_mout_g2d,
1052                 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1053                 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1054         }, {
1055                 .clk            = {
1056                         .name           = "sclk_mfc",
1057                         .devname        = "s5p-mfc",
1058                 },
1059                 .sources = &clkset_mout_mfc,
1060                 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1061                 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1062         }, {
1063                 .clk            = {
1064                         .name           = "sclk_mmc",
1065                         .devname        = "s3c-sdhci.0",
1066                         .parent         = &clk_dout_mmc0.clk,
1067                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1068                         .ctrlbit        = (1 << 0),
1069                 },
1070                 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1071         }, {
1072                 .clk            = {
1073                         .name           = "sclk_mmc",
1074                         .devname        = "s3c-sdhci.1",
1075                         .parent         = &clk_dout_mmc1.clk,
1076                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1077                         .ctrlbit        = (1 << 4),
1078                 },
1079                 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1080         }, {
1081                 .clk            = {
1082                         .name           = "sclk_mmc",
1083                         .devname        = "s3c-sdhci.2",
1084                         .parent         = &clk_dout_mmc2.clk,
1085                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1086                         .ctrlbit        = (1 << 8),
1087                 },
1088                 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1089         }, {
1090                 .clk            = {
1091                         .name           = "sclk_mmc",
1092                         .devname        = "s3c-sdhci.3",
1093                         .parent         = &clk_dout_mmc3.clk,
1094                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1095                         .ctrlbit        = (1 << 12),
1096                 },
1097                 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1098         }, {
1099                 .clk            = {
1100                         .name           = "sclk_dwmmc",
1101                         .parent         = &clk_dout_mmc4.clk,
1102                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1103                         .ctrlbit        = (1 << 16),
1104                 },
1105                 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1106         }
1107 };
1108
1109 /* Clock initialization code */
1110 static struct clksrc_clk *sysclks[] = {
1111         &clk_mout_apll,
1112         &clk_sclk_apll,
1113         &clk_mout_epll,
1114         &clk_mout_mpll,
1115         &clk_moutcore,
1116         &clk_coreclk,
1117         &clk_armclk,
1118         &clk_aclk_corem0,
1119         &clk_aclk_cores,
1120         &clk_aclk_corem1,
1121         &clk_periphclk,
1122         &clk_mout_corebus,
1123         &clk_sclk_dmc,
1124         &clk_aclk_cored,
1125         &clk_aclk_corep,
1126         &clk_aclk_acp,
1127         &clk_pclk_acp,
1128         &clk_vpllsrc,
1129         &clk_sclk_vpll,
1130         &clk_aclk_200,
1131         &clk_aclk_100,
1132         &clk_aclk_160,
1133         &clk_aclk_133,
1134         &clk_dout_mmc0,
1135         &clk_dout_mmc1,
1136         &clk_dout_mmc2,
1137         &clk_dout_mmc3,
1138         &clk_dout_mmc4,
1139         &clk_mout_mfc0,
1140         &clk_mout_mfc1,
1141 };
1142
1143 static int xtal_rate;
1144
1145 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1146 {
1147         if (soc_is_exynos4210())
1148                 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
1149                                         pll_4508);
1150         else if (soc_is_exynos4212() || soc_is_exynos4412())
1151                 return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
1152         else
1153                 return 0;
1154 }
1155
1156 static struct clk_ops exynos4_fout_apll_ops = {
1157         .get_rate = exynos4_fout_apll_get_rate,
1158 };
1159
1160 void __init_or_cpufreq exynos4_setup_clocks(void)
1161 {
1162         struct clk *xtal_clk;
1163         unsigned long apll = 0;
1164         unsigned long mpll = 0;
1165         unsigned long epll = 0;
1166         unsigned long vpll = 0;
1167         unsigned long vpllsrc;
1168         unsigned long xtal;
1169         unsigned long armclk;
1170         unsigned long sclk_dmc;
1171         unsigned long aclk_200;
1172         unsigned long aclk_100;
1173         unsigned long aclk_160;
1174         unsigned long aclk_133;
1175         unsigned int ptr;
1176
1177         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1178
1179         xtal_clk = clk_get(NULL, "xtal");
1180         BUG_ON(IS_ERR(xtal_clk));
1181
1182         xtal = clk_get_rate(xtal_clk);
1183
1184         xtal_rate = xtal;
1185
1186         clk_put(xtal_clk);
1187
1188         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1189
1190         if (soc_is_exynos4210()) {
1191                 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
1192                                         pll_4508);
1193                 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
1194                                         pll_4508);
1195                 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1196                                         __raw_readl(S5P_EPLL_CON1), pll_4600);
1197
1198                 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1199                 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1200                                         __raw_readl(S5P_VPLL_CON1), pll_4650c);
1201         } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1202                 apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
1203                 mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
1204                 epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
1205                                         __raw_readl(S5P_EPLL_CON1));
1206
1207                 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1208                 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1209                                         __raw_readl(S5P_VPLL_CON1));
1210         } else {
1211                 /* nothing */
1212         }
1213
1214         clk_fout_apll.ops = &exynos4_fout_apll_ops;
1215         clk_fout_mpll.rate = mpll;
1216         clk_fout_epll.rate = epll;
1217         clk_fout_vpll.rate = vpll;
1218
1219         printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1220                         apll, mpll, epll, vpll);
1221
1222         armclk = clk_get_rate(&clk_armclk.clk);
1223         sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1224
1225         aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1226         aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1227         aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1228         aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1229
1230         printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1231                          "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1232                         armclk, sclk_dmc, aclk_200,
1233                         aclk_100, aclk_160, aclk_133);
1234
1235         clk_f.rate = armclk;
1236         clk_h.rate = sclk_dmc;
1237         clk_p.rate = aclk_100;
1238
1239         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1240                 s3c_set_clksrc(&clksrcs[ptr], true);
1241 }
1242
1243 static struct clk *clks[] __initdata = {
1244         /* Nothing here yet */
1245 };
1246
1247 #ifdef CONFIG_PM_SLEEP
1248 static int exynos4_clock_suspend(void)
1249 {
1250         s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1251         return 0;
1252 }
1253
1254 static void exynos4_clock_resume(void)
1255 {
1256         s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1257 }
1258
1259 #else
1260 #define exynos4_clock_suspend NULL
1261 #define exynos4_clock_resume NULL
1262 #endif
1263
1264 struct syscore_ops exynos4_clock_syscore_ops = {
1265         .suspend        = exynos4_clock_suspend,
1266         .resume         = exynos4_clock_resume,
1267 };
1268
1269 void __init exynos4_register_clocks(void)
1270 {
1271         int ptr;
1272
1273         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1274
1275         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1276                 s3c_register_clksrc(sysclks[ptr], 1);
1277
1278         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1279         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1280
1281         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1282         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1283
1284         register_syscore_ops(&exynos4_clock_syscore_ops);
1285         s3c_pwmclk_init();
1286 }