1 /* linux/arch/arm/mach-exynos4/clock.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * EXYNOS4 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/err.h>
16 #include <linux/syscore_ops.h>
18 #include <plat/cpu-freq.h>
19 #include <plat/clock.h>
22 #include <plat/s5p-clock.h>
23 #include <plat/clock-clksrc.h>
24 #include <plat/exynos4.h>
28 #include <mach/regs-clock.h>
29 #include <mach/sysmmu.h>
30 #include <mach/exynos4-clock.h>
32 static struct sleep_save exynos4_clock_save[] = {
33 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
34 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
35 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
36 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
37 SAVE_ITEM(S5P_CLKSRC_TOP0),
38 SAVE_ITEM(S5P_CLKSRC_TOP1),
39 SAVE_ITEM(S5P_CLKSRC_CAM),
40 SAVE_ITEM(S5P_CLKSRC_TV),
41 SAVE_ITEM(S5P_CLKSRC_MFC),
42 SAVE_ITEM(S5P_CLKSRC_G3D),
43 SAVE_ITEM(S5P_CLKSRC_LCD0),
44 SAVE_ITEM(S5P_CLKSRC_MAUDIO),
45 SAVE_ITEM(S5P_CLKSRC_FSYS),
46 SAVE_ITEM(S5P_CLKSRC_PERIL0),
47 SAVE_ITEM(S5P_CLKSRC_PERIL1),
48 SAVE_ITEM(S5P_CLKDIV_CAM),
49 SAVE_ITEM(S5P_CLKDIV_TV),
50 SAVE_ITEM(S5P_CLKDIV_MFC),
51 SAVE_ITEM(S5P_CLKDIV_G3D),
52 SAVE_ITEM(S5P_CLKDIV_LCD0),
53 SAVE_ITEM(S5P_CLKDIV_MAUDIO),
54 SAVE_ITEM(S5P_CLKDIV_FSYS0),
55 SAVE_ITEM(S5P_CLKDIV_FSYS1),
56 SAVE_ITEM(S5P_CLKDIV_FSYS2),
57 SAVE_ITEM(S5P_CLKDIV_FSYS3),
58 SAVE_ITEM(S5P_CLKDIV_PERIL0),
59 SAVE_ITEM(S5P_CLKDIV_PERIL1),
60 SAVE_ITEM(S5P_CLKDIV_PERIL2),
61 SAVE_ITEM(S5P_CLKDIV_PERIL3),
62 SAVE_ITEM(S5P_CLKDIV_PERIL4),
63 SAVE_ITEM(S5P_CLKDIV_PERIL5),
64 SAVE_ITEM(S5P_CLKDIV_TOP),
65 SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
66 SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
67 SAVE_ITEM(S5P_CLKSRC_MASK_TV),
68 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
69 SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
70 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
71 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
72 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
73 SAVE_ITEM(S5P_CLKDIV2_RATIO),
74 SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
75 SAVE_ITEM(S5P_CLKGATE_IP_CAM),
76 SAVE_ITEM(S5P_CLKGATE_IP_TV),
77 SAVE_ITEM(S5P_CLKGATE_IP_MFC),
78 SAVE_ITEM(S5P_CLKGATE_IP_G3D),
79 SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
80 SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
81 SAVE_ITEM(S5P_CLKGATE_IP_GPS),
82 SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
83 SAVE_ITEM(S5P_CLKGATE_BLOCK),
84 SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
85 SAVE_ITEM(S5P_CLKSRC_DMC),
86 SAVE_ITEM(S5P_CLKDIV_DMC0),
87 SAVE_ITEM(S5P_CLKDIV_DMC1),
88 SAVE_ITEM(S5P_CLKGATE_IP_DMC),
89 SAVE_ITEM(S5P_CLKSRC_CPU),
90 SAVE_ITEM(S5P_CLKDIV_CPU),
91 SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
92 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
93 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
96 struct clk clk_sclk_hdmi27m = {
97 .name = "sclk_hdmi27m",
101 struct clk clk_sclk_hdmiphy = {
102 .name = "sclk_hdmiphy",
105 struct clk clk_sclk_usbphy0 = {
106 .name = "sclk_usbphy0",
110 struct clk clk_sclk_usbphy1 = {
111 .name = "sclk_usbphy1",
114 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
116 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
119 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
121 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
124 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
126 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
129 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
131 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
134 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
136 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
139 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
141 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
144 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
146 return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
149 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
151 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
154 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
156 return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
159 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
161 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
164 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
166 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
169 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
171 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
174 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
176 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
179 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
181 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
184 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
186 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
189 /* Core list of CMU_CPU side */
191 static struct clksrc_clk clk_mout_apll = {
195 .sources = &clk_src_apll,
196 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
199 struct clksrc_clk clk_sclk_apll = {
202 .parent = &clk_mout_apll.clk,
204 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
207 struct clksrc_clk clk_mout_epll = {
211 .sources = &clk_src_epll,
212 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
215 struct clksrc_clk clk_mout_mpll = {
219 .sources = &clk_src_mpll,
221 /* reg_src will be added in each SoCs' clock */
224 static struct clk *clkset_moutcore_list[] = {
225 [0] = &clk_mout_apll.clk,
226 [1] = &clk_mout_mpll.clk,
229 static struct clksrc_sources clkset_moutcore = {
230 .sources = clkset_moutcore_list,
231 .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
234 static struct clksrc_clk clk_moutcore = {
238 .sources = &clkset_moutcore,
239 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
242 static struct clksrc_clk clk_coreclk = {
245 .parent = &clk_moutcore.clk,
247 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
250 static struct clksrc_clk clk_armclk = {
253 .parent = &clk_coreclk.clk,
257 static struct clksrc_clk clk_aclk_corem0 = {
259 .name = "aclk_corem0",
260 .parent = &clk_coreclk.clk,
262 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
265 static struct clksrc_clk clk_aclk_cores = {
267 .name = "aclk_cores",
268 .parent = &clk_coreclk.clk,
270 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
273 static struct clksrc_clk clk_aclk_corem1 = {
275 .name = "aclk_corem1",
276 .parent = &clk_coreclk.clk,
278 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
281 static struct clksrc_clk clk_periphclk = {
284 .parent = &clk_coreclk.clk,
286 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
289 /* Core list of CMU_CORE side */
291 struct clk *clkset_corebus_list[] = {
292 [0] = &clk_mout_mpll.clk,
293 [1] = &clk_sclk_apll.clk,
296 struct clksrc_sources clkset_mout_corebus = {
297 .sources = clkset_corebus_list,
298 .nr_sources = ARRAY_SIZE(clkset_corebus_list),
301 static struct clksrc_clk clk_mout_corebus = {
303 .name = "mout_corebus",
305 .sources = &clkset_mout_corebus,
306 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
309 static struct clksrc_clk clk_sclk_dmc = {
312 .parent = &clk_mout_corebus.clk,
314 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
317 static struct clksrc_clk clk_aclk_cored = {
319 .name = "aclk_cored",
320 .parent = &clk_sclk_dmc.clk,
322 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
325 static struct clksrc_clk clk_aclk_corep = {
327 .name = "aclk_corep",
328 .parent = &clk_aclk_cored.clk,
330 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
333 static struct clksrc_clk clk_aclk_acp = {
336 .parent = &clk_mout_corebus.clk,
338 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
341 static struct clksrc_clk clk_pclk_acp = {
344 .parent = &clk_aclk_acp.clk,
346 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
349 /* Core list of CMU_TOP side */
351 struct clk *clkset_aclk_top_list[] = {
352 [0] = &clk_mout_mpll.clk,
353 [1] = &clk_sclk_apll.clk,
356 struct clksrc_sources clkset_aclk = {
357 .sources = clkset_aclk_top_list,
358 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
361 static struct clksrc_clk clk_aclk_200 = {
365 .sources = &clkset_aclk,
366 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
367 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
370 static struct clksrc_clk clk_aclk_100 = {
374 .sources = &clkset_aclk,
375 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
376 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
379 static struct clksrc_clk clk_aclk_160 = {
383 .sources = &clkset_aclk,
384 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
385 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
388 struct clksrc_clk clk_aclk_133 = {
392 .sources = &clkset_aclk,
393 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
394 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
397 static struct clk *clkset_vpllsrc_list[] = {
399 [1] = &clk_sclk_hdmi27m,
402 static struct clksrc_sources clkset_vpllsrc = {
403 .sources = clkset_vpllsrc_list,
404 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
407 static struct clksrc_clk clk_vpllsrc = {
410 .enable = exynos4_clksrc_mask_top_ctrl,
413 .sources = &clkset_vpllsrc,
414 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
417 static struct clk *clkset_sclk_vpll_list[] = {
418 [0] = &clk_vpllsrc.clk,
419 [1] = &clk_fout_vpll,
422 static struct clksrc_sources clkset_sclk_vpll = {
423 .sources = clkset_sclk_vpll_list,
424 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
427 struct clksrc_clk clk_sclk_vpll = {
431 .sources = &clkset_sclk_vpll,
432 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
435 static struct clk init_clocks_off[] = {
438 .parent = &clk_aclk_100.clk,
439 .enable = exynos4_clk_ip_peril_ctrl,
443 .devname = "s5p-mipi-csis.0",
444 .enable = exynos4_clk_ip_cam_ctrl,
448 .devname = "s5p-mipi-csis.1",
449 .enable = exynos4_clk_ip_cam_ctrl,
453 .devname = "exynos4-fimc.0",
454 .enable = exynos4_clk_ip_cam_ctrl,
458 .devname = "exynos4-fimc.1",
459 .enable = exynos4_clk_ip_cam_ctrl,
463 .devname = "exynos4-fimc.2",
464 .enable = exynos4_clk_ip_cam_ctrl,
468 .devname = "exynos4-fimc.3",
469 .enable = exynos4_clk_ip_cam_ctrl,
473 .devname = "exynos4-fb.0",
474 .enable = exynos4_clk_ip_lcd0_ctrl,
478 .devname = "s3c-sdhci.0",
479 .parent = &clk_aclk_133.clk,
480 .enable = exynos4_clk_ip_fsys_ctrl,
484 .devname = "s3c-sdhci.1",
485 .parent = &clk_aclk_133.clk,
486 .enable = exynos4_clk_ip_fsys_ctrl,
490 .devname = "s3c-sdhci.2",
491 .parent = &clk_aclk_133.clk,
492 .enable = exynos4_clk_ip_fsys_ctrl,
496 .devname = "s3c-sdhci.3",
497 .parent = &clk_aclk_133.clk,
498 .enable = exynos4_clk_ip_fsys_ctrl,
502 .parent = &clk_aclk_133.clk,
503 .enable = exynos4_clk_ip_fsys_ctrl,
507 .devname = "s3c-pl330.0",
508 .enable = exynos4_clk_ip_fsys_ctrl,
512 .devname = "s3c-pl330.1",
513 .enable = exynos4_clk_ip_fsys_ctrl,
517 .enable = exynos4_clk_ip_peril_ctrl,
518 .ctrlbit = (1 << 15),
521 .enable = exynos4_clk_ip_perir_ctrl,
522 .ctrlbit = (1 << 16),
525 .enable = exynos4_clk_ip_perir_ctrl,
526 .ctrlbit = (1 << 15),
529 .parent = &clk_aclk_100.clk,
530 .enable = exynos4_clk_ip_perir_ctrl,
531 .ctrlbit = (1 << 14),
534 .enable = exynos4_clk_ip_fsys_ctrl ,
535 .ctrlbit = (1 << 12),
538 .enable = exynos4_clk_ip_fsys_ctrl,
539 .ctrlbit = (1 << 13),
542 .devname = "s3c64xx-spi.0",
543 .enable = exynos4_clk_ip_peril_ctrl,
544 .ctrlbit = (1 << 16),
547 .devname = "s3c64xx-spi.1",
548 .enable = exynos4_clk_ip_peril_ctrl,
549 .ctrlbit = (1 << 17),
552 .devname = "s3c64xx-spi.2",
553 .enable = exynos4_clk_ip_peril_ctrl,
554 .ctrlbit = (1 << 18),
557 .devname = "samsung-i2s.0",
558 .enable = exynos4_clk_ip_peril_ctrl,
559 .ctrlbit = (1 << 19),
562 .devname = "samsung-i2s.1",
563 .enable = exynos4_clk_ip_peril_ctrl,
564 .ctrlbit = (1 << 20),
567 .devname = "samsung-i2s.2",
568 .enable = exynos4_clk_ip_peril_ctrl,
569 .ctrlbit = (1 << 21),
572 .devname = "samsung-ac97",
573 .enable = exynos4_clk_ip_peril_ctrl,
574 .ctrlbit = (1 << 27),
577 .enable = exynos4_clk_ip_image_ctrl,
581 .devname = "s5p-mfc",
582 .enable = exynos4_clk_ip_mfc_ctrl,
586 .devname = "s3c2440-i2c.0",
587 .parent = &clk_aclk_100.clk,
588 .enable = exynos4_clk_ip_peril_ctrl,
592 .devname = "s3c2440-i2c.1",
593 .parent = &clk_aclk_100.clk,
594 .enable = exynos4_clk_ip_peril_ctrl,
598 .devname = "s3c2440-i2c.2",
599 .parent = &clk_aclk_100.clk,
600 .enable = exynos4_clk_ip_peril_ctrl,
604 .devname = "s3c2440-i2c.3",
605 .parent = &clk_aclk_100.clk,
606 .enable = exynos4_clk_ip_peril_ctrl,
610 .devname = "s3c2440-i2c.4",
611 .parent = &clk_aclk_100.clk,
612 .enable = exynos4_clk_ip_peril_ctrl,
613 .ctrlbit = (1 << 10),
616 .devname = "s3c2440-i2c.5",
617 .parent = &clk_aclk_100.clk,
618 .enable = exynos4_clk_ip_peril_ctrl,
619 .ctrlbit = (1 << 11),
622 .devname = "s3c2440-i2c.6",
623 .parent = &clk_aclk_100.clk,
624 .enable = exynos4_clk_ip_peril_ctrl,
625 .ctrlbit = (1 << 12),
628 .devname = "s3c2440-i2c.7",
629 .parent = &clk_aclk_100.clk,
630 .enable = exynos4_clk_ip_peril_ctrl,
631 .ctrlbit = (1 << 13),
633 .name = "SYSMMU_MDMA",
634 .enable = exynos4_clk_ip_image_ctrl,
637 .name = "SYSMMU_FIMC0",
638 .enable = exynos4_clk_ip_cam_ctrl,
641 .name = "SYSMMU_FIMC1",
642 .enable = exynos4_clk_ip_cam_ctrl,
645 .name = "SYSMMU_FIMC2",
646 .enable = exynos4_clk_ip_cam_ctrl,
649 .name = "SYSMMU_FIMC3",
650 .enable = exynos4_clk_ip_cam_ctrl,
651 .ctrlbit = (1 << 10),
653 .name = "SYSMMU_JPEG",
654 .enable = exynos4_clk_ip_cam_ctrl,
655 .ctrlbit = (1 << 11),
657 .name = "SYSMMU_FIMD0",
658 .enable = exynos4_clk_ip_lcd0_ctrl,
661 .name = "SYSMMU_FIMD1",
662 .enable = exynos4_clk_ip_lcd1_ctrl,
665 .name = "SYSMMU_PCIe",
666 .enable = exynos4_clk_ip_fsys_ctrl,
667 .ctrlbit = (1 << 18),
669 .name = "SYSMMU_G2D",
670 .enable = exynos4_clk_ip_image_ctrl,
673 .name = "SYSMMU_ROTATOR",
674 .enable = exynos4_clk_ip_image_ctrl,
678 .enable = exynos4_clk_ip_tv_ctrl,
681 .name = "SYSMMU_MFC_L",
682 .enable = exynos4_clk_ip_mfc_ctrl,
685 .name = "SYSMMU_MFC_R",
686 .enable = exynos4_clk_ip_mfc_ctrl,
691 static struct clk init_clocks[] = {
694 .devname = "s5pv210-uart.0",
695 .enable = exynos4_clk_ip_peril_ctrl,
699 .devname = "s5pv210-uart.1",
700 .enable = exynos4_clk_ip_peril_ctrl,
704 .devname = "s5pv210-uart.2",
705 .enable = exynos4_clk_ip_peril_ctrl,
709 .devname = "s5pv210-uart.3",
710 .enable = exynos4_clk_ip_peril_ctrl,
714 .devname = "s5pv210-uart.4",
715 .enable = exynos4_clk_ip_peril_ctrl,
719 .devname = "s5pv210-uart.5",
720 .enable = exynos4_clk_ip_peril_ctrl,
725 struct clk *clkset_group_list[] = {
726 [0] = &clk_ext_xtal_mux,
728 [2] = &clk_sclk_hdmi27m,
729 [3] = &clk_sclk_usbphy0,
730 [4] = &clk_sclk_usbphy1,
731 [5] = &clk_sclk_hdmiphy,
732 [6] = &clk_mout_mpll.clk,
733 [7] = &clk_mout_epll.clk,
734 [8] = &clk_sclk_vpll.clk,
737 struct clksrc_sources clkset_group = {
738 .sources = clkset_group_list,
739 .nr_sources = ARRAY_SIZE(clkset_group_list),
742 static struct clk *clkset_mout_g2d0_list[] = {
743 [0] = &clk_mout_mpll.clk,
744 [1] = &clk_sclk_apll.clk,
747 static struct clksrc_sources clkset_mout_g2d0 = {
748 .sources = clkset_mout_g2d0_list,
749 .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
752 static struct clksrc_clk clk_mout_g2d0 = {
756 .sources = &clkset_mout_g2d0,
757 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
760 static struct clk *clkset_mout_g2d1_list[] = {
761 [0] = &clk_mout_epll.clk,
762 [1] = &clk_sclk_vpll.clk,
765 static struct clksrc_sources clkset_mout_g2d1 = {
766 .sources = clkset_mout_g2d1_list,
767 .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
770 static struct clksrc_clk clk_mout_g2d1 = {
774 .sources = &clkset_mout_g2d1,
775 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
778 static struct clk *clkset_mout_g2d_list[] = {
779 [0] = &clk_mout_g2d0.clk,
780 [1] = &clk_mout_g2d1.clk,
783 static struct clksrc_sources clkset_mout_g2d = {
784 .sources = clkset_mout_g2d_list,
785 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
788 static struct clk *clkset_mout_mfc0_list[] = {
789 [0] = &clk_mout_mpll.clk,
790 [1] = &clk_sclk_apll.clk,
793 static struct clksrc_sources clkset_mout_mfc0 = {
794 .sources = clkset_mout_mfc0_list,
795 .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list),
798 static struct clksrc_clk clk_mout_mfc0 = {
802 .sources = &clkset_mout_mfc0,
803 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
806 static struct clk *clkset_mout_mfc1_list[] = {
807 [0] = &clk_mout_epll.clk,
808 [1] = &clk_sclk_vpll.clk,
811 static struct clksrc_sources clkset_mout_mfc1 = {
812 .sources = clkset_mout_mfc1_list,
813 .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list),
816 static struct clksrc_clk clk_mout_mfc1 = {
820 .sources = &clkset_mout_mfc1,
821 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
824 static struct clk *clkset_mout_mfc_list[] = {
825 [0] = &clk_mout_mfc0.clk,
826 [1] = &clk_mout_mfc1.clk,
829 static struct clksrc_sources clkset_mout_mfc = {
830 .sources = clkset_mout_mfc_list,
831 .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
834 static struct clksrc_clk clk_dout_mmc0 = {
838 .sources = &clkset_group,
839 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
840 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
843 static struct clksrc_clk clk_dout_mmc1 = {
847 .sources = &clkset_group,
848 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
849 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
852 static struct clksrc_clk clk_dout_mmc2 = {
856 .sources = &clkset_group,
857 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
858 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
861 static struct clksrc_clk clk_dout_mmc3 = {
865 .sources = &clkset_group,
866 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
867 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
870 static struct clksrc_clk clk_dout_mmc4 = {
874 .sources = &clkset_group,
875 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
876 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
879 static struct clksrc_clk clksrcs[] = {
883 .devname = "s5pv210-uart.0",
884 .enable = exynos4_clksrc_mask_peril0_ctrl,
887 .sources = &clkset_group,
888 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
889 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
893 .devname = "s5pv210-uart.1",
894 .enable = exynos4_clksrc_mask_peril0_ctrl,
897 .sources = &clkset_group,
898 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
899 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
903 .devname = "s5pv210-uart.2",
904 .enable = exynos4_clksrc_mask_peril0_ctrl,
907 .sources = &clkset_group,
908 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
909 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
913 .devname = "s5pv210-uart.3",
914 .enable = exynos4_clksrc_mask_peril0_ctrl,
915 .ctrlbit = (1 << 12),
917 .sources = &clkset_group,
918 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
919 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
923 .enable = exynos4_clksrc_mask_peril0_ctrl,
924 .ctrlbit = (1 << 24),
926 .sources = &clkset_group,
927 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
928 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
932 .devname = "s5p-mipi-csis.0",
933 .enable = exynos4_clksrc_mask_cam_ctrl,
934 .ctrlbit = (1 << 24),
936 .sources = &clkset_group,
937 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
938 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
942 .devname = "s5p-mipi-csis.1",
943 .enable = exynos4_clksrc_mask_cam_ctrl,
944 .ctrlbit = (1 << 28),
946 .sources = &clkset_group,
947 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
948 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
952 .enable = exynos4_clksrc_mask_cam_ctrl,
953 .ctrlbit = (1 << 16),
955 .sources = &clkset_group,
956 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
957 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
961 .enable = exynos4_clksrc_mask_cam_ctrl,
962 .ctrlbit = (1 << 20),
964 .sources = &clkset_group,
965 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
966 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
970 .devname = "exynos4-fimc.0",
971 .enable = exynos4_clksrc_mask_cam_ctrl,
974 .sources = &clkset_group,
975 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
976 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
980 .devname = "exynos4-fimc.1",
981 .enable = exynos4_clksrc_mask_cam_ctrl,
984 .sources = &clkset_group,
985 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
986 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
990 .devname = "exynos4-fimc.2",
991 .enable = exynos4_clksrc_mask_cam_ctrl,
994 .sources = &clkset_group,
995 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
996 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
1000 .devname = "exynos4-fimc.3",
1001 .enable = exynos4_clksrc_mask_cam_ctrl,
1002 .ctrlbit = (1 << 12),
1004 .sources = &clkset_group,
1005 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
1006 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
1009 .name = "sclk_fimd",
1010 .devname = "exynos4-fb.0",
1011 .enable = exynos4_clksrc_mask_lcd0_ctrl,
1012 .ctrlbit = (1 << 0),
1014 .sources = &clkset_group,
1015 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
1016 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
1020 .devname = "s3c64xx-spi.0",
1021 .enable = exynos4_clksrc_mask_peril1_ctrl,
1022 .ctrlbit = (1 << 16),
1024 .sources = &clkset_group,
1025 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1026 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1030 .devname = "s3c64xx-spi.1",
1031 .enable = exynos4_clksrc_mask_peril1_ctrl,
1032 .ctrlbit = (1 << 20),
1034 .sources = &clkset_group,
1035 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1036 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1040 .devname = "s3c64xx-spi.2",
1041 .enable = exynos4_clksrc_mask_peril1_ctrl,
1042 .ctrlbit = (1 << 24),
1044 .sources = &clkset_group,
1045 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1046 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1049 .name = "sclk_fimg2d",
1051 .sources = &clkset_mout_g2d,
1052 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1053 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1057 .devname = "s5p-mfc",
1059 .sources = &clkset_mout_mfc,
1060 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1061 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1065 .devname = "s3c-sdhci.0",
1066 .parent = &clk_dout_mmc0.clk,
1067 .enable = exynos4_clksrc_mask_fsys_ctrl,
1068 .ctrlbit = (1 << 0),
1070 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1074 .devname = "s3c-sdhci.1",
1075 .parent = &clk_dout_mmc1.clk,
1076 .enable = exynos4_clksrc_mask_fsys_ctrl,
1077 .ctrlbit = (1 << 4),
1079 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1083 .devname = "s3c-sdhci.2",
1084 .parent = &clk_dout_mmc2.clk,
1085 .enable = exynos4_clksrc_mask_fsys_ctrl,
1086 .ctrlbit = (1 << 8),
1088 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1092 .devname = "s3c-sdhci.3",
1093 .parent = &clk_dout_mmc3.clk,
1094 .enable = exynos4_clksrc_mask_fsys_ctrl,
1095 .ctrlbit = (1 << 12),
1097 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1100 .name = "sclk_dwmmc",
1101 .parent = &clk_dout_mmc4.clk,
1102 .enable = exynos4_clksrc_mask_fsys_ctrl,
1103 .ctrlbit = (1 << 16),
1105 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1109 /* Clock initialization code */
1110 static struct clksrc_clk *sysclks[] = {
1143 static int xtal_rate;
1145 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1147 if (soc_is_exynos4210())
1148 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
1150 else if (soc_is_exynos4212() || soc_is_exynos4412())
1151 return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
1156 static struct clk_ops exynos4_fout_apll_ops = {
1157 .get_rate = exynos4_fout_apll_get_rate,
1160 void __init_or_cpufreq exynos4_setup_clocks(void)
1162 struct clk *xtal_clk;
1163 unsigned long apll = 0;
1164 unsigned long mpll = 0;
1165 unsigned long epll = 0;
1166 unsigned long vpll = 0;
1167 unsigned long vpllsrc;
1169 unsigned long armclk;
1170 unsigned long sclk_dmc;
1171 unsigned long aclk_200;
1172 unsigned long aclk_100;
1173 unsigned long aclk_160;
1174 unsigned long aclk_133;
1177 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1179 xtal_clk = clk_get(NULL, "xtal");
1180 BUG_ON(IS_ERR(xtal_clk));
1182 xtal = clk_get_rate(xtal_clk);
1188 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1190 if (soc_is_exynos4210()) {
1191 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
1193 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
1195 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1196 __raw_readl(S5P_EPLL_CON1), pll_4600);
1198 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1199 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1200 __raw_readl(S5P_VPLL_CON1), pll_4650c);
1201 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1202 apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
1203 mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
1204 epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
1205 __raw_readl(S5P_EPLL_CON1));
1207 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1208 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1209 __raw_readl(S5P_VPLL_CON1));
1214 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1215 clk_fout_mpll.rate = mpll;
1216 clk_fout_epll.rate = epll;
1217 clk_fout_vpll.rate = vpll;
1219 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1220 apll, mpll, epll, vpll);
1222 armclk = clk_get_rate(&clk_armclk.clk);
1223 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1225 aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1226 aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1227 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1228 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1230 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1231 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1232 armclk, sclk_dmc, aclk_200,
1233 aclk_100, aclk_160, aclk_133);
1235 clk_f.rate = armclk;
1236 clk_h.rate = sclk_dmc;
1237 clk_p.rate = aclk_100;
1239 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1240 s3c_set_clksrc(&clksrcs[ptr], true);
1243 static struct clk *clks[] __initdata = {
1244 /* Nothing here yet */
1247 #ifdef CONFIG_PM_SLEEP
1248 static int exynos4_clock_suspend(void)
1250 s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1254 static void exynos4_clock_resume(void)
1256 s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1260 #define exynos4_clock_suspend NULL
1261 #define exynos4_clock_resume NULL
1264 struct syscore_ops exynos4_clock_syscore_ops = {
1265 .suspend = exynos4_clock_suspend,
1266 .resume = exynos4_clock_resume,
1269 void __init exynos4_register_clocks(void)
1273 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1275 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1276 s3c_register_clksrc(sysclks[ptr], 1);
1278 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1279 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1281 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1282 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1284 register_syscore_ops(&exynos4_clock_syscore_ops);