arch/arm/mach-exynos/mct.c

   1 /* linux/arch/arm/mach-exynos4/mct.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * EXYNOS4 MCT(Multi-Core Timer) support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/sched.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/delay.h>
  21 #include <linux/percpu.h>
  22
  23 #include <asm/hardware/gic.h>
  24
  25 #include <plat/cpu.h>
  26
  27 #include <mach/map.h>
  28 #include <mach/irqs.h>
  29 #include <mach/regs-mct.h>
  30 #include <asm/mach/time.h>
  31
  32 enum {
  33         MCT_INT_SPI,
  34         MCT_INT_PPI
  35 };
  36
  37 static unsigned long clk_cnt_per_tick;
  38 static unsigned long clk_rate;
  39 static unsigned int mct_int_type;
  40
  41 struct mct_clock_event_device {
  42         struct clock_event_device *evt;
  43         void __iomem *base;
  44         char name[10];
  45 };
  46
  47 static void exynos4_mct_write(unsigned int value, void *addr)
  48 {
  49         void __iomem *stat_addr;
  50         u32 mask;
  51         u32 i;
  52
  53         __raw_writel(value, addr);
  54
  55         if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
  56                 u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
  57                 switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
  58                 case (u32) MCT_L_TCON_OFFSET:
  59                         stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
  60                         mask = 1 << 3;          /* L_TCON write status */
  61                         break;
  62                 case (u32) MCT_L_ICNTB_OFFSET:
  63                         stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
  64                         mask = 1 << 1;          /* L_ICNTB write status */
  65                         break;
  66                 case (u32) MCT_L_TCNTB_OFFSET:
  67                         stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
  68                         mask = 1 << 0;          /* L_TCNTB write status */
  69                         break;
  70                 default:
  71                         return;
  72                 }
  73         } else {
  74                 switch ((u32) addr) {
  75                 case (u32) EXYNOS4_MCT_G_TCON:
  76                         stat_addr = EXYNOS4_MCT_G_WSTAT;
  77                         mask = 1 << 16;         /* G_TCON write status */
  78                         break;
  79                 case (u32) EXYNOS4_MCT_G_COMP0_L:
  80                         stat_addr = EXYNOS4_MCT_G_WSTAT;
  81                         mask = 1 << 0;          /* G_COMP0_L write status */
  82                         break;
  83                 case (u32) EXYNOS4_MCT_G_COMP0_U:
  84                         stat_addr = EXYNOS4_MCT_G_WSTAT;
  85                         mask = 1 << 1;          /* G_COMP0_U write status */
  86                         break;
  87                 case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
  88                         stat_addr = EXYNOS4_MCT_G_WSTAT;
  89                         mask = 1 << 2;          /* G_COMP0_ADD_INCR w status */
  90                         break;
  91                 case (u32) EXYNOS4_MCT_G_CNT_L:
  92                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
  93                         mask = 1 << 0;          /* G_CNT_L write status */
  94                         break;
  95                 case (u32) EXYNOS4_MCT_G_CNT_U:
  96                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
  97                         mask = 1 << 1;          /* G_CNT_U write status */
  98                         break;
  99                 default:
 100                         return;
 101                 }
 102         }
 103
 104         /* Wait maximum 1 ms until written values are applied */
 105         for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
 106                 if (__raw_readl(stat_addr) & mask) {
 107                         __raw_writel(mask, stat_addr);
 108                         return;
 109                 }
 110
 111         panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
 112 }
 113
 114 /* Clocksource handling */
 115 static void exynos4_mct_frc_start(u32 hi, u32 lo)
 116 {
 117         u32 reg;
 118
 119         exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
 120         exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
 121
 122         reg = __raw_readl(EXYNOS4_MCT_G_TCON);
 123         reg |= MCT_G_TCON_START;
 124         exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
 125 }
 126
 127 static cycle_t exynos4_frc_read(struct clocksource *cs)
 128 {
 129         unsigned int lo, hi;
 130         u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
 131
 132         do {
 133                 hi = hi2;
 134                 lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
 135                 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
 136         } while (hi != hi2);
 137
 138         return ((cycle_t)hi << 32) | lo;
 139 }
 140
 141 static void exynos4_frc_resume(struct clocksource *cs)
 142 {
 143         exynos4_mct_frc_start(0, 0);
 144 }
 145
 146 struct clocksource mct_frc = {
 147         .name           = "mct-frc",
 148         .rating         = 400,
 149         .read           = exynos4_frc_read,
 150         .mask           = CLOCKSOURCE_MASK(64),
 151         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 152         .resume         = exynos4_frc_resume,
 153 };
 154
 155 static void __init exynos4_clocksource_init(void)
 156 {
 157         exynos4_mct_frc_start(0, 0);
 158
 159         if (clocksource_register_hz(&mct_frc, clk_rate))
 160                 panic("%s: can't register clocksource\n", mct_frc.name);
 161 }
 162
 163 static void exynos4_mct_comp0_stop(void)
 164 {
 165         unsigned int tcon;
 166
 167         tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
 168         tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
 169
 170         exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
 171         exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
 172 }
 173
 174 static void exynos4_mct_comp0_start(enum clock_event_mode mode,
 175                                     unsigned long cycles)
 176 {
 177         unsigned int tcon;
 178         cycle_t comp_cycle;
 179
 180         tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
 181
 182         if (mode == CLOCK_EVT_MODE_PERIODIC) {
 183                 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
 184                 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
 185         }
 186
 187         comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
 188         exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
 189         exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
 190
 191         exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
 192
 193         tcon |= MCT_G_TCON_COMP0_ENABLE;
 194         exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
 195 }
 196
 197 static int exynos4_comp_set_next_event(unsigned long cycles,
 198                                        struct clock_event_device *evt)
 199 {
 200         exynos4_mct_comp0_start(evt->mode, cycles);
 201
 202         return 0;
 203 }
 204
 205 static void exynos4_comp_set_mode(enum clock_event_mode mode,
 206                                   struct clock_event_device *evt)
 207 {
 208         exynos4_mct_comp0_stop();
 209
 210         switch (mode) {
 211         case CLOCK_EVT_MODE_PERIODIC:
 212                 exynos4_mct_comp0_start(mode, clk_cnt_per_tick);
 213                 break;
 214
 215         case CLOCK_EVT_MODE_ONESHOT:
 216         case CLOCK_EVT_MODE_UNUSED:
 217         case CLOCK_EVT_MODE_SHUTDOWN:
 218         case CLOCK_EVT_MODE_RESUME:
 219                 break;
 220         }
 221 }
 222
 223 static struct clock_event_device mct_comp_device = {
 224         .name           = "mct-comp",
 225         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 226         .rating         = 250,
 227         .set_next_event = exynos4_comp_set_next_event,
 228         .set_mode       = exynos4_comp_set_mode,
 229 };
 230
 231 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
 232 {
 233         struct clock_event_device *evt = dev_id;
 234
 235         exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
 236
 237         evt->event_handler(evt);
 238
 239         return IRQ_HANDLED;
 240 }
 241
 242 static struct irqaction mct_comp_event_irq = {
 243         .name           = "mct_comp_irq",
 244         .flags          = IRQF_TIMER | IRQF_IRQPOLL,
 245         .handler        = exynos4_mct_comp_isr,
 246         .dev_id         = &mct_comp_device,
 247 };
 248
 249 static void exynos4_clockevent_init(void)
 250 {
 251         clk_cnt_per_tick = clk_rate / 2 / HZ;
 252
 253         clockevents_calc_mult_shift(&mct_comp_device, clk_rate / 2, 5);
 254         mct_comp_device.max_delta_ns =
 255                 clockevent_delta2ns(0xffffffff, &mct_comp_device);
 256         mct_comp_device.min_delta_ns =
 257                 clockevent_delta2ns(0xf, &mct_comp_device);
 258         mct_comp_device.cpumask = cpumask_of(0);
 259         clockevents_register_device(&mct_comp_device);
 260
 261         setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
 262 }
 263
 264 #ifdef CONFIG_LOCAL_TIMERS
 265
 266 static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
 267
 268 /* Clock event handling */
 269 static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
 270 {
 271         unsigned long tmp;
 272         unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
 273         void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
 274
 275         tmp = __raw_readl(addr);
 276         if (tmp & mask) {
 277                 tmp &= ~mask;
 278                 exynos4_mct_write(tmp, addr);
 279         }
 280 }
 281
 282 static void exynos4_mct_tick_start(unsigned long cycles,
 283                                    struct mct_clock_event_device *mevt)
 284 {
 285         unsigned long tmp;
 286
 287         exynos4_mct_tick_stop(mevt);
 288
 289         tmp = (1 << 31) | cycles;       /* MCT_L_UPDATE_ICNTB */
 290
 291         /* update interrupt count buffer */
 292         exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
 293
 294         /* enable MCT tick interrupt */
 295         exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
 296
 297         tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
 298         tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
 299                MCT_L_TCON_INTERVAL_MODE;
 300         exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
 301 }
 302
 303 static int exynos4_tick_set_next_event(unsigned long cycles,
 304                                        struct clock_event_device *evt)
 305 {
 306         struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
 307
 308         exynos4_mct_tick_start(cycles, mevt);
 309
 310         return 0;
 311 }
 312
 313 static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
 314                                          struct clock_event_device *evt)
 315 {
 316         struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
 317
 318         exynos4_mct_tick_stop(mevt);
 319
 320         switch (mode) {
 321         case CLOCK_EVT_MODE_PERIODIC:
 322                 exynos4_mct_tick_start(clk_cnt_per_tick, mevt);
 323                 break;
 324
 325         case CLOCK_EVT_MODE_ONESHOT:
 326         case CLOCK_EVT_MODE_UNUSED:
 327         case CLOCK_EVT_MODE_SHUTDOWN:
 328         case CLOCK_EVT_MODE_RESUME:
 329                 break;
 330         }
 331 }
 332
 333 static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
 334 {
 335         struct clock_event_device *evt = mevt->evt;
 336
 337         /*
 338          * This is for supporting oneshot mode.
 339          * Mct would generate interrupt periodically
 340          * without explicit stopping.
 341          */
 342         if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
 343                 exynos4_mct_tick_stop(mevt);
 344
 345         /* Clear the MCT tick interrupt */
 346         if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
 347                 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
 348                 return 1;
 349         } else {
 350                 return 0;
 351         }
 352 }
 353
 354 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
 355 {
 356         struct mct_clock_event_device *mevt = dev_id;
 357         struct clock_event_device *evt = mevt->evt;
 358
 359         exynos4_mct_tick_clear(mevt);
 360
 361         evt->event_handler(evt);
 362
 363         return IRQ_HANDLED;
 364 }
 365
 366 static struct irqaction mct_tick0_event_irq = {
 367         .name           = "mct_tick0_irq",
 368         .flags          = IRQF_TIMER | IRQF_NOBALANCING,
 369         .handler        = exynos4_mct_tick_isr,
 370 };
 371
 372 static struct irqaction mct_tick1_event_irq = {
 373         .name           = "mct_tick1_irq",
 374         .flags          = IRQF_TIMER | IRQF_NOBALANCING,
 375         .handler        = exynos4_mct_tick_isr,
 376 };
 377
 378 static void exynos4_mct_tick_init(struct clock_event_device *evt)
 379 {
 380         struct mct_clock_event_device *mevt;
 381         unsigned int cpu = smp_processor_id();
 382
 383         mevt = this_cpu_ptr(&percpu_mct_tick);
 384         mevt->evt = evt;
 385
 386         mevt->base = EXYNOS4_MCT_L_BASE(cpu);
 387         sprintf(mevt->name, "mct_tick%d", cpu);
 388
 389         evt->name = mevt->name;
 390         evt->cpumask = cpumask_of(cpu);
 391         evt->set_next_event = exynos4_tick_set_next_event;
 392         evt->set_mode = exynos4_tick_set_mode;
 393         evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
 394         evt->rating = 450;
 395
 396         clockevents_calc_mult_shift(evt, clk_rate / 2, 5);
 397         evt->max_delta_ns =
 398                 clockevent_delta2ns(0x7fffffff, evt);
 399         evt->min_delta_ns =
 400                 clockevent_delta2ns(0xf, evt);
 401
 402         clockevents_register_device(evt);
 403
 404         exynos4_mct_write(0x1, mevt->base + MCT_L_TCNTB_OFFSET);
 405
 406         if (mct_int_type == MCT_INT_SPI) {
 407                 if (cpu == 0) {
 408                         mct_tick0_event_irq.dev_id = mevt;
 409                         evt->irq = IRQ_MCT_L0;
 410                         setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
 411                 } else {
 412                         mct_tick1_event_irq.dev_id = mevt;
 413                         evt->irq = IRQ_MCT_L1;
 414                         setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
 415                         irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
 416                 }
 417         } else {
 418                 enable_percpu_irq(IRQ_MCT_LOCALTIMER, 0);
 419         }
 420 }
 421
 422 /* Setup the local clock events for a CPU */
 423 int __cpuinit local_timer_setup(struct clock_event_device *evt)
 424 {
 425         exynos4_mct_tick_init(evt);
 426
 427         return 0;
 428 }
 429
 430 void local_timer_stop(struct clock_event_device *evt)
 431 {
 432         unsigned int cpu = smp_processor_id();
 433         evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
 434         if (mct_int_type == MCT_INT_SPI)
 435                 if (cpu == 0)
 436                         remove_irq(evt->irq, &mct_tick0_event_irq);
 437                 else
 438                         remove_irq(evt->irq, &mct_tick1_event_irq);
 439         else
 440                 disable_percpu_irq(IRQ_MCT_LOCALTIMER);
 441 }
 442 #endif /* CONFIG_LOCAL_TIMERS */
 443
 444 static void __init exynos4_timer_resources(void)
 445 {
 446         struct clk *mct_clk;
 447         mct_clk = clk_get(NULL, "xtal");
 448
 449         clk_rate = clk_get_rate(mct_clk);
 450
 451 #ifdef CONFIG_LOCAL_TIMERS
 452         if (mct_int_type == MCT_INT_PPI) {
 453                 int err;
 454
 455                 err = request_percpu_irq(IRQ_MCT_LOCALTIMER,
 456                                          exynos4_mct_tick_isr, "MCT",
 457                                          &percpu_mct_tick);
 458                 WARN(err, "MCT: can't request IRQ %d (%d)\n",
 459                      IRQ_MCT_LOCALTIMER, err);
 460         }
 461 #endif /* CONFIG_LOCAL_TIMERS */
 462 }
 463
 464 static void __init exynos4_timer_init(void)
 465 {
 466         if (soc_is_exynos4210())
 467                 mct_int_type = MCT_INT_SPI;
 468         else
 469                 mct_int_type = MCT_INT_PPI;
 470
 471         exynos4_timer_resources();
 472         exynos4_clocksource_init();
 473         exynos4_clockevent_init();
 474 }
 475
 476 struct sys_timer exynos4_timer = {
 477         .init           = exynos4_timer_init,
 478 };