arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h

   1 /*
   2  * arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
   3  */
   4
   5 #ifndef __ASM_ARCH_EP93XX_REGS_H
   6 #define __ASM_ARCH_EP93XX_REGS_H
   7
   8 /*
   9  * EP93xx Physical Memory Map:
  10  *
  11  * The ASDO pin is sampled at system reset to select a synchronous or
  12  * asynchronous boot configuration.  When ASDO is "1" (i.e. pulled-up)
  13  * the synchronous boot mode is selected.  When ASDO is "0" (i.e
  14  * pulled-down) the asynchronous boot mode is selected.
  15  *
  16  * In synchronous boot mode nSDCE3 is decoded starting at physical address
  17  * 0x00000000 and nCS0 is decoded starting at 0xf0000000.  For asynchronous
  18  * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
  19  * decoded at 0xf0000000.
  20  *
  21  * There is known errata for the EP93xx dealing with External Memory
  22  * Configurations.  Please refer to "AN273: EP93xx Silicon Rev E Design
  23  * Guidelines" for more information.  This document can be found at:
  24  *
  25  *      http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
  26  */
  27
  28 #define EP93XX_CS0_PHYS_BASE_ASYNC      0x00000000      /* ASDO Pin = 0 */
  29 #define EP93XX_SDCE3_PHYS_BASE_SYNC     0x00000000      /* ASDO Pin = 1 */
  30 #define EP93XX_CS1_PHYS_BASE            0x10000000
  31 #define EP93XX_CS2_PHYS_BASE            0x20000000
  32 #define EP93XX_CS3_PHYS_BASE            0x30000000
  33 #define EP93XX_PCMCIA_PHYS_BASE         0x40000000
  34 #define EP93XX_CS6_PHYS_BASE            0x60000000
  35 #define EP93XX_CS7_PHYS_BASE            0x70000000
  36 #define EP93XX_SDCE0_PHYS_BASE          0xc0000000
  37 #define EP93XX_SDCE1_PHYS_BASE          0xd0000000
  38 #define EP93XX_SDCE2_PHYS_BASE          0xe0000000
  39 #define EP93XX_SDCE3_PHYS_BASE_ASYNC    0xf0000000      /* ASDO Pin = 0 */
  40 #define EP93XX_CS0_PHYS_BASE_SYNC       0xf0000000      /* ASDO Pin = 1 */
  41
  42 /*
  43  * EP93xx linux memory map:
  44  *
  45  * virt         phys            size
  46  * fe800000                     5M              per-platform mappings
  47  * fed00000     80800000        2M              APB
  48  * fef00000     80000000        1M              AHB
  49  */
  50
  51 #define EP93XX_AHB_PHYS_BASE            0x80000000
  52 #define EP93XX_AHB_VIRT_BASE            0xfef00000
  53 #define EP93XX_AHB_SIZE                 0x00100000
  54
  55 #define EP93XX_AHB_IOMEM(x)             IOMEM(EP93XX_AHB_VIRT_BASE + (x))
  56
  57 #define EP93XX_APB_PHYS_BASE            0x80800000
  58 #define EP93XX_APB_VIRT_BASE            0xfed00000
  59 #define EP93XX_APB_SIZE                 0x00200000
  60
  61 #define EP93XX_APB_IOMEM(x)             IOMEM(EP93XX_APB_VIRT_BASE + (x))
  62
  63
  64 /* AHB peripherals */
  65 #define EP93XX_DMA_BASE                 EP93XX_AHB_IOMEM(0x00000000)
  66
  67 #define EP93XX_ETHERNET_PHYS_BASE       (EP93XX_AHB_PHYS_BASE + 0x00010000)
  68 #define EP93XX_ETHERNET_BASE            EP93XX_AHB_IOMEM(0x00010000)
  69
  70 #define EP93XX_USB_PHYS_BASE            (EP93XX_AHB_PHYS_BASE + 0x00020000)
  71 #define EP93XX_USB_BASE                 EP93XX_AHB_IOMEM(0x00020000)
  72
  73 #define EP93XX_RASTER_PHYS_BASE         (EP93XX_AHB_PHYS_BASE + 0x00030000)
  74 #define EP93XX_RASTER_BASE              EP93XX_AHB_IOMEM(0x00030000)
  75
  76 #define EP93XX_GRAPHICS_ACCEL_BASE      EP93XX_AHB_IOMEM(0x00040000)
  77
  78 #define EP93XX_SDRAM_CONTROLLER_BASE    EP93XX_AHB_IOMEM(0x00060000)
  79
  80 #define EP93XX_PCMCIA_CONTROLLER_BASE   EP93XX_AHB_IOMEM(0x00080000)
  81
  82 #define EP93XX_BOOT_ROM_BASE            EP93XX_AHB_IOMEM(0x00090000)
  83
  84 #define EP93XX_IDE_BASE                 EP93XX_AHB_IOMEM(0x000a0000)
  85
  86 #define EP93XX_VIC1_BASE                EP93XX_AHB_IOMEM(0x000b0000)
  87
  88 #define EP93XX_VIC2_BASE                EP93XX_AHB_IOMEM(0x000c0000)
  89
  90
  91 /* APB peripherals */
  92 #define EP93XX_TIMER_BASE               EP93XX_APB_IOMEM(0x00010000)
  93 #define EP93XX_TIMER_REG(x)             (EP93XX_TIMER_BASE + (x))
  94 #define EP93XX_TIMER1_LOAD              EP93XX_TIMER_REG(0x00)
  95 #define EP93XX_TIMER1_VALUE             EP93XX_TIMER_REG(0x04)
  96 #define EP93XX_TIMER1_CONTROL           EP93XX_TIMER_REG(0x08)
  97 #define EP93XX_TIMER1_CLEAR             EP93XX_TIMER_REG(0x0c)
  98 #define EP93XX_TIMER2_LOAD              EP93XX_TIMER_REG(0x20)
  99 #define EP93XX_TIMER2_VALUE             EP93XX_TIMER_REG(0x24)
 100 #define EP93XX_TIMER2_CONTROL           EP93XX_TIMER_REG(0x28)
 101 #define EP93XX_TIMER2_CLEAR             EP93XX_TIMER_REG(0x2c)
 102 #define EP93XX_TIMER4_VALUE_LOW         EP93XX_TIMER_REG(0x60)
 103 #define EP93XX_TIMER4_VALUE_HIGH        EP93XX_TIMER_REG(0x64)
 104 #define EP93XX_TIMER3_LOAD              EP93XX_TIMER_REG(0x80)
 105 #define EP93XX_TIMER3_VALUE             EP93XX_TIMER_REG(0x84)
 106 #define EP93XX_TIMER3_CONTROL           EP93XX_TIMER_REG(0x88)
 107 #define EP93XX_TIMER3_CLEAR             EP93XX_TIMER_REG(0x8c)
 108
 109 #define EP93XX_I2S_BASE                 EP93XX_APB_IOMEM(0x00020000)
 110
 111 #define EP93XX_SECURITY_BASE            EP93XX_APB_IOMEM(0x00030000)
 112
 113 #define EP93XX_GPIO_BASE                EP93XX_APB_IOMEM(0x00040000)
 114 #define EP93XX_GPIO_REG(x)              (EP93XX_GPIO_BASE + (x))
 115 #define EP93XX_GPIO_F_INT_TYPE1         EP93XX_GPIO_REG(0x4c)
 116 #define EP93XX_GPIO_F_INT_TYPE2         EP93XX_GPIO_REG(0x50)
 117 #define EP93XX_GPIO_F_INT_ACK           EP93XX_GPIO_REG(0x54)
 118 #define EP93XX_GPIO_F_INT_ENABLE        EP93XX_GPIO_REG(0x58)
 119 #define EP93XX_GPIO_F_INT_STATUS        EP93XX_GPIO_REG(0x5c)
 120 #define EP93XX_GPIO_A_INT_TYPE1         EP93XX_GPIO_REG(0x90)
 121 #define EP93XX_GPIO_A_INT_TYPE2         EP93XX_GPIO_REG(0x94)
 122 #define EP93XX_GPIO_A_INT_ACK           EP93XX_GPIO_REG(0x98)
 123 #define EP93XX_GPIO_A_INT_ENABLE        EP93XX_GPIO_REG(0x9c)
 124 #define EP93XX_GPIO_A_INT_STATUS        EP93XX_GPIO_REG(0xa0)
 125 #define EP93XX_GPIO_B_INT_TYPE1         EP93XX_GPIO_REG(0xac)
 126 #define EP93XX_GPIO_B_INT_TYPE2         EP93XX_GPIO_REG(0xb0)
 127 #define EP93XX_GPIO_B_INT_ACK           EP93XX_GPIO_REG(0xb4)
 128 #define EP93XX_GPIO_B_INT_ENABLE        EP93XX_GPIO_REG(0xb8)
 129 #define EP93XX_GPIO_B_INT_STATUS        EP93XX_GPIO_REG(0xbc)
 130
 131 #define EP93XX_AAC_BASE                 EP93XX_APB_IOMEM(0x00080000)
 132
 133 #define EP93XX_SPI_BASE                 EP93XX_APB_IOMEM(0x000a0000)
 134
 135 #define EP93XX_IRDA_BASE                EP93XX_APB_IOMEM(0x000b0000)
 136
 137 #define EP93XX_UART1_PHYS_BASE          (EP93XX_APB_PHYS_BASE + 0x000c0000)
 138 #define EP93XX_UART1_BASE               EP93XX_APB_IOMEM(0x000c0000)
 139
 140 #define EP93XX_UART2_PHYS_BASE          (EP93XX_APB_PHYS_BASE + 0x000d0000)
 141 #define EP93XX_UART2_BASE               EP93XX_APB_IOMEM(0x000d0000)
 142
 143 #define EP93XX_UART3_PHYS_BASE          (EP93XX_APB_PHYS_BASE + 0x000e0000)
 144 #define EP93XX_UART3_BASE               EP93XX_APB_IOMEM(0x000e0000)
 145
 146 #define EP93XX_KEY_MATRIX_BASE          EP93XX_APB_IOMEM(0x000f0000)
 147
 148 #define EP93XX_ADC_BASE                 EP93XX_APB_IOMEM(0x00100000)
 149 #define EP93XX_TOUCHSCREEN_BASE         EP93XX_APB_IOMEM(0x00100000)
 150
 151 #define EP93XX_PWM_PHYS_BASE            (EP93XX_APB_PHYS_BASE + 0x00110000)
 152 #define EP93XX_PWM_BASE                 EP93XX_APB_IOMEM(0x00110000)
 153
 154 #define EP93XX_RTC_PHYS_BASE            (EP93XX_APB_PHYS_BASE + 0x00120000)
 155 #define EP93XX_RTC_BASE                 EP93XX_APB_IOMEM(0x00120000)
 156
 157 #define EP93XX_SYSCON_BASE              EP93XX_APB_IOMEM(0x00130000)
 158 #define EP93XX_SYSCON_REG(x)            (EP93XX_SYSCON_BASE + (x))
 159 #define EP93XX_SYSCON_POWER_STATE       EP93XX_SYSCON_REG(0x00)
 160 #define EP93XX_SYSCON_PWRCNT            EP93XX_SYSCON_REG(0x04)
 161 #define EP93XX_SYSCON_PWRCNT_FIR_EN     (1<<31)
 162 #define EP93XX_SYSCON_PWRCNT_UARTBAUD   (1<<29)
 163 #define EP93XX_SYSCON_PWRCNT_USH_EN     (1<<28)
 164 #define EP93XX_SYSCON_PWRCNT_DMA_M2M1   (1<<27)
 165 #define EP93XX_SYSCON_PWRCNT_DMA_M2M0   (1<<26)
 166 #define EP93XX_SYSCON_PWRCNT_DMA_M2P8   (1<<25)
 167 #define EP93XX_SYSCON_PWRCNT_DMA_M2P9   (1<<24)
 168 #define EP93XX_SYSCON_PWRCNT_DMA_M2P6   (1<<23)
 169 #define EP93XX_SYSCON_PWRCNT_DMA_M2P7   (1<<22)
 170 #define EP93XX_SYSCON_PWRCNT_DMA_M2P4   (1<<21)
 171 #define EP93XX_SYSCON_PWRCNT_DMA_M2P5   (1<<20)
 172 #define EP93XX_SYSCON_PWRCNT_DMA_M2P2   (1<<19)
 173 #define EP93XX_SYSCON_PWRCNT_DMA_M2P3   (1<<18)
 174 #define EP93XX_SYSCON_PWRCNT_DMA_M2P0   (1<<17)
 175 #define EP93XX_SYSCON_PWRCNT_DMA_M2P1   (1<<16)
 176 #define EP93XX_SYSCON_HALT              EP93XX_SYSCON_REG(0x08)
 177 #define EP93XX_SYSCON_STANDBY           EP93XX_SYSCON_REG(0x0c)
 178 #define EP93XX_SYSCON_CLOCK_SET1        EP93XX_SYSCON_REG(0x20)
 179 #define EP93XX_SYSCON_CLOCK_SET2        EP93XX_SYSCON_REG(0x24)
 180 #define EP93XX_SYSCON_DEVCFG            EP93XX_SYSCON_REG(0x80)
 181 #define EP93XX_SYSCON_DEVCFG_SWRST      (1<<31)
 182 #define EP93XX_SYSCON_DEVCFG_D1ONG      (1<<30)
 183 #define EP93XX_SYSCON_DEVCFG_D0ONG      (1<<29)
 184 #define EP93XX_SYSCON_DEVCFG_IONU2      (1<<28)
 185 #define EP93XX_SYSCON_DEVCFG_GONK       (1<<27)
 186 #define EP93XX_SYSCON_DEVCFG_TONG       (1<<26)
 187 #define EP93XX_SYSCON_DEVCFG_MONG       (1<<25)
 188 #define EP93XX_SYSCON_DEVCFG_U3EN       (1<<24)
 189 #define EP93XX_SYSCON_DEVCFG_CPENA      (1<<23)
 190 #define EP93XX_SYSCON_DEVCFG_A2ONG      (1<<22)
 191 #define EP93XX_SYSCON_DEVCFG_A1ONG      (1<<21)
 192 #define EP93XX_SYSCON_DEVCFG_U2EN       (1<<20)
 193 #define EP93XX_SYSCON_DEVCFG_EXVC       (1<<19)
 194 #define EP93XX_SYSCON_DEVCFG_U1EN       (1<<18)
 195 #define EP93XX_SYSCON_DEVCFG_TIN        (1<<17)
 196 #define EP93XX_SYSCON_DEVCFG_HC3IN      (1<<15)
 197 #define EP93XX_SYSCON_DEVCFG_HC3EN      (1<<14)
 198 #define EP93XX_SYSCON_DEVCFG_HC1IN      (1<<13)
 199 #define EP93XX_SYSCON_DEVCFG_HC1EN      (1<<12)
 200 #define EP93XX_SYSCON_DEVCFG_HONIDE     (1<<11)
 201 #define EP93XX_SYSCON_DEVCFG_GONIDE     (1<<10)
 202 #define EP93XX_SYSCON_DEVCFG_PONG       (1<<9)
 203 #define EP93XX_SYSCON_DEVCFG_EONIDE     (1<<8)
 204 #define EP93XX_SYSCON_DEVCFG_I2SONSSP   (1<<7)
 205 #define EP93XX_SYSCON_DEVCFG_I2SONAC97  (1<<6)
 206 #define EP93XX_SYSCON_DEVCFG_RASONP3    (1<<4)
 207 #define EP93XX_SYSCON_DEVCFG_RAS        (1<<3)
 208 #define EP93XX_SYSCON_DEVCFG_ADCPD      (1<<2)
 209 #define EP93XX_SYSCON_DEVCFG_KEYS       (1<<1)
 210 #define EP93XX_SYSCON_DEVCFG_SHENA      (1<<0)
 211 #define EP93XX_SYSCON_VIDCLKDIV         EP93XX_SYSCON_REG(0x84)
 212 #define EP93XX_SYSCON_CLKDIV_ENABLE     (1<<15)
 213 #define EP93XX_SYSCON_CLKDIV_ESEL       (1<<14)
 214 #define EP93XX_SYSCON_CLKDIV_PSEL       (1<<13)
 215 #define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
 216 #define EP93XX_SYSCON_KEYTCHCLKDIV      EP93XX_SYSCON_REG(0x90)
 217 #define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
 218 #define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
 219 #define EP93XX_SYSCON_KEYTCHCLKDIV_KEN  (1<<15)
 220 #define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
 221 #define EP93XX_SYSCON_SWLOCK            EP93XX_SYSCON_REG(0xc0)
 222
 223 #define EP93XX_WATCHDOG_BASE            EP93XX_APB_IOMEM(0x00140000)
 224
 225
 226 #endif