arch/arm/mach-ep93xx/core.c

   1 /*
   2  * arch/arm/mach-ep93xx/core.c
   3  * Core routines for Cirrus EP93xx chips.
   4  *
   5  * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
   6  * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
   7  *
   8  * Thanks go to Michael Burian and Ray Lehtiniemi for their key
   9  * role in the ep93xx linux community.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or (at
  14  * your option) any later version.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/timex.h>
  23 #include <linux/io.h>
  24 #include <linux/gpio.h>
  25 #include <linux/leds.h>
  26 #include <linux/termios.h>
  27 #include <linux/amba/bus.h>
  28 #include <linux/amba/serial.h>
  29 #include <linux/i2c.h>
  30 #include <linux/i2c-gpio.h>
  31
  32 #include <mach/hardware.h>
  33 #include <mach/fb.h>
  34
  35 #include <asm/mach/map.h>
  36 #include <asm/mach/time.h>
  37 #include <asm/mach/irq.h>
  38
  39 #include <asm/hardware/vic.h>
  40
  41
  42 /*************************************************************************
  43  * Static I/O mappings that are needed for all EP93xx platforms
  44  *************************************************************************/
  45 static struct map_desc ep93xx_io_desc[] __initdata = {
  46         {
  47                 .virtual        = EP93XX_AHB_VIRT_BASE,
  48                 .pfn            = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
  49                 .length         = EP93XX_AHB_SIZE,
  50                 .type           = MT_DEVICE,
  51         }, {
  52                 .virtual        = EP93XX_APB_VIRT_BASE,
  53                 .pfn            = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
  54                 .length         = EP93XX_APB_SIZE,
  55                 .type           = MT_DEVICE,
  56         },
  57 };
  58
  59 void __init ep93xx_map_io(void)
  60 {
  61         iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
  62 }
  63
  64
  65 /*************************************************************************
  66  * Timer handling for EP93xx
  67  *************************************************************************
  68  * The ep93xx has four internal timers.  Timers 1, 2 (both 16 bit) and
  69  * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
  70  * an interrupt on underflow.  Timer 4 (40 bit) counts down at 983.04 kHz,
  71  * is free-running, and can't generate interrupts.
  72  *
  73  * The 508 kHz timers are ideal for use for the timer interrupt, as the
  74  * most common values of HZ divide 508 kHz nicely.  We pick one of the 16
  75  * bit timers (timer 1) since we don't need more than 16 bits of reload
  76  * value as long as HZ >= 8.
  77  *
  78  * The higher clock rate of timer 4 makes it a better choice than the
  79  * other timers for use in gettimeoffset(), while the fact that it can't
  80  * generate interrupts means we don't have to worry about not being able
  81  * to use this timer for something else.  We also use timer 4 for keeping
  82  * track of lost jiffies.
  83  */
  84 static unsigned int last_jiffy_time;
  85
  86 #define TIMER4_TICKS_PER_JIFFY          DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
  87
  88 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
  89 {
  90         __raw_writel(1, EP93XX_TIMER1_CLEAR);
  91         while ((signed long)
  92                 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
  93                                                 >= TIMER4_TICKS_PER_JIFFY) {
  94                 last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
  95                 timer_tick();
  96         }
  97
  98         return IRQ_HANDLED;
  99 }
 100
 101 static struct irqaction ep93xx_timer_irq = {
 102         .name           = "ep93xx timer",
 103         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 104         .handler        = ep93xx_timer_interrupt,
 105 };
 106
 107 static void __init ep93xx_timer_init(void)
 108 {
 109         /* Enable periodic HZ timer.  */
 110         __raw_writel(0x48, EP93XX_TIMER1_CONTROL);
 111         __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
 112         __raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
 113
 114         /* Enable lost jiffy timer.  */
 115         __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
 116
 117         setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
 118 }
 119
 120 static unsigned long ep93xx_gettimeoffset(void)
 121 {
 122         int offset;
 123
 124         offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
 125
 126         /* Calculate (1000000 / 983040) * offset.  */
 127         return offset + (53 * offset / 3072);
 128 }
 129
 130 struct sys_timer ep93xx_timer = {
 131         .init           = ep93xx_timer_init,
 132         .offset         = ep93xx_gettimeoffset,
 133 };
 134
 135
 136 /*************************************************************************
 137  * GPIO handling for EP93xx
 138  *************************************************************************/
 139 static unsigned char gpio_int_unmasked[3];
 140 static unsigned char gpio_int_enabled[3];
 141 static unsigned char gpio_int_type1[3];
 142 static unsigned char gpio_int_type2[3];
 143 static unsigned char gpio_int_debounce[3];
 144
 145 /* Port ordering is: A B F */
 146 static const u8 int_type1_register_offset[3]    = { 0x90, 0xac, 0x4c };
 147 static const u8 int_type2_register_offset[3]    = { 0x94, 0xb0, 0x50 };
 148 static const u8 eoi_register_offset[3]          = { 0x98, 0xb4, 0x54 };
 149 static const u8 int_en_register_offset[3]       = { 0x9c, 0xb8, 0x58 };
 150 static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
 151
 152 void ep93xx_gpio_update_int_params(unsigned port)
 153 {
 154         BUG_ON(port > 2);
 155
 156         __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
 157
 158         __raw_writeb(gpio_int_type2[port],
 159                 EP93XX_GPIO_REG(int_type2_register_offset[port]));
 160
 161         __raw_writeb(gpio_int_type1[port],
 162                 EP93XX_GPIO_REG(int_type1_register_offset[port]));
 163
 164         __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
 165                 EP93XX_GPIO_REG(int_en_register_offset[port]));
 166 }
 167
 168 void ep93xx_gpio_int_mask(unsigned line)
 169 {
 170         gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
 171 }
 172
 173 void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
 174 {
 175         int line = irq_to_gpio(irq);
 176         int port = line >> 3;
 177         int port_mask = 1 << (line & 7);
 178
 179         if (enable)
 180                 gpio_int_debounce[port] |= port_mask;
 181         else
 182                 gpio_int_debounce[port] &= ~port_mask;
 183
 184         __raw_writeb(gpio_int_debounce[port],
 185                 EP93XX_GPIO_REG(int_debounce_register_offset[port]));
 186 }
 187 EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
 188
 189 /*************************************************************************
 190  * EP93xx IRQ handling
 191  *************************************************************************/
 192 static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
 193 {
 194         unsigned char status;
 195         int i;
 196
 197         status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
 198         for (i = 0; i < 8; i++) {
 199                 if (status & (1 << i)) {
 200                         int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
 201                         generic_handle_irq(gpio_irq);
 202                 }
 203         }
 204
 205         status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
 206         for (i = 0; i < 8; i++) {
 207                 if (status & (1 << i)) {
 208                         int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
 209                         desc = irq_desc + gpio_irq;
 210                         generic_handle_irq(gpio_irq);
 211                 }
 212         }
 213 }
 214
 215 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
 216 {
 217         /*
 218          * map discontiguous hw irq range to continous sw irq range:
 219          *
 220          *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
 221          */
 222         int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
 223         int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
 224
 225         generic_handle_irq(gpio_irq);
 226 }
 227
 228 static void ep93xx_gpio_irq_ack(unsigned int irq)
 229 {
 230         int line = irq_to_gpio(irq);
 231         int port = line >> 3;
 232         int port_mask = 1 << (line & 7);
 233
 234         if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 235                 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
 236                 ep93xx_gpio_update_int_params(port);
 237         }
 238
 239         __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
 240 }
 241
 242 static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
 243 {
 244         int line = irq_to_gpio(irq);
 245         int port = line >> 3;
 246         int port_mask = 1 << (line & 7);
 247
 248         if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
 249                 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
 250
 251         gpio_int_unmasked[port] &= ~port_mask;
 252         ep93xx_gpio_update_int_params(port);
 253
 254         __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
 255 }
 256
 257 static void ep93xx_gpio_irq_mask(unsigned int irq)
 258 {
 259         int line = irq_to_gpio(irq);
 260         int port = line >> 3;
 261
 262         gpio_int_unmasked[port] &= ~(1 << (line & 7));
 263         ep93xx_gpio_update_int_params(port);
 264 }
 265
 266 static void ep93xx_gpio_irq_unmask(unsigned int irq)
 267 {
 268         int line = irq_to_gpio(irq);
 269         int port = line >> 3;
 270
 271         gpio_int_unmasked[port] |= 1 << (line & 7);
 272         ep93xx_gpio_update_int_params(port);
 273 }
 274
 275
 276 /*
 277  * gpio_int_type1 controls whether the interrupt is level (0) or
 278  * edge (1) triggered, while gpio_int_type2 controls whether it
 279  * triggers on low/falling (0) or high/rising (1).
 280  */
 281 static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
 282 {
 283         struct irq_desc *desc = irq_desc + irq;
 284         const int gpio = irq_to_gpio(irq);
 285         const int port = gpio >> 3;
 286         const int port_mask = 1 << (gpio & 7);
 287
 288         gpio_direction_input(gpio);
 289
 290         switch (type) {
 291         case IRQ_TYPE_EDGE_RISING:
 292                 gpio_int_type1[port] |= port_mask;
 293                 gpio_int_type2[port] |= port_mask;
 294                 desc->handle_irq = handle_edge_irq;
 295                 break;
 296         case IRQ_TYPE_EDGE_FALLING:
 297                 gpio_int_type1[port] |= port_mask;
 298                 gpio_int_type2[port] &= ~port_mask;
 299                 desc->handle_irq = handle_edge_irq;
 300                 break;
 301         case IRQ_TYPE_LEVEL_HIGH:
 302                 gpio_int_type1[port] &= ~port_mask;
 303                 gpio_int_type2[port] |= port_mask;
 304                 desc->handle_irq = handle_level_irq;
 305                 break;
 306         case IRQ_TYPE_LEVEL_LOW:
 307                 gpio_int_type1[port] &= ~port_mask;
 308                 gpio_int_type2[port] &= ~port_mask;
 309                 desc->handle_irq = handle_level_irq;
 310                 break;
 311         case IRQ_TYPE_EDGE_BOTH:
 312                 gpio_int_type1[port] |= port_mask;
 313                 /* set initial polarity based on current input level */
 314                 if (gpio_get_value(gpio))
 315                         gpio_int_type2[port] &= ~port_mask; /* falling */
 316                 else
 317                         gpio_int_type2[port] |= port_mask; /* rising */
 318                 desc->handle_irq = handle_edge_irq;
 319                 break;
 320         default:
 321                 pr_err("ep93xx: failed to set irq type %d for gpio %d\n",
 322                        type, gpio);
 323                 return -EINVAL;
 324         }
 325
 326         gpio_int_enabled[port] |= port_mask;
 327
 328         desc->status &= ~IRQ_TYPE_SENSE_MASK;
 329         desc->status |= type & IRQ_TYPE_SENSE_MASK;
 330
 331         ep93xx_gpio_update_int_params(port);
 332
 333         return 0;
 334 }
 335
 336 static struct irq_chip ep93xx_gpio_irq_chip = {
 337         .name           = "GPIO",
 338         .ack            = ep93xx_gpio_irq_ack,
 339         .mask_ack       = ep93xx_gpio_irq_mask_ack,
 340         .mask           = ep93xx_gpio_irq_mask,
 341         .unmask         = ep93xx_gpio_irq_unmask,
 342         .set_type       = ep93xx_gpio_irq_type,
 343 };
 344
 345
 346 void __init ep93xx_init_irq(void)
 347 {
 348         int gpio_irq;
 349
 350         vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
 351         vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
 352
 353         for (gpio_irq = gpio_to_irq(0);
 354              gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
 355                 set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
 356                 set_irq_handler(gpio_irq, handle_level_irq);
 357                 set_irq_flags(gpio_irq, IRQF_VALID);
 358         }
 359
 360         set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
 361         set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
 362         set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
 363         set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
 364         set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
 365         set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
 366         set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
 367         set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
 368         set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
 369 }
 370
 371
 372 /*************************************************************************
 373  * EP93xx System Controller Software Locked register handling
 374  *************************************************************************/
 375
 376 /*
 377  * syscon_swlock prevents anything else from writing to the syscon
 378  * block while a software locked register is being written.
 379  */
 380 static DEFINE_SPINLOCK(syscon_swlock);
 381
 382 void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
 383 {
 384         unsigned long flags;
 385
 386         spin_lock_irqsave(&syscon_swlock, flags);
 387
 388         __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
 389         __raw_writel(val, reg);
 390
 391         spin_unlock_irqrestore(&syscon_swlock, flags);
 392 }
 393 EXPORT_SYMBOL(ep93xx_syscon_swlocked_write);
 394
 395 void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
 396 {
 397         unsigned long flags;
 398         unsigned int val;
 399
 400         spin_lock_irqsave(&syscon_swlock, flags);
 401
 402         val = __raw_readl(EP93XX_SYSCON_DEVCFG);
 403         val |= set_bits;
 404         val &= ~clear_bits;
 405         __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
 406         __raw_writel(val, EP93XX_SYSCON_DEVCFG);
 407
 408         spin_unlock_irqrestore(&syscon_swlock, flags);
 409 }
 410 EXPORT_SYMBOL(ep93xx_devcfg_set_clear);
 411
 412
 413 /*************************************************************************
 414  * EP93xx peripheral handling
 415  *************************************************************************/
 416 #define EP93XX_UART_MCR_OFFSET          (0x0100)
 417
 418 static void ep93xx_uart_set_mctrl(struct amba_device *dev,
 419                                   void __iomem *base, unsigned int mctrl)
 420 {
 421         unsigned int mcr;
 422
 423         mcr = 0;
 424         if (!(mctrl & TIOCM_RTS))
 425                 mcr |= 2;
 426         if (!(mctrl & TIOCM_DTR))
 427                 mcr |= 1;
 428
 429         __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
 430 }
 431
 432 static struct amba_pl010_data ep93xx_uart_data = {
 433         .set_mctrl      = ep93xx_uart_set_mctrl,
 434 };
 435
 436 static struct amba_device uart1_device = {
 437         .dev            = {
 438                 .init_name      = "apb:uart1",
 439                 .platform_data  = &ep93xx_uart_data,
 440         },
 441         .res            = {
 442                 .start  = EP93XX_UART1_PHYS_BASE,
 443                 .end    = EP93XX_UART1_PHYS_BASE + 0x0fff,
 444                 .flags  = IORESOURCE_MEM,
 445         },
 446         .irq            = { IRQ_EP93XX_UART1, NO_IRQ },
 447         .periphid       = 0x00041010,
 448 };
 449
 450 static struct amba_device uart2_device = {
 451         .dev            = {
 452                 .init_name      = "apb:uart2",
 453                 .platform_data  = &ep93xx_uart_data,
 454         },
 455         .res            = {
 456                 .start  = EP93XX_UART2_PHYS_BASE,
 457                 .end    = EP93XX_UART2_PHYS_BASE + 0x0fff,
 458                 .flags  = IORESOURCE_MEM,
 459         },
 460         .irq            = { IRQ_EP93XX_UART2, NO_IRQ },
 461         .periphid       = 0x00041010,
 462 };
 463
 464 static struct amba_device uart3_device = {
 465         .dev            = {
 466                 .init_name      = "apb:uart3",
 467                 .platform_data  = &ep93xx_uart_data,
 468         },
 469         .res            = {
 470                 .start  = EP93XX_UART3_PHYS_BASE,
 471                 .end    = EP93XX_UART3_PHYS_BASE + 0x0fff,
 472                 .flags  = IORESOURCE_MEM,
 473         },
 474         .irq            = { IRQ_EP93XX_UART3, NO_IRQ },
 475         .periphid       = 0x00041010,
 476 };
 477
 478
 479 static struct resource ep93xx_rtc_resource[] = {
 480         {
 481                 .start          = EP93XX_RTC_PHYS_BASE,
 482                 .end            = EP93XX_RTC_PHYS_BASE + 0x10c - 1,
 483                 .flags          = IORESOURCE_MEM,
 484         },
 485 };
 486
 487 static struct platform_device ep93xx_rtc_device = {
 488         .name           = "ep93xx-rtc",
 489         .id             = -1,
 490         .num_resources  = ARRAY_SIZE(ep93xx_rtc_resource),
 491         .resource       = ep93xx_rtc_resource,
 492 };
 493
 494
 495 static struct resource ep93xx_ohci_resources[] = {
 496         [0] = {
 497                 .start  = EP93XX_USB_PHYS_BASE,
 498                 .end    = EP93XX_USB_PHYS_BASE + 0x0fff,
 499                 .flags  = IORESOURCE_MEM,
 500         },
 501         [1] = {
 502                 .start  = IRQ_EP93XX_USB,
 503                 .end    = IRQ_EP93XX_USB,
 504                 .flags  = IORESOURCE_IRQ,
 505         },
 506 };
 507
 508
 509 static struct platform_device ep93xx_ohci_device = {
 510         .name           = "ep93xx-ohci",
 511         .id             = -1,
 512         .dev            = {
 513                 .dma_mask               = &ep93xx_ohci_device.dev.coherent_dma_mask,
 514                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 515         },
 516         .num_resources  = ARRAY_SIZE(ep93xx_ohci_resources),
 517         .resource       = ep93xx_ohci_resources,
 518 };
 519
 520 static struct ep93xx_eth_data ep93xx_eth_data;
 521
 522 static struct resource ep93xx_eth_resource[] = {
 523         {
 524                 .start  = EP93XX_ETHERNET_PHYS_BASE,
 525                 .end    = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
 526                 .flags  = IORESOURCE_MEM,
 527         }, {
 528                 .start  = IRQ_EP93XX_ETHERNET,
 529                 .end    = IRQ_EP93XX_ETHERNET,
 530                 .flags  = IORESOURCE_IRQ,
 531         }
 532 };
 533
 534 static struct platform_device ep93xx_eth_device = {
 535         .name           = "ep93xx-eth",
 536         .id             = -1,
 537         .dev            = {
 538                 .platform_data  = &ep93xx_eth_data,
 539         },
 540         .num_resources  = ARRAY_SIZE(ep93xx_eth_resource),
 541         .resource       = ep93xx_eth_resource,
 542 };
 543
 544 void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
 545 {
 546         if (copy_addr)
 547                 memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6);
 548
 549         ep93xx_eth_data = *data;
 550         platform_device_register(&ep93xx_eth_device);
 551 }
 552
 553 static struct i2c_gpio_platform_data ep93xx_i2c_data = {
 554         .sda_pin                = EP93XX_GPIO_LINE_EEDAT,
 555         .sda_is_open_drain      = 0,
 556         .scl_pin                = EP93XX_GPIO_LINE_EECLK,
 557         .scl_is_open_drain      = 0,
 558         .udelay                 = 2,
 559 };
 560
 561 static struct platform_device ep93xx_i2c_device = {
 562         .name                   = "i2c-gpio",
 563         .id                     = 0,
 564         .dev.platform_data      = &ep93xx_i2c_data,
 565 };
 566
 567 void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num)
 568 {
 569         i2c_register_board_info(0, devices, num);
 570         platform_device_register(&ep93xx_i2c_device);
 571 }
 572
 573
 574 /*************************************************************************
 575  * EP93xx LEDs
 576  *************************************************************************/
 577 static struct gpio_led ep93xx_led_pins[] = {
 578         {
 579                 .name                   = "platform:grled",
 580                 .gpio                   = EP93XX_GPIO_LINE_GRLED,
 581         }, {
 582                 .name                   = "platform:rdled",
 583                 .gpio                   = EP93XX_GPIO_LINE_RDLED,
 584         },
 585 };
 586
 587 static struct gpio_led_platform_data ep93xx_led_data = {
 588         .num_leds       = ARRAY_SIZE(ep93xx_led_pins),
 589         .leds           = ep93xx_led_pins,
 590 };
 591
 592 static struct platform_device ep93xx_leds = {
 593         .name           = "leds-gpio",
 594         .id             = -1,
 595         .dev            = {
 596                 .platform_data  = &ep93xx_led_data,
 597         },
 598 };
 599
 600
 601 /*************************************************************************
 602  * EP93xx pwm peripheral handling
 603  *************************************************************************/
 604 static struct resource ep93xx_pwm0_resource[] = {
 605         {
 606                 .start  = EP93XX_PWM_PHYS_BASE,
 607                 .end    = EP93XX_PWM_PHYS_BASE + 0x10 - 1,
 608                 .flags  = IORESOURCE_MEM,
 609         },
 610 };
 611
 612 static struct platform_device ep93xx_pwm0_device = {
 613         .name           = "ep93xx-pwm",
 614         .id             = 0,
 615         .num_resources  = ARRAY_SIZE(ep93xx_pwm0_resource),
 616         .resource       = ep93xx_pwm0_resource,
 617 };
 618
 619 static struct resource ep93xx_pwm1_resource[] = {
 620         {
 621                 .start  = EP93XX_PWM_PHYS_BASE + 0x20,
 622                 .end    = EP93XX_PWM_PHYS_BASE + 0x30 - 1,
 623                 .flags  = IORESOURCE_MEM,
 624         },
 625 };
 626
 627 static struct platform_device ep93xx_pwm1_device = {
 628         .name           = "ep93xx-pwm",
 629         .id             = 1,
 630         .num_resources  = ARRAY_SIZE(ep93xx_pwm1_resource),
 631         .resource       = ep93xx_pwm1_resource,
 632 };
 633
 634 void __init ep93xx_register_pwm(int pwm0, int pwm1)
 635 {
 636         if (pwm0)
 637                 platform_device_register(&ep93xx_pwm0_device);
 638
 639         /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */
 640         if (pwm1)
 641                 platform_device_register(&ep93xx_pwm1_device);
 642 }
 643
 644 int ep93xx_pwm_acquire_gpio(struct platform_device *pdev)
 645 {
 646         int err;
 647
 648         if (pdev->id == 0) {
 649                 err = 0;
 650         } else if (pdev->id == 1) {
 651                 err = gpio_request(EP93XX_GPIO_LINE_EGPIO14,
 652                                    dev_name(&pdev->dev));
 653                 if (err)
 654                         return err;
 655                 err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0);
 656                 if (err)
 657                         goto fail;
 658
 659                 /* PWM 1 output on EGPIO[14] */
 660                 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG);
 661         } else {
 662                 err = -ENODEV;
 663         }
 664
 665         return err;
 666
 667 fail:
 668         gpio_free(EP93XX_GPIO_LINE_EGPIO14);
 669         return err;
 670 }
 671 EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio);
 672
 673 void ep93xx_pwm_release_gpio(struct platform_device *pdev)
 674 {
 675         if (pdev->id == 1) {
 676                 gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14);
 677                 gpio_free(EP93XX_GPIO_LINE_EGPIO14);
 678
 679                 /* EGPIO[14] used for GPIO */
 680                 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG);
 681         }
 682 }
 683 EXPORT_SYMBOL(ep93xx_pwm_release_gpio);
 684
 685
 686 /*************************************************************************
 687  * EP93xx video peripheral handling
 688  *************************************************************************/
 689 static struct ep93xxfb_mach_info ep93xxfb_data;
 690
 691 static struct resource ep93xx_fb_resource[] = {
 692         {
 693                 .start          = EP93XX_RASTER_PHYS_BASE,
 694                 .end            = EP93XX_RASTER_PHYS_BASE + 0x800 - 1,
 695                 .flags          = IORESOURCE_MEM,
 696         },
 697 };
 698
 699 static struct platform_device ep93xx_fb_device = {
 700         .name                   = "ep93xx-fb",
 701         .id                     = -1,
 702         .dev                    = {
 703                 .platform_data  = &ep93xxfb_data,
 704                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 705                 .dma_mask               = &ep93xx_fb_device.dev.coherent_dma_mask,
 706         },
 707         .num_resources          = ARRAY_SIZE(ep93xx_fb_resource),
 708         .resource               = ep93xx_fb_resource,
 709 };
 710
 711 void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
 712 {
 713         ep93xxfb_data = *data;
 714         platform_device_register(&ep93xx_fb_device);
 715 }
 716
 717 extern void ep93xx_gpio_init(void);
 718
 719 void __init ep93xx_init_devices(void)
 720 {
 721         /* Disallow access to MaverickCrunch initially */
 722         ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
 723
 724         ep93xx_gpio_init();
 725
 726         amba_device_register(&uart1_device, &iomem_resource);
 727         amba_device_register(&uart2_device, &iomem_resource);
 728         amba_device_register(&uart3_device, &iomem_resource);
 729
 730         platform_device_register(&ep93xx_rtc_device);
 731         platform_device_register(&ep93xx_ohci_device);
 732         platform_device_register(&ep93xx_leds);
 733 }