arch/arm/mach-davinci/include/mach/mux.h

   1 /*
   2  * Table of the DAVINCI register configurations for the PINMUX combinations
   3  *
   4  * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
   5  *
   6  * Based on linux/include/asm-arm/arch-omap/mux.h:
   7  * Copyright (C) 2003 - 2005 Nokia Corporation
   8  *
   9  * Written by Tony Lindgren
  10  *
  11  * 2007 (c) MontaVista Software, Inc. This file is licensed under
  12  * the terms of the GNU General Public License version 2. This program
  13  * is licensed "as is" without any warranty of any kind, whether express
  14  * or implied.
  15  *
  16  * Copyright (C) 2008 Texas Instruments.
  17  */
  18
  19 #ifndef __INC_MACH_MUX_H
  20 #define __INC_MACH_MUX_H
  21
  22 /* System module registers */
  23 #define PINMUX0                 0x00
  24 #define PINMUX1                 0x04
  25 /* dm355 only */
  26 #define PINMUX2                 0x08
  27 #define PINMUX3                 0x0c
  28 #define PINMUX4                 0x10
  29 #define INTMUX                  0x18
  30 #define EVTMUX                  0x1c
  31
  32 struct mux_config {
  33         const char *name;
  34         const char *mux_reg_name;
  35         const unsigned char mux_reg;
  36         const unsigned char mask_offset;
  37         const unsigned char mask;
  38         const unsigned char mode;
  39         bool debug;
  40 };
  41
  42 enum davinci_dm644x_index {
  43         /* ATA and HDDIR functions */
  44         DM644X_HDIREN,
  45         DM644X_ATAEN,
  46         DM644X_ATAEN_DISABLE,
  47
  48         /* HPI functions */
  49         DM644X_HPIEN_DISABLE,
  50
  51         /* AEAW functions */
  52         DM644X_AEAW,
  53
  54         /* Memory Stick */
  55         DM644X_MSTK,
  56
  57         /* I2C */
  58         DM644X_I2C,
  59
  60         /* ASP function */
  61         DM644X_MCBSP,
  62
  63         /* UART1 */
  64         DM644X_UART1,
  65
  66         /* UART2 */
  67         DM644X_UART2,
  68
  69         /* PWM0 */
  70         DM644X_PWM0,
  71
  72         /* PWM1 */
  73         DM644X_PWM1,
  74
  75         /* PWM2 */
  76         DM644X_PWM2,
  77
  78         /* VLYNQ function */
  79         DM644X_VLYNQEN,
  80         DM644X_VLSCREN,
  81         DM644X_VLYNQWD,
  82
  83         /* EMAC and MDIO function */
  84         DM644X_EMACEN,
  85
  86         /* GPIO3V[0:16] pins */
  87         DM644X_GPIO3V,
  88
  89         /* GPIO pins */
  90         DM644X_GPIO0,
  91         DM644X_GPIO3,
  92         DM644X_GPIO43_44,
  93         DM644X_GPIO46_47,
  94
  95         /* VPBE */
  96         DM644X_RGB666,
  97
  98         /* LCD */
  99         DM644X_LOEEN,
 100         DM644X_LFLDEN,
 101 };
 102
 103 enum davinci_dm646x_index {
 104         /* ATA function */
 105         DM646X_ATAEN,
 106
 107         /* AUDIO Clock */
 108         DM646X_AUDCK1,
 109         DM646X_AUDCK0,
 110
 111         /* CRGEN Control */
 112         DM646X_CRGMUX,
 113
 114         /* VPIF Control */
 115         DM646X_STSOMUX_DISABLE,
 116         DM646X_STSIMUX_DISABLE,
 117         DM646X_PTSOMUX_DISABLE,
 118         DM646X_PTSIMUX_DISABLE,
 119
 120         /* TSIF Control */
 121         DM646X_STSOMUX,
 122         DM646X_STSIMUX,
 123         DM646X_PTSOMUX_PARALLEL,
 124         DM646X_PTSIMUX_PARALLEL,
 125         DM646X_PTSOMUX_SERIAL,
 126         DM646X_PTSIMUX_SERIAL,
 127 };
 128
 129 enum davinci_dm355_index {
 130         /* MMC/SD 0 */
 131         DM355_MMCSD0,
 132
 133         /* MMC/SD 1 */
 134         DM355_SD1_CLK,
 135         DM355_SD1_CMD,
 136         DM355_SD1_DATA3,
 137         DM355_SD1_DATA2,
 138         DM355_SD1_DATA1,
 139         DM355_SD1_DATA0,
 140
 141         /* I2C */
 142         DM355_I2C_SDA,
 143         DM355_I2C_SCL,
 144
 145         /* ASP0 function */
 146         DM355_MCBSP0_BDX,
 147         DM355_MCBSP0_X,
 148         DM355_MCBSP0_BFSX,
 149         DM355_MCBSP0_BDR,
 150         DM355_MCBSP0_R,
 151         DM355_MCBSP0_BFSR,
 152
 153         /* SPI0 */
 154         DM355_SPI0_SDI,
 155         DM355_SPI0_SDENA0,
 156         DM355_SPI0_SDENA1,
 157
 158         /* IRQ muxing */
 159         DM355_INT_EDMA_CC,
 160         DM355_INT_EDMA_TC0_ERR,
 161         DM355_INT_EDMA_TC1_ERR,
 162
 163         /* EDMA event muxing */
 164         DM355_EVT8_ASP1_TX,
 165         DM355_EVT9_ASP1_RX,
 166         DM355_EVT26_MMC0_RX,
 167 };
 168
 169 #ifdef CONFIG_DAVINCI_MUX
 170 /* setup pin muxing */
 171 extern void davinci_mux_init(void);
 172 extern int davinci_mux_register(const struct mux_config *pins,
 173                                 unsigned long size);
 174 extern int davinci_cfg_reg(unsigned long reg_cfg);
 175 #else
 176 /* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
 177 static inline void davinci_mux_init(void) {}
 178 static inline int davinci_mux_register(const struct mux_config *pins,
 179                                        unsigned long size) { return 0; }
 180 static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
 181 #endif
 182
 183 #endif /* __INC_MACH_MUX_H */