arch/arm/mach-davinci/dm646x.c

   1 /*
   2  * TI DaVinci DM644x chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/dma-mapping.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/serial_8250.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/gpio.h>
  17
  18 #include <asm/mach/map.h>
  19
  20 #include <mach/dm646x.h>
  21 #include <mach/cputype.h>
  22 #include <mach/edma.h>
  23 #include <mach/irqs.h>
  24 #include <mach/psc.h>
  25 #include <mach/mux.h>
  26 #include <mach/time.h>
  27 #include <mach/serial.h>
  28 #include <mach/common.h>
  29 #include <mach/asp.h>
  30
  31 #include "clock.h"
  32 #include "mux.h"
  33
  34 #define DAVINCI_VPIF_BASE       (0x01C12000)
  35 #define VDD3P3V_PWDN_OFFSET     (0x48)
  36 #define VSCLKDIS_OFFSET         (0x6C)
  37
  38 #define VDD3P3V_VID_MASK        (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
  39                                         BIT_MASK(0))
  40 #define VSCLKDIS_MASK           (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
  41                                         BIT_MASK(8))
  42
  43 /*
  44  * Device specific clocks
  45  */
  46 #define DM646X_AUX_FREQ         24000000
  47
  48 static struct pll_data pll1_data = {
  49         .num       = 1,
  50         .phys_base = DAVINCI_PLL1_BASE,
  51 };
  52
  53 static struct pll_data pll2_data = {
  54         .num       = 2,
  55         .phys_base = DAVINCI_PLL2_BASE,
  56 };
  57
  58 static struct clk ref_clk = {
  59         .name = "ref_clk",
  60 };
  61
  62 static struct clk aux_clkin = {
  63         .name = "aux_clkin",
  64         .rate = DM646X_AUX_FREQ,
  65 };
  66
  67 static struct clk pll1_clk = {
  68         .name = "pll1",
  69         .parent = &ref_clk,
  70         .pll_data = &pll1_data,
  71         .flags = CLK_PLL,
  72 };
  73
  74 static struct clk pll1_sysclk1 = {
  75         .name = "pll1_sysclk1",
  76         .parent = &pll1_clk,
  77         .flags = CLK_PLL,
  78         .div_reg = PLLDIV1,
  79 };
  80
  81 static struct clk pll1_sysclk2 = {
  82         .name = "pll1_sysclk2",
  83         .parent = &pll1_clk,
  84         .flags = CLK_PLL,
  85         .div_reg = PLLDIV2,
  86 };
  87
  88 static struct clk pll1_sysclk3 = {
  89         .name = "pll1_sysclk3",
  90         .parent = &pll1_clk,
  91         .flags = CLK_PLL,
  92         .div_reg = PLLDIV3,
  93 };
  94
  95 static struct clk pll1_sysclk4 = {
  96         .name = "pll1_sysclk4",
  97         .parent = &pll1_clk,
  98         .flags = CLK_PLL,
  99         .div_reg = PLLDIV4,
 100 };
 101
 102 static struct clk pll1_sysclk5 = {
 103         .name = "pll1_sysclk5",
 104         .parent = &pll1_clk,
 105         .flags = CLK_PLL,
 106         .div_reg = PLLDIV5,
 107 };
 108
 109 static struct clk pll1_sysclk6 = {
 110         .name = "pll1_sysclk6",
 111         .parent = &pll1_clk,
 112         .flags = CLK_PLL,
 113         .div_reg = PLLDIV6,
 114 };
 115
 116 static struct clk pll1_sysclk8 = {
 117         .name = "pll1_sysclk8",
 118         .parent = &pll1_clk,
 119         .flags = CLK_PLL,
 120         .div_reg = PLLDIV8,
 121 };
 122
 123 static struct clk pll1_sysclk9 = {
 124         .name = "pll1_sysclk9",
 125         .parent = &pll1_clk,
 126         .flags = CLK_PLL,
 127         .div_reg = PLLDIV9,
 128 };
 129
 130 static struct clk pll1_sysclkbp = {
 131         .name = "pll1_sysclkbp",
 132         .parent = &pll1_clk,
 133         .flags = CLK_PLL | PRE_PLL,
 134         .div_reg = BPDIV,
 135 };
 136
 137 static struct clk pll1_aux_clk = {
 138         .name = "pll1_aux_clk",
 139         .parent = &pll1_clk,
 140         .flags = CLK_PLL | PRE_PLL,
 141 };
 142
 143 static struct clk pll2_clk = {
 144         .name = "pll2_clk",
 145         .parent = &ref_clk,
 146         .pll_data = &pll2_data,
 147         .flags = CLK_PLL,
 148 };
 149
 150 static struct clk pll2_sysclk1 = {
 151         .name = "pll2_sysclk1",
 152         .parent = &pll2_clk,
 153         .flags = CLK_PLL,
 154         .div_reg = PLLDIV1,
 155 };
 156
 157 static struct clk dsp_clk = {
 158         .name = "dsp",
 159         .parent = &pll1_sysclk1,
 160         .lpsc = DM646X_LPSC_C64X_CPU,
 161         .flags = PSC_DSP,
 162         .usecount = 1,                  /* REVISIT how to disable? */
 163 };
 164
 165 static struct clk arm_clk = {
 166         .name = "arm",
 167         .parent = &pll1_sysclk2,
 168         .lpsc = DM646X_LPSC_ARM,
 169         .flags = ALWAYS_ENABLED,
 170 };
 171
 172 static struct clk edma_cc_clk = {
 173         .name = "edma_cc",
 174         .parent = &pll1_sysclk2,
 175         .lpsc = DM646X_LPSC_TPCC,
 176         .flags = ALWAYS_ENABLED,
 177 };
 178
 179 static struct clk edma_tc0_clk = {
 180         .name = "edma_tc0",
 181         .parent = &pll1_sysclk2,
 182         .lpsc = DM646X_LPSC_TPTC0,
 183         .flags = ALWAYS_ENABLED,
 184 };
 185
 186 static struct clk edma_tc1_clk = {
 187         .name = "edma_tc1",
 188         .parent = &pll1_sysclk2,
 189         .lpsc = DM646X_LPSC_TPTC1,
 190         .flags = ALWAYS_ENABLED,
 191 };
 192
 193 static struct clk edma_tc2_clk = {
 194         .name = "edma_tc2",
 195         .parent = &pll1_sysclk2,
 196         .lpsc = DM646X_LPSC_TPTC2,
 197         .flags = ALWAYS_ENABLED,
 198 };
 199
 200 static struct clk edma_tc3_clk = {
 201         .name = "edma_tc3",
 202         .parent = &pll1_sysclk2,
 203         .lpsc = DM646X_LPSC_TPTC3,
 204         .flags = ALWAYS_ENABLED,
 205 };
 206
 207 static struct clk uart0_clk = {
 208         .name = "uart0",
 209         .parent = &aux_clkin,
 210         .lpsc = DM646X_LPSC_UART0,
 211 };
 212
 213 static struct clk uart1_clk = {
 214         .name = "uart1",
 215         .parent = &aux_clkin,
 216         .lpsc = DM646X_LPSC_UART1,
 217 };
 218
 219 static struct clk uart2_clk = {
 220         .name = "uart2",
 221         .parent = &aux_clkin,
 222         .lpsc = DM646X_LPSC_UART2,
 223 };
 224
 225 static struct clk i2c_clk = {
 226         .name = "I2CCLK",
 227         .parent = &pll1_sysclk3,
 228         .lpsc = DM646X_LPSC_I2C,
 229 };
 230
 231 static struct clk gpio_clk = {
 232         .name = "gpio",
 233         .parent = &pll1_sysclk3,
 234         .lpsc = DM646X_LPSC_GPIO,
 235 };
 236
 237 static struct clk mcasp0_clk = {
 238         .name = "mcasp0",
 239         .parent = &pll1_sysclk3,
 240         .lpsc = DM646X_LPSC_McASP0,
 241 };
 242
 243 static struct clk mcasp1_clk = {
 244         .name = "mcasp1",
 245         .parent = &pll1_sysclk3,
 246         .lpsc = DM646X_LPSC_McASP1,
 247 };
 248
 249 static struct clk aemif_clk = {
 250         .name = "aemif",
 251         .parent = &pll1_sysclk3,
 252         .lpsc = DM646X_LPSC_AEMIF,
 253         .flags = ALWAYS_ENABLED,
 254 };
 255
 256 static struct clk emac_clk = {
 257         .name = "emac",
 258         .parent = &pll1_sysclk3,
 259         .lpsc = DM646X_LPSC_EMAC,
 260 };
 261
 262 static struct clk pwm0_clk = {
 263         .name = "pwm0",
 264         .parent = &pll1_sysclk3,
 265         .lpsc = DM646X_LPSC_PWM0,
 266         .usecount = 1,            /* REVIST: disabling hangs system */
 267 };
 268
 269 static struct clk pwm1_clk = {
 270         .name = "pwm1",
 271         .parent = &pll1_sysclk3,
 272         .lpsc = DM646X_LPSC_PWM1,
 273         .usecount = 1,            /* REVIST: disabling hangs system */
 274 };
 275
 276 static struct clk timer0_clk = {
 277         .name = "timer0",
 278         .parent = &pll1_sysclk3,
 279         .lpsc = DM646X_LPSC_TIMER0,
 280 };
 281
 282 static struct clk timer1_clk = {
 283         .name = "timer1",
 284         .parent = &pll1_sysclk3,
 285         .lpsc = DM646X_LPSC_TIMER1,
 286 };
 287
 288 static struct clk timer2_clk = {
 289         .name = "timer2",
 290         .parent = &pll1_sysclk3,
 291         .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
 292 };
 293
 294
 295 static struct clk ide_clk = {
 296         .name = "ide",
 297         .parent = &pll1_sysclk4,
 298         .lpsc = DAVINCI_LPSC_ATA,
 299 };
 300
 301 static struct clk vpif0_clk = {
 302         .name = "vpif0",
 303         .parent = &ref_clk,
 304         .lpsc = DM646X_LPSC_VPSSMSTR,
 305         .flags = ALWAYS_ENABLED,
 306 };
 307
 308 static struct clk vpif1_clk = {
 309         .name = "vpif1",
 310         .parent = &ref_clk,
 311         .lpsc = DM646X_LPSC_VPSSSLV,
 312         .flags = ALWAYS_ENABLED,
 313 };
 314
 315 static struct clk_lookup dm646x_clks[] = {
 316         CLK(NULL, "ref", &ref_clk),
 317         CLK(NULL, "aux", &aux_clkin),
 318         CLK(NULL, "pll1", &pll1_clk),
 319         CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
 320         CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
 321         CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
 322         CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
 323         CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
 324         CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
 325         CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
 326         CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
 327         CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
 328         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 329         CLK(NULL, "pll2", &pll2_clk),
 330         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 331         CLK(NULL, "dsp", &dsp_clk),
 332         CLK(NULL, "arm", &arm_clk),
 333         CLK(NULL, "edma_cc", &edma_cc_clk),
 334         CLK(NULL, "edma_tc0", &edma_tc0_clk),
 335         CLK(NULL, "edma_tc1", &edma_tc1_clk),
 336         CLK(NULL, "edma_tc2", &edma_tc2_clk),
 337         CLK(NULL, "edma_tc3", &edma_tc3_clk),
 338         CLK(NULL, "uart0", &uart0_clk),
 339         CLK(NULL, "uart1", &uart1_clk),
 340         CLK(NULL, "uart2", &uart2_clk),
 341         CLK("i2c_davinci.1", NULL, &i2c_clk),
 342         CLK(NULL, "gpio", &gpio_clk),
 343         CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
 344         CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
 345         CLK(NULL, "aemif", &aemif_clk),
 346         CLK("davinci_emac.1", NULL, &emac_clk),
 347         CLK(NULL, "pwm0", &pwm0_clk),
 348         CLK(NULL, "pwm1", &pwm1_clk),
 349         CLK(NULL, "timer0", &timer0_clk),
 350         CLK(NULL, "timer1", &timer1_clk),
 351         CLK("watchdog", NULL, &timer2_clk),
 352         CLK("palm_bk3710", NULL, &ide_clk),
 353         CLK(NULL, "vpif0", &vpif0_clk),
 354         CLK(NULL, "vpif1", &vpif1_clk),
 355         CLK(NULL, NULL, NULL),
 356 };
 357
 358 static struct emac_platform_data dm646x_emac_pdata = {
 359         .ctrl_reg_offset        = DM646X_EMAC_CNTRL_OFFSET,
 360         .ctrl_mod_reg_offset    = DM646X_EMAC_CNTRL_MOD_OFFSET,
 361         .ctrl_ram_offset        = DM646X_EMAC_CNTRL_RAM_OFFSET,
 362         .ctrl_ram_size          = DM646X_EMAC_CNTRL_RAM_SIZE,
 363         .version                = EMAC_VERSION_2,
 364 };
 365
 366 static struct resource dm646x_emac_resources[] = {
 367         {
 368                 .start  = DM646X_EMAC_BASE,
 369                 .end    = DM646X_EMAC_BASE + SZ_16K - 1,
 370                 .flags  = IORESOURCE_MEM,
 371         },
 372         {
 373                 .start  = IRQ_DM646X_EMACRXTHINT,
 374                 .end    = IRQ_DM646X_EMACRXTHINT,
 375                 .flags  = IORESOURCE_IRQ,
 376         },
 377         {
 378                 .start  = IRQ_DM646X_EMACRXINT,
 379                 .end    = IRQ_DM646X_EMACRXINT,
 380                 .flags  = IORESOURCE_IRQ,
 381         },
 382         {
 383                 .start  = IRQ_DM646X_EMACTXINT,
 384                 .end    = IRQ_DM646X_EMACTXINT,
 385                 .flags  = IORESOURCE_IRQ,
 386         },
 387         {
 388                 .start  = IRQ_DM646X_EMACMISCINT,
 389                 .end    = IRQ_DM646X_EMACMISCINT,
 390                 .flags  = IORESOURCE_IRQ,
 391         },
 392 };
 393
 394 static struct platform_device dm646x_emac_device = {
 395         .name           = "davinci_emac",
 396         .id             = 1,
 397         .dev = {
 398                 .platform_data  = &dm646x_emac_pdata,
 399         },
 400         .num_resources  = ARRAY_SIZE(dm646x_emac_resources),
 401         .resource       = dm646x_emac_resources,
 402 };
 403
 404 static struct resource dm646x_mdio_resources[] = {
 405         {
 406                 .start  = DM646X_EMAC_MDIO_BASE,
 407                 .end    = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
 408                 .flags  = IORESOURCE_MEM,
 409         },
 410 };
 411
 412 static struct platform_device dm646x_mdio_device = {
 413         .name           = "davinci_mdio",
 414         .id             = 0,
 415         .num_resources  = ARRAY_SIZE(dm646x_mdio_resources),
 416         .resource       = dm646x_mdio_resources,
 417 };
 418
 419 /*
 420  * Device specific mux setup
 421  *
 422  *      soc     description     mux  mode   mode  mux    dbg
 423  *                              reg  offset mask  mode
 424  */
 425 static const struct mux_config dm646x_pins[] = {
 426 #ifdef CONFIG_DAVINCI_MUX
 427 MUX_CFG(DM646X, ATAEN,          0,   0,     5,    1,     true)
 428
 429 MUX_CFG(DM646X, AUDCK1,         0,   29,    1,    0,     false)
 430
 431 MUX_CFG(DM646X, AUDCK0,         0,   28,    1,    0,     false)
 432
 433 MUX_CFG(DM646X, CRGMUX,                 0,   24,    7,    5,     true)
 434
 435 MUX_CFG(DM646X, STSOMUX_DISABLE,        0,   22,    3,    0,     true)
 436
 437 MUX_CFG(DM646X, STSIMUX_DISABLE,        0,   20,    3,    0,     true)
 438
 439 MUX_CFG(DM646X, PTSOMUX_DISABLE,        0,   18,    3,    0,     true)
 440
 441 MUX_CFG(DM646X, PTSIMUX_DISABLE,        0,   16,    3,    0,     true)
 442
 443 MUX_CFG(DM646X, STSOMUX,                0,   22,    3,    2,     true)
 444
 445 MUX_CFG(DM646X, STSIMUX,                0,   20,    3,    2,     true)
 446
 447 MUX_CFG(DM646X, PTSOMUX_PARALLEL,       0,   18,    3,    2,     true)
 448
 449 MUX_CFG(DM646X, PTSIMUX_PARALLEL,       0,   16,    3,    2,     true)
 450
 451 MUX_CFG(DM646X, PTSOMUX_SERIAL,         0,   18,    3,    3,     true)
 452
 453 MUX_CFG(DM646X, PTSIMUX_SERIAL,         0,   16,    3,    3,     true)
 454 #endif
 455 };
 456
 457 static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 458         [IRQ_DM646X_VP_VERTINT0]        = 7,
 459         [IRQ_DM646X_VP_VERTINT1]        = 7,
 460         [IRQ_DM646X_VP_VERTINT2]        = 7,
 461         [IRQ_DM646X_VP_VERTINT3]        = 7,
 462         [IRQ_DM646X_VP_ERRINT]          = 7,
 463         [IRQ_DM646X_RESERVED_1]         = 7,
 464         [IRQ_DM646X_RESERVED_2]         = 7,
 465         [IRQ_DM646X_WDINT]              = 7,
 466         [IRQ_DM646X_CRGENINT0]          = 7,
 467         [IRQ_DM646X_CRGENINT1]          = 7,
 468         [IRQ_DM646X_TSIFINT0]           = 7,
 469         [IRQ_DM646X_TSIFINT1]           = 7,
 470         [IRQ_DM646X_VDCEINT]            = 7,
 471         [IRQ_DM646X_USBINT]             = 7,
 472         [IRQ_DM646X_USBDMAINT]          = 7,
 473         [IRQ_DM646X_PCIINT]             = 7,
 474         [IRQ_CCINT0]                    = 7,    /* dma */
 475         [IRQ_CCERRINT]                  = 7,    /* dma */
 476         [IRQ_TCERRINT0]                 = 7,    /* dma */
 477         [IRQ_TCERRINT]                  = 7,    /* dma */
 478         [IRQ_DM646X_TCERRINT2]          = 7,
 479         [IRQ_DM646X_TCERRINT3]          = 7,
 480         [IRQ_DM646X_IDE]                = 7,
 481         [IRQ_DM646X_HPIINT]             = 7,
 482         [IRQ_DM646X_EMACRXTHINT]        = 7,
 483         [IRQ_DM646X_EMACRXINT]          = 7,
 484         [IRQ_DM646X_EMACTXINT]          = 7,
 485         [IRQ_DM646X_EMACMISCINT]        = 7,
 486         [IRQ_DM646X_MCASP0TXINT]        = 7,
 487         [IRQ_DM646X_MCASP0RXINT]        = 7,
 488         [IRQ_AEMIFINT]                  = 7,
 489         [IRQ_DM646X_RESERVED_3]         = 7,
 490         [IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */
 491         [IRQ_TINT0_TINT34]              = 7,    /* clocksource */
 492         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 493         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 494         [IRQ_PWMINT0]                   = 7,
 495         [IRQ_PWMINT1]                   = 7,
 496         [IRQ_DM646X_VLQINT]             = 7,
 497         [IRQ_I2C]                       = 7,
 498         [IRQ_UARTINT0]                  = 7,
 499         [IRQ_UARTINT1]                  = 7,
 500         [IRQ_DM646X_UARTINT2]           = 7,
 501         [IRQ_DM646X_SPINT0]             = 7,
 502         [IRQ_DM646X_SPINT1]             = 7,
 503         [IRQ_DM646X_DSP2ARMINT]         = 7,
 504         [IRQ_DM646X_RESERVED_4]         = 7,
 505         [IRQ_DM646X_PSCINT]             = 7,
 506         [IRQ_DM646X_GPIO0]              = 7,
 507         [IRQ_DM646X_GPIO1]              = 7,
 508         [IRQ_DM646X_GPIO2]              = 7,
 509         [IRQ_DM646X_GPIO3]              = 7,
 510         [IRQ_DM646X_GPIO4]              = 7,
 511         [IRQ_DM646X_GPIO5]              = 7,
 512         [IRQ_DM646X_GPIO6]              = 7,
 513         [IRQ_DM646X_GPIO7]              = 7,
 514         [IRQ_DM646X_GPIOBNK0]           = 7,
 515         [IRQ_DM646X_GPIOBNK1]           = 7,
 516         [IRQ_DM646X_GPIOBNK2]           = 7,
 517         [IRQ_DM646X_DDRINT]             = 7,
 518         [IRQ_DM646X_AEMIFINT]           = 7,
 519         [IRQ_COMMTX]                    = 7,
 520         [IRQ_COMMRX]                    = 7,
 521         [IRQ_EMUINT]                    = 7,
 522 };
 523
 524 /*----------------------------------------------------------------------*/
 525
 526 /* Four Transfer Controllers on DM646x */
 527 static const s8
 528 dm646x_queue_tc_mapping[][2] = {
 529         /* {event queue no, TC no} */
 530         {0, 0},
 531         {1, 1},
 532         {2, 2},
 533         {3, 3},
 534         {-1, -1},
 535 };
 536
 537 static const s8
 538 dm646x_queue_priority_mapping[][2] = {
 539         /* {event queue no, Priority} */
 540         {0, 4},
 541         {1, 0},
 542         {2, 5},
 543         {3, 1},
 544         {-1, -1},
 545 };
 546
 547 static struct edma_soc_info edma_cc0_info = {
 548         .n_channel              = 64,
 549         .n_region               = 6,    /* 0-1, 4-7 */
 550         .n_slot                 = 512,
 551         .n_tc                   = 4,
 552         .n_cc                   = 1,
 553         .queue_tc_mapping       = dm646x_queue_tc_mapping,
 554         .queue_priority_mapping = dm646x_queue_priority_mapping,
 555 };
 556
 557 static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = {
 558         &edma_cc0_info,
 559 };
 560
 561 static struct resource edma_resources[] = {
 562         {
 563                 .name   = "edma_cc0",
 564                 .start  = 0x01c00000,
 565                 .end    = 0x01c00000 + SZ_64K - 1,
 566                 .flags  = IORESOURCE_MEM,
 567         },
 568         {
 569                 .name   = "edma_tc0",
 570                 .start  = 0x01c10000,
 571                 .end    = 0x01c10000 + SZ_1K - 1,
 572                 .flags  = IORESOURCE_MEM,
 573         },
 574         {
 575                 .name   = "edma_tc1",
 576                 .start  = 0x01c10400,
 577                 .end    = 0x01c10400 + SZ_1K - 1,
 578                 .flags  = IORESOURCE_MEM,
 579         },
 580         {
 581                 .name   = "edma_tc2",
 582                 .start  = 0x01c10800,
 583                 .end    = 0x01c10800 + SZ_1K - 1,
 584                 .flags  = IORESOURCE_MEM,
 585         },
 586         {
 587                 .name   = "edma_tc3",
 588                 .start  = 0x01c10c00,
 589                 .end    = 0x01c10c00 + SZ_1K - 1,
 590                 .flags  = IORESOURCE_MEM,
 591         },
 592         {
 593                 .name   = "edma0",
 594                 .start  = IRQ_CCINT0,
 595                 .flags  = IORESOURCE_IRQ,
 596         },
 597         {
 598                 .name   = "edma0_err",
 599                 .start  = IRQ_CCERRINT,
 600                 .flags  = IORESOURCE_IRQ,
 601         },
 602         /* not using TC*_ERR */
 603 };
 604
 605 static struct platform_device dm646x_edma_device = {
 606         .name                   = "edma",
 607         .id                     = 0,
 608         .dev.platform_data      = dm646x_edma_info,
 609         .num_resources          = ARRAY_SIZE(edma_resources),
 610         .resource               = edma_resources,
 611 };
 612
 613 static struct resource dm646x_mcasp0_resources[] = {
 614         {
 615                 .name   = "mcasp0",
 616                 .start  = DAVINCI_DM646X_MCASP0_REG_BASE,
 617                 .end    = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
 618                 .flags  = IORESOURCE_MEM,
 619         },
 620         /* first TX, then RX */
 621         {
 622                 .start  = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
 623                 .end    = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
 624                 .flags  = IORESOURCE_DMA,
 625         },
 626         {
 627                 .start  = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
 628                 .end    = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
 629                 .flags  = IORESOURCE_DMA,
 630         },
 631 };
 632
 633 static struct resource dm646x_mcasp1_resources[] = {
 634         {
 635                 .name   = "mcasp1",
 636                 .start  = DAVINCI_DM646X_MCASP1_REG_BASE,
 637                 .end    = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
 638                 .flags  = IORESOURCE_MEM,
 639         },
 640         /* DIT mode, only TX event */
 641         {
 642                 .start  = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
 643                 .end    = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
 644                 .flags  = IORESOURCE_DMA,
 645         },
 646         /* DIT mode, dummy entry */
 647         {
 648                 .start  = -1,
 649                 .end    = -1,
 650                 .flags  = IORESOURCE_DMA,
 651         },
 652 };
 653
 654 static struct platform_device dm646x_mcasp0_device = {
 655         .name           = "davinci-mcasp",
 656         .id             = 0,
 657         .num_resources  = ARRAY_SIZE(dm646x_mcasp0_resources),
 658         .resource       = dm646x_mcasp0_resources,
 659 };
 660
 661 static struct platform_device dm646x_mcasp1_device = {
 662         .name           = "davinci-mcasp",
 663         .id             = 1,
 664         .num_resources  = ARRAY_SIZE(dm646x_mcasp1_resources),
 665         .resource       = dm646x_mcasp1_resources,
 666 };
 667
 668 static struct platform_device dm646x_dit_device = {
 669         .name   = "spdif-dit",
 670         .id     = -1,
 671 };
 672
 673 static u64 vpif_dma_mask = DMA_BIT_MASK(32);
 674
 675 static struct resource vpif_resource[] = {
 676         {
 677                 .start  = DAVINCI_VPIF_BASE,
 678                 .end    = DAVINCI_VPIF_BASE + 0x03ff,
 679                 .flags  = IORESOURCE_MEM,
 680         }
 681 };
 682
 683 static struct platform_device vpif_dev = {
 684         .name           = "vpif",
 685         .id             = -1,
 686         .dev            = {
 687                         .dma_mask               = &vpif_dma_mask,
 688                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 689         },
 690         .resource       = vpif_resource,
 691         .num_resources  = ARRAY_SIZE(vpif_resource),
 692 };
 693
 694 static struct resource vpif_display_resource[] = {
 695         {
 696                 .start = IRQ_DM646X_VP_VERTINT2,
 697                 .end   = IRQ_DM646X_VP_VERTINT2,
 698                 .flags = IORESOURCE_IRQ,
 699         },
 700         {
 701                 .start = IRQ_DM646X_VP_VERTINT3,
 702                 .end   = IRQ_DM646X_VP_VERTINT3,
 703                 .flags = IORESOURCE_IRQ,
 704         },
 705 };
 706
 707 static struct platform_device vpif_display_dev = {
 708         .name           = "vpif_display",
 709         .id             = -1,
 710         .dev            = {
 711                         .dma_mask               = &vpif_dma_mask,
 712                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 713         },
 714         .resource       = vpif_display_resource,
 715         .num_resources  = ARRAY_SIZE(vpif_display_resource),
 716 };
 717
 718 static struct resource vpif_capture_resource[] = {
 719         {
 720                 .start = IRQ_DM646X_VP_VERTINT0,
 721                 .end   = IRQ_DM646X_VP_VERTINT0,
 722                 .flags = IORESOURCE_IRQ,
 723         },
 724         {
 725                 .start = IRQ_DM646X_VP_VERTINT1,
 726                 .end   = IRQ_DM646X_VP_VERTINT1,
 727                 .flags = IORESOURCE_IRQ,
 728         },
 729 };
 730
 731 static struct platform_device vpif_capture_dev = {
 732         .name           = "vpif_capture",
 733         .id             = -1,
 734         .dev            = {
 735                         .dma_mask               = &vpif_dma_mask,
 736                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 737         },
 738         .resource       = vpif_capture_resource,
 739         .num_resources  = ARRAY_SIZE(vpif_capture_resource),
 740 };
 741
 742 /*----------------------------------------------------------------------*/
 743
 744 static struct map_desc dm646x_io_desc[] = {
 745         {
 746                 .virtual        = IO_VIRT,
 747                 .pfn            = __phys_to_pfn(IO_PHYS),
 748                 .length         = IO_SIZE,
 749                 .type           = MT_DEVICE
 750         },
 751         {
 752                 .virtual        = SRAM_VIRT,
 753                 .pfn            = __phys_to_pfn(0x00010000),
 754                 .length         = SZ_32K,
 755                 .type           = MT_MEMORY_NONCACHED,
 756         },
 757 };
 758
 759 /* Contents of JTAG ID register used to identify exact cpu type */
 760 static struct davinci_id dm646x_ids[] = {
 761         {
 762                 .variant        = 0x0,
 763                 .part_no        = 0xb770,
 764                 .manufacturer   = 0x017,
 765                 .cpu_id         = DAVINCI_CPU_ID_DM6467,
 766                 .name           = "dm6467_rev1.x",
 767         },
 768         {
 769                 .variant        = 0x1,
 770                 .part_no        = 0xb770,
 771                 .manufacturer   = 0x017,
 772                 .cpu_id         = DAVINCI_CPU_ID_DM6467,
 773                 .name           = "dm6467_rev3.x",
 774         },
 775 };
 776
 777 static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
 778
 779 /*
 780  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 781  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 782  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 783  * T1_TOP: Timer 1, top   :  <unused>
 784  */
 785 static struct davinci_timer_info dm646x_timer_info = {
 786         .timers         = davinci_timer_instance,
 787         .clockevent_id  = T0_BOT,
 788         .clocksource_id = T0_TOP,
 789 };
 790
 791 static struct plat_serial8250_port dm646x_serial_platform_data[] = {
 792         {
 793                 .mapbase        = DAVINCI_UART0_BASE,
 794                 .irq            = IRQ_UARTINT0,
 795                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 796                                   UPF_IOREMAP,
 797                 .iotype         = UPIO_MEM32,
 798                 .regshift       = 2,
 799         },
 800         {
 801                 .mapbase        = DAVINCI_UART1_BASE,
 802                 .irq            = IRQ_UARTINT1,
 803                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 804                                   UPF_IOREMAP,
 805                 .iotype         = UPIO_MEM32,
 806                 .regshift       = 2,
 807         },
 808         {
 809                 .mapbase        = DAVINCI_UART2_BASE,
 810                 .irq            = IRQ_DM646X_UARTINT2,
 811                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 812                                   UPF_IOREMAP,
 813                 .iotype         = UPIO_MEM32,
 814                 .regshift       = 2,
 815         },
 816         {
 817                 .flags          = 0
 818         },
 819 };
 820
 821 static struct platform_device dm646x_serial_device = {
 822         .name                   = "serial8250",
 823         .id                     = PLAT8250_DEV_PLATFORM,
 824         .dev                    = {
 825                 .platform_data  = dm646x_serial_platform_data,
 826         },
 827 };
 828
 829 static struct davinci_soc_info davinci_soc_info_dm646x = {
 830         .io_desc                = dm646x_io_desc,
 831         .io_desc_num            = ARRAY_SIZE(dm646x_io_desc),
 832         .jtag_id_reg            = 0x01c40028,
 833         .ids                    = dm646x_ids,
 834         .ids_num                = ARRAY_SIZE(dm646x_ids),
 835         .cpu_clks               = dm646x_clks,
 836         .psc_bases              = dm646x_psc_bases,
 837         .psc_bases_num          = ARRAY_SIZE(dm646x_psc_bases),
 838         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
 839         .pinmux_pins            = dm646x_pins,
 840         .pinmux_pins_num        = ARRAY_SIZE(dm646x_pins),
 841         .intc_base              = DAVINCI_ARM_INTC_BASE,
 842         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 843         .intc_irq_prios         = dm646x_default_priorities,
 844         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 845         .timer_info             = &dm646x_timer_info,
 846         .gpio_type              = GPIO_TYPE_DAVINCI,
 847         .gpio_base              = DAVINCI_GPIO_BASE,
 848         .gpio_num               = 43, /* Only 33 usable */
 849         .gpio_irq               = IRQ_DM646X_GPIOBNK0,
 850         .serial_dev             = &dm646x_serial_device,
 851         .emac_pdata             = &dm646x_emac_pdata,
 852         .sram_dma               = 0x10010000,
 853         .sram_len               = SZ_32K,
 854         .reset_device           = &davinci_wdt_device,
 855 };
 856
 857 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
 858 {
 859         dm646x_mcasp0_device.dev.platform_data = pdata;
 860         platform_device_register(&dm646x_mcasp0_device);
 861 }
 862
 863 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
 864 {
 865         dm646x_mcasp1_device.dev.platform_data = pdata;
 866         platform_device_register(&dm646x_mcasp1_device);
 867         platform_device_register(&dm646x_dit_device);
 868 }
 869
 870 void dm646x_setup_vpif(struct vpif_display_config *display_config,
 871                        struct vpif_capture_config *capture_config)
 872 {
 873         unsigned int value;
 874         void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
 875
 876         value = __raw_readl(base + VSCLKDIS_OFFSET);
 877         value &= ~VSCLKDIS_MASK;
 878         __raw_writel(value, base + VSCLKDIS_OFFSET);
 879
 880         value = __raw_readl(base + VDD3P3V_PWDN_OFFSET);
 881         value &= ~VDD3P3V_VID_MASK;
 882         __raw_writel(value, base + VDD3P3V_PWDN_OFFSET);
 883
 884         davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
 885         davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
 886         davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
 887         davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
 888
 889         vpif_display_dev.dev.platform_data = display_config;
 890         vpif_capture_dev.dev.platform_data = capture_config;
 891         platform_device_register(&vpif_dev);
 892         platform_device_register(&vpif_display_dev);
 893         platform_device_register(&vpif_capture_dev);
 894 }
 895
 896 int __init dm646x_init_edma(struct edma_rsv_info *rsv)
 897 {
 898         edma_cc0_info.rsv = rsv;
 899
 900         return platform_device_register(&dm646x_edma_device);
 901 }
 902
 903 void __init dm646x_init(void)
 904 {
 905         dm646x_board_setup_refclk(&ref_clk);
 906         davinci_common_init(&davinci_soc_info_dm646x);
 907 }
 908
 909 static int __init dm646x_init_devices(void)
 910 {
 911         if (!cpu_is_davinci_dm646x())
 912                 return 0;
 913
 914         platform_device_register(&dm646x_mdio_device);
 915         platform_device_register(&dm646x_emac_device);
 916         clk_add_alias(NULL, dev_name(&dm646x_mdio_device.dev),
 917                       NULL, &dm646x_emac_device.dev);
 918
 919         return 0;
 920 }
 921 postcore_initcall(dm646x_init_devices);