2 * TI DaVinci DM644x chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/dma-mapping.h>
12 #include <linux/init.h>
13 #include <linux/clk.h>
14 #include <linux/serial_8250.h>
15 #include <linux/platform_device.h>
16 #include <linux/gpio.h>
18 #include <asm/mach/map.h>
20 #include <mach/dm646x.h>
21 #include <mach/cputype.h>
22 #include <mach/edma.h>
23 #include <mach/irqs.h>
26 #include <mach/time.h>
27 #include <mach/serial.h>
28 #include <mach/common.h>
34 #define DAVINCI_VPIF_BASE (0x01C12000)
35 #define VDD3P3V_PWDN_OFFSET (0x48)
36 #define VSCLKDIS_OFFSET (0x6C)
38 #define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
40 #define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
44 * Device specific clocks
46 #define DM646X_AUX_FREQ 24000000
48 static struct pll_data pll1_data = {
50 .phys_base = DAVINCI_PLL1_BASE,
53 static struct pll_data pll2_data = {
55 .phys_base = DAVINCI_PLL2_BASE,
58 static struct clk ref_clk = {
62 static struct clk aux_clkin = {
64 .rate = DM646X_AUX_FREQ,
67 static struct clk pll1_clk = {
70 .pll_data = &pll1_data,
74 static struct clk pll1_sysclk1 = {
75 .name = "pll1_sysclk1",
81 static struct clk pll1_sysclk2 = {
82 .name = "pll1_sysclk2",
88 static struct clk pll1_sysclk3 = {
89 .name = "pll1_sysclk3",
95 static struct clk pll1_sysclk4 = {
96 .name = "pll1_sysclk4",
102 static struct clk pll1_sysclk5 = {
103 .name = "pll1_sysclk5",
109 static struct clk pll1_sysclk6 = {
110 .name = "pll1_sysclk6",
116 static struct clk pll1_sysclk8 = {
117 .name = "pll1_sysclk8",
123 static struct clk pll1_sysclk9 = {
124 .name = "pll1_sysclk9",
130 static struct clk pll1_sysclkbp = {
131 .name = "pll1_sysclkbp",
133 .flags = CLK_PLL | PRE_PLL,
137 static struct clk pll1_aux_clk = {
138 .name = "pll1_aux_clk",
140 .flags = CLK_PLL | PRE_PLL,
143 static struct clk pll2_clk = {
146 .pll_data = &pll2_data,
150 static struct clk pll2_sysclk1 = {
151 .name = "pll2_sysclk1",
157 static struct clk dsp_clk = {
159 .parent = &pll1_sysclk1,
160 .lpsc = DM646X_LPSC_C64X_CPU,
162 .usecount = 1, /* REVISIT how to disable? */
165 static struct clk arm_clk = {
167 .parent = &pll1_sysclk2,
168 .lpsc = DM646X_LPSC_ARM,
169 .flags = ALWAYS_ENABLED,
172 static struct clk edma_cc_clk = {
174 .parent = &pll1_sysclk2,
175 .lpsc = DM646X_LPSC_TPCC,
176 .flags = ALWAYS_ENABLED,
179 static struct clk edma_tc0_clk = {
181 .parent = &pll1_sysclk2,
182 .lpsc = DM646X_LPSC_TPTC0,
183 .flags = ALWAYS_ENABLED,
186 static struct clk edma_tc1_clk = {
188 .parent = &pll1_sysclk2,
189 .lpsc = DM646X_LPSC_TPTC1,
190 .flags = ALWAYS_ENABLED,
193 static struct clk edma_tc2_clk = {
195 .parent = &pll1_sysclk2,
196 .lpsc = DM646X_LPSC_TPTC2,
197 .flags = ALWAYS_ENABLED,
200 static struct clk edma_tc3_clk = {
202 .parent = &pll1_sysclk2,
203 .lpsc = DM646X_LPSC_TPTC3,
204 .flags = ALWAYS_ENABLED,
207 static struct clk uart0_clk = {
209 .parent = &aux_clkin,
210 .lpsc = DM646X_LPSC_UART0,
213 static struct clk uart1_clk = {
215 .parent = &aux_clkin,
216 .lpsc = DM646X_LPSC_UART1,
219 static struct clk uart2_clk = {
221 .parent = &aux_clkin,
222 .lpsc = DM646X_LPSC_UART2,
225 static struct clk i2c_clk = {
227 .parent = &pll1_sysclk3,
228 .lpsc = DM646X_LPSC_I2C,
231 static struct clk gpio_clk = {
233 .parent = &pll1_sysclk3,
234 .lpsc = DM646X_LPSC_GPIO,
237 static struct clk mcasp0_clk = {
239 .parent = &pll1_sysclk3,
240 .lpsc = DM646X_LPSC_McASP0,
243 static struct clk mcasp1_clk = {
245 .parent = &pll1_sysclk3,
246 .lpsc = DM646X_LPSC_McASP1,
249 static struct clk aemif_clk = {
251 .parent = &pll1_sysclk3,
252 .lpsc = DM646X_LPSC_AEMIF,
253 .flags = ALWAYS_ENABLED,
256 static struct clk emac_clk = {
258 .parent = &pll1_sysclk3,
259 .lpsc = DM646X_LPSC_EMAC,
262 static struct clk pwm0_clk = {
264 .parent = &pll1_sysclk3,
265 .lpsc = DM646X_LPSC_PWM0,
266 .usecount = 1, /* REVIST: disabling hangs system */
269 static struct clk pwm1_clk = {
271 .parent = &pll1_sysclk3,
272 .lpsc = DM646X_LPSC_PWM1,
273 .usecount = 1, /* REVIST: disabling hangs system */
276 static struct clk timer0_clk = {
278 .parent = &pll1_sysclk3,
279 .lpsc = DM646X_LPSC_TIMER0,
282 static struct clk timer1_clk = {
284 .parent = &pll1_sysclk3,
285 .lpsc = DM646X_LPSC_TIMER1,
288 static struct clk timer2_clk = {
290 .parent = &pll1_sysclk3,
291 .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
295 static struct clk ide_clk = {
297 .parent = &pll1_sysclk4,
298 .lpsc = DAVINCI_LPSC_ATA,
301 static struct clk vpif0_clk = {
304 .lpsc = DM646X_LPSC_VPSSMSTR,
305 .flags = ALWAYS_ENABLED,
308 static struct clk vpif1_clk = {
311 .lpsc = DM646X_LPSC_VPSSSLV,
312 .flags = ALWAYS_ENABLED,
315 static struct clk_lookup dm646x_clks[] = {
316 CLK(NULL, "ref", &ref_clk),
317 CLK(NULL, "aux", &aux_clkin),
318 CLK(NULL, "pll1", &pll1_clk),
319 CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
320 CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
321 CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
322 CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
323 CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
324 CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
325 CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
326 CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
327 CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
328 CLK(NULL, "pll1_aux", &pll1_aux_clk),
329 CLK(NULL, "pll2", &pll2_clk),
330 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
331 CLK(NULL, "dsp", &dsp_clk),
332 CLK(NULL, "arm", &arm_clk),
333 CLK(NULL, "edma_cc", &edma_cc_clk),
334 CLK(NULL, "edma_tc0", &edma_tc0_clk),
335 CLK(NULL, "edma_tc1", &edma_tc1_clk),
336 CLK(NULL, "edma_tc2", &edma_tc2_clk),
337 CLK(NULL, "edma_tc3", &edma_tc3_clk),
338 CLK(NULL, "uart0", &uart0_clk),
339 CLK(NULL, "uart1", &uart1_clk),
340 CLK(NULL, "uart2", &uart2_clk),
341 CLK("i2c_davinci.1", NULL, &i2c_clk),
342 CLK(NULL, "gpio", &gpio_clk),
343 CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
344 CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
345 CLK(NULL, "aemif", &aemif_clk),
346 CLK("davinci_emac.1", NULL, &emac_clk),
347 CLK(NULL, "pwm0", &pwm0_clk),
348 CLK(NULL, "pwm1", &pwm1_clk),
349 CLK(NULL, "timer0", &timer0_clk),
350 CLK(NULL, "timer1", &timer1_clk),
351 CLK("watchdog", NULL, &timer2_clk),
352 CLK("palm_bk3710", NULL, &ide_clk),
353 CLK(NULL, "vpif0", &vpif0_clk),
354 CLK(NULL, "vpif1", &vpif1_clk),
355 CLK(NULL, NULL, NULL),
358 static struct emac_platform_data dm646x_emac_pdata = {
359 .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
360 .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
361 .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
362 .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
363 .version = EMAC_VERSION_2,
366 static struct resource dm646x_emac_resources[] = {
368 .start = DM646X_EMAC_BASE,
369 .end = DM646X_EMAC_BASE + SZ_16K - 1,
370 .flags = IORESOURCE_MEM,
373 .start = IRQ_DM646X_EMACRXTHINT,
374 .end = IRQ_DM646X_EMACRXTHINT,
375 .flags = IORESOURCE_IRQ,
378 .start = IRQ_DM646X_EMACRXINT,
379 .end = IRQ_DM646X_EMACRXINT,
380 .flags = IORESOURCE_IRQ,
383 .start = IRQ_DM646X_EMACTXINT,
384 .end = IRQ_DM646X_EMACTXINT,
385 .flags = IORESOURCE_IRQ,
388 .start = IRQ_DM646X_EMACMISCINT,
389 .end = IRQ_DM646X_EMACMISCINT,
390 .flags = IORESOURCE_IRQ,
394 static struct platform_device dm646x_emac_device = {
395 .name = "davinci_emac",
398 .platform_data = &dm646x_emac_pdata,
400 .num_resources = ARRAY_SIZE(dm646x_emac_resources),
401 .resource = dm646x_emac_resources,
404 static struct resource dm646x_mdio_resources[] = {
406 .start = DM646X_EMAC_MDIO_BASE,
407 .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
408 .flags = IORESOURCE_MEM,
412 static struct platform_device dm646x_mdio_device = {
413 .name = "davinci_mdio",
415 .num_resources = ARRAY_SIZE(dm646x_mdio_resources),
416 .resource = dm646x_mdio_resources,
420 * Device specific mux setup
422 * soc description mux mode mode mux dbg
423 * reg offset mask mode
425 static const struct mux_config dm646x_pins[] = {
426 #ifdef CONFIG_DAVINCI_MUX
427 MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
429 MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
431 MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
433 MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
435 MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
437 MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
439 MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
441 MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
443 MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
445 MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
447 MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
449 MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
451 MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
453 MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
457 static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
458 [IRQ_DM646X_VP_VERTINT0] = 7,
459 [IRQ_DM646X_VP_VERTINT1] = 7,
460 [IRQ_DM646X_VP_VERTINT2] = 7,
461 [IRQ_DM646X_VP_VERTINT3] = 7,
462 [IRQ_DM646X_VP_ERRINT] = 7,
463 [IRQ_DM646X_RESERVED_1] = 7,
464 [IRQ_DM646X_RESERVED_2] = 7,
465 [IRQ_DM646X_WDINT] = 7,
466 [IRQ_DM646X_CRGENINT0] = 7,
467 [IRQ_DM646X_CRGENINT1] = 7,
468 [IRQ_DM646X_TSIFINT0] = 7,
469 [IRQ_DM646X_TSIFINT1] = 7,
470 [IRQ_DM646X_VDCEINT] = 7,
471 [IRQ_DM646X_USBINT] = 7,
472 [IRQ_DM646X_USBDMAINT] = 7,
473 [IRQ_DM646X_PCIINT] = 7,
474 [IRQ_CCINT0] = 7, /* dma */
475 [IRQ_CCERRINT] = 7, /* dma */
476 [IRQ_TCERRINT0] = 7, /* dma */
477 [IRQ_TCERRINT] = 7, /* dma */
478 [IRQ_DM646X_TCERRINT2] = 7,
479 [IRQ_DM646X_TCERRINT3] = 7,
480 [IRQ_DM646X_IDE] = 7,
481 [IRQ_DM646X_HPIINT] = 7,
482 [IRQ_DM646X_EMACRXTHINT] = 7,
483 [IRQ_DM646X_EMACRXINT] = 7,
484 [IRQ_DM646X_EMACTXINT] = 7,
485 [IRQ_DM646X_EMACMISCINT] = 7,
486 [IRQ_DM646X_MCASP0TXINT] = 7,
487 [IRQ_DM646X_MCASP0RXINT] = 7,
489 [IRQ_DM646X_RESERVED_3] = 7,
490 [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
491 [IRQ_TINT0_TINT34] = 7, /* clocksource */
492 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
493 [IRQ_TINT1_TINT34] = 7, /* system tick */
496 [IRQ_DM646X_VLQINT] = 7,
500 [IRQ_DM646X_UARTINT2] = 7,
501 [IRQ_DM646X_SPINT0] = 7,
502 [IRQ_DM646X_SPINT1] = 7,
503 [IRQ_DM646X_DSP2ARMINT] = 7,
504 [IRQ_DM646X_RESERVED_4] = 7,
505 [IRQ_DM646X_PSCINT] = 7,
506 [IRQ_DM646X_GPIO0] = 7,
507 [IRQ_DM646X_GPIO1] = 7,
508 [IRQ_DM646X_GPIO2] = 7,
509 [IRQ_DM646X_GPIO3] = 7,
510 [IRQ_DM646X_GPIO4] = 7,
511 [IRQ_DM646X_GPIO5] = 7,
512 [IRQ_DM646X_GPIO6] = 7,
513 [IRQ_DM646X_GPIO7] = 7,
514 [IRQ_DM646X_GPIOBNK0] = 7,
515 [IRQ_DM646X_GPIOBNK1] = 7,
516 [IRQ_DM646X_GPIOBNK2] = 7,
517 [IRQ_DM646X_DDRINT] = 7,
518 [IRQ_DM646X_AEMIFINT] = 7,
524 /*----------------------------------------------------------------------*/
526 /* Four Transfer Controllers on DM646x */
528 dm646x_queue_tc_mapping[][2] = {
529 /* {event queue no, TC no} */
538 dm646x_queue_priority_mapping[][2] = {
539 /* {event queue no, Priority} */
547 static struct edma_soc_info edma_cc0_info = {
549 .n_region = 6, /* 0-1, 4-7 */
553 .queue_tc_mapping = dm646x_queue_tc_mapping,
554 .queue_priority_mapping = dm646x_queue_priority_mapping,
557 static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = {
561 static struct resource edma_resources[] = {
565 .end = 0x01c00000 + SZ_64K - 1,
566 .flags = IORESOURCE_MEM,
571 .end = 0x01c10000 + SZ_1K - 1,
572 .flags = IORESOURCE_MEM,
577 .end = 0x01c10400 + SZ_1K - 1,
578 .flags = IORESOURCE_MEM,
583 .end = 0x01c10800 + SZ_1K - 1,
584 .flags = IORESOURCE_MEM,
589 .end = 0x01c10c00 + SZ_1K - 1,
590 .flags = IORESOURCE_MEM,
595 .flags = IORESOURCE_IRQ,
599 .start = IRQ_CCERRINT,
600 .flags = IORESOURCE_IRQ,
602 /* not using TC*_ERR */
605 static struct platform_device dm646x_edma_device = {
608 .dev.platform_data = dm646x_edma_info,
609 .num_resources = ARRAY_SIZE(edma_resources),
610 .resource = edma_resources,
613 static struct resource dm646x_mcasp0_resources[] = {
616 .start = DAVINCI_DM646X_MCASP0_REG_BASE,
617 .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
618 .flags = IORESOURCE_MEM,
620 /* first TX, then RX */
622 .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
623 .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
624 .flags = IORESOURCE_DMA,
627 .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
628 .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
629 .flags = IORESOURCE_DMA,
633 static struct resource dm646x_mcasp1_resources[] = {
636 .start = DAVINCI_DM646X_MCASP1_REG_BASE,
637 .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
638 .flags = IORESOURCE_MEM,
640 /* DIT mode, only TX event */
642 .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
643 .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
644 .flags = IORESOURCE_DMA,
646 /* DIT mode, dummy entry */
650 .flags = IORESOURCE_DMA,
654 static struct platform_device dm646x_mcasp0_device = {
655 .name = "davinci-mcasp",
657 .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources),
658 .resource = dm646x_mcasp0_resources,
661 static struct platform_device dm646x_mcasp1_device = {
662 .name = "davinci-mcasp",
664 .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources),
665 .resource = dm646x_mcasp1_resources,
668 static struct platform_device dm646x_dit_device = {
673 static u64 vpif_dma_mask = DMA_BIT_MASK(32);
675 static struct resource vpif_resource[] = {
677 .start = DAVINCI_VPIF_BASE,
678 .end = DAVINCI_VPIF_BASE + 0x03ff,
679 .flags = IORESOURCE_MEM,
683 static struct platform_device vpif_dev = {
687 .dma_mask = &vpif_dma_mask,
688 .coherent_dma_mask = DMA_BIT_MASK(32),
690 .resource = vpif_resource,
691 .num_resources = ARRAY_SIZE(vpif_resource),
694 static struct resource vpif_display_resource[] = {
696 .start = IRQ_DM646X_VP_VERTINT2,
697 .end = IRQ_DM646X_VP_VERTINT2,
698 .flags = IORESOURCE_IRQ,
701 .start = IRQ_DM646X_VP_VERTINT3,
702 .end = IRQ_DM646X_VP_VERTINT3,
703 .flags = IORESOURCE_IRQ,
707 static struct platform_device vpif_display_dev = {
708 .name = "vpif_display",
711 .dma_mask = &vpif_dma_mask,
712 .coherent_dma_mask = DMA_BIT_MASK(32),
714 .resource = vpif_display_resource,
715 .num_resources = ARRAY_SIZE(vpif_display_resource),
718 static struct resource vpif_capture_resource[] = {
720 .start = IRQ_DM646X_VP_VERTINT0,
721 .end = IRQ_DM646X_VP_VERTINT0,
722 .flags = IORESOURCE_IRQ,
725 .start = IRQ_DM646X_VP_VERTINT1,
726 .end = IRQ_DM646X_VP_VERTINT1,
727 .flags = IORESOURCE_IRQ,
731 static struct platform_device vpif_capture_dev = {
732 .name = "vpif_capture",
735 .dma_mask = &vpif_dma_mask,
736 .coherent_dma_mask = DMA_BIT_MASK(32),
738 .resource = vpif_capture_resource,
739 .num_resources = ARRAY_SIZE(vpif_capture_resource),
742 /*----------------------------------------------------------------------*/
744 static struct map_desc dm646x_io_desc[] = {
747 .pfn = __phys_to_pfn(IO_PHYS),
752 .virtual = SRAM_VIRT,
753 .pfn = __phys_to_pfn(0x00010000),
755 .type = MT_MEMORY_NONCACHED,
759 /* Contents of JTAG ID register used to identify exact cpu type */
760 static struct davinci_id dm646x_ids[] = {
764 .manufacturer = 0x017,
765 .cpu_id = DAVINCI_CPU_ID_DM6467,
766 .name = "dm6467_rev1.x",
771 .manufacturer = 0x017,
772 .cpu_id = DAVINCI_CPU_ID_DM6467,
773 .name = "dm6467_rev3.x",
777 static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
780 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
781 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
782 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
783 * T1_TOP: Timer 1, top : <unused>
785 static struct davinci_timer_info dm646x_timer_info = {
786 .timers = davinci_timer_instance,
787 .clockevent_id = T0_BOT,
788 .clocksource_id = T0_TOP,
791 static struct plat_serial8250_port dm646x_serial_platform_data[] = {
793 .mapbase = DAVINCI_UART0_BASE,
795 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
797 .iotype = UPIO_MEM32,
801 .mapbase = DAVINCI_UART1_BASE,
803 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
805 .iotype = UPIO_MEM32,
809 .mapbase = DAVINCI_UART2_BASE,
810 .irq = IRQ_DM646X_UARTINT2,
811 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
813 .iotype = UPIO_MEM32,
821 static struct platform_device dm646x_serial_device = {
822 .name = "serial8250",
823 .id = PLAT8250_DEV_PLATFORM,
825 .platform_data = dm646x_serial_platform_data,
829 static struct davinci_soc_info davinci_soc_info_dm646x = {
830 .io_desc = dm646x_io_desc,
831 .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
832 .jtag_id_reg = 0x01c40028,
834 .ids_num = ARRAY_SIZE(dm646x_ids),
835 .cpu_clks = dm646x_clks,
836 .psc_bases = dm646x_psc_bases,
837 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
838 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
839 .pinmux_pins = dm646x_pins,
840 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
841 .intc_base = DAVINCI_ARM_INTC_BASE,
842 .intc_type = DAVINCI_INTC_TYPE_AINTC,
843 .intc_irq_prios = dm646x_default_priorities,
844 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
845 .timer_info = &dm646x_timer_info,
846 .gpio_type = GPIO_TYPE_DAVINCI,
847 .gpio_base = DAVINCI_GPIO_BASE,
848 .gpio_num = 43, /* Only 33 usable */
849 .gpio_irq = IRQ_DM646X_GPIOBNK0,
850 .serial_dev = &dm646x_serial_device,
851 .emac_pdata = &dm646x_emac_pdata,
852 .sram_dma = 0x10010000,
854 .reset_device = &davinci_wdt_device,
857 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
859 dm646x_mcasp0_device.dev.platform_data = pdata;
860 platform_device_register(&dm646x_mcasp0_device);
863 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
865 dm646x_mcasp1_device.dev.platform_data = pdata;
866 platform_device_register(&dm646x_mcasp1_device);
867 platform_device_register(&dm646x_dit_device);
870 void dm646x_setup_vpif(struct vpif_display_config *display_config,
871 struct vpif_capture_config *capture_config)
874 void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
876 value = __raw_readl(base + VSCLKDIS_OFFSET);
877 value &= ~VSCLKDIS_MASK;
878 __raw_writel(value, base + VSCLKDIS_OFFSET);
880 value = __raw_readl(base + VDD3P3V_PWDN_OFFSET);
881 value &= ~VDD3P3V_VID_MASK;
882 __raw_writel(value, base + VDD3P3V_PWDN_OFFSET);
884 davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
885 davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
886 davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
887 davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
889 vpif_display_dev.dev.platform_data = display_config;
890 vpif_capture_dev.dev.platform_data = capture_config;
891 platform_device_register(&vpif_dev);
892 platform_device_register(&vpif_display_dev);
893 platform_device_register(&vpif_capture_dev);
896 int __init dm646x_init_edma(struct edma_rsv_info *rsv)
898 edma_cc0_info.rsv = rsv;
900 return platform_device_register(&dm646x_edma_device);
903 void __init dm646x_init(void)
905 dm646x_board_setup_refclk(&ref_clk);
906 davinci_common_init(&davinci_soc_info_dm646x);
909 static int __init dm646x_init_devices(void)
911 if (!cpu_is_davinci_dm646x())
914 platform_device_register(&dm646x_mdio_device);
915 platform_device_register(&dm646x_emac_device);
916 clk_add_alias(NULL, dev_name(&dm646x_mdio_device.dev),
917 NULL, &dm646x_emac_device.dev);
921 postcore_initcall(dm646x_init_devices);