arch/arm/mach-davinci/dm646x.c

   1 /*
   2  * TI DaVinci DM644x chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/clk.h>
  13 #include <linux/serial_8250.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/gpio.h>
  16
  17 #include <asm/mach/map.h>
  18
  19 #include <mach/dm646x.h>
  20 #include <mach/cputype.h>
  21 #include <mach/edma.h>
  22 #include <mach/irqs.h>
  23 #include <mach/psc.h>
  24 #include <mach/mux.h>
  25 #include <mach/time.h>
  26 #include <mach/serial.h>
  27 #include <mach/common.h>
  28 #include <mach/asp.h>
  29
  30 #include "clock.h"
  31 #include "mux.h"
  32
  33 #define DAVINCI_VPIF_BASE       (0x01C12000)
  34 #define VDD3P3V_PWDN_OFFSET     (0x48)
  35 #define VSCLKDIS_OFFSET         (0x6C)
  36
  37 #define VDD3P3V_VID_MASK        (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
  38                                         BIT_MASK(0))
  39 #define VSCLKDIS_MASK           (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
  40                                         BIT_MASK(8))
  41
  42 /*
  43  * Device specific clocks
  44  */
  45 #define DM646X_REF_FREQ         27000000
  46 #define DM646X_AUX_FREQ         24000000
  47
  48 static struct pll_data pll1_data = {
  49         .num       = 1,
  50         .phys_base = DAVINCI_PLL1_BASE,
  51 };
  52
  53 static struct pll_data pll2_data = {
  54         .num       = 2,
  55         .phys_base = DAVINCI_PLL2_BASE,
  56 };
  57
  58 static struct clk ref_clk = {
  59         .name = "ref_clk",
  60         .rate = DM646X_REF_FREQ,
  61 };
  62
  63 static struct clk aux_clkin = {
  64         .name = "aux_clkin",
  65         .rate = DM646X_AUX_FREQ,
  66 };
  67
  68 static struct clk pll1_clk = {
  69         .name = "pll1",
  70         .parent = &ref_clk,
  71         .pll_data = &pll1_data,
  72         .flags = CLK_PLL,
  73 };
  74
  75 static struct clk pll1_sysclk1 = {
  76         .name = "pll1_sysclk1",
  77         .parent = &pll1_clk,
  78         .flags = CLK_PLL,
  79         .div_reg = PLLDIV1,
  80 };
  81
  82 static struct clk pll1_sysclk2 = {
  83         .name = "pll1_sysclk2",
  84         .parent = &pll1_clk,
  85         .flags = CLK_PLL,
  86         .div_reg = PLLDIV2,
  87 };
  88
  89 static struct clk pll1_sysclk3 = {
  90         .name = "pll1_sysclk3",
  91         .parent = &pll1_clk,
  92         .flags = CLK_PLL,
  93         .div_reg = PLLDIV3,
  94 };
  95
  96 static struct clk pll1_sysclk4 = {
  97         .name = "pll1_sysclk4",
  98         .parent = &pll1_clk,
  99         .flags = CLK_PLL,
 100         .div_reg = PLLDIV4,
 101 };
 102
 103 static struct clk pll1_sysclk5 = {
 104         .name = "pll1_sysclk5",
 105         .parent = &pll1_clk,
 106         .flags = CLK_PLL,
 107         .div_reg = PLLDIV5,
 108 };
 109
 110 static struct clk pll1_sysclk6 = {
 111         .name = "pll1_sysclk6",
 112         .parent = &pll1_clk,
 113         .flags = CLK_PLL,
 114         .div_reg = PLLDIV6,
 115 };
 116
 117 static struct clk pll1_sysclk8 = {
 118         .name = "pll1_sysclk8",
 119         .parent = &pll1_clk,
 120         .flags = CLK_PLL,
 121         .div_reg = PLLDIV8,
 122 };
 123
 124 static struct clk pll1_sysclk9 = {
 125         .name = "pll1_sysclk9",
 126         .parent = &pll1_clk,
 127         .flags = CLK_PLL,
 128         .div_reg = PLLDIV9,
 129 };
 130
 131 static struct clk pll1_sysclkbp = {
 132         .name = "pll1_sysclkbp",
 133         .parent = &pll1_clk,
 134         .flags = CLK_PLL | PRE_PLL,
 135         .div_reg = BPDIV,
 136 };
 137
 138 static struct clk pll1_aux_clk = {
 139         .name = "pll1_aux_clk",
 140         .parent = &pll1_clk,
 141         .flags = CLK_PLL | PRE_PLL,
 142 };
 143
 144 static struct clk pll2_clk = {
 145         .name = "pll2_clk",
 146         .parent = &ref_clk,
 147         .pll_data = &pll2_data,
 148         .flags = CLK_PLL,
 149 };
 150
 151 static struct clk pll2_sysclk1 = {
 152         .name = "pll2_sysclk1",
 153         .parent = &pll2_clk,
 154         .flags = CLK_PLL,
 155         .div_reg = PLLDIV1,
 156 };
 157
 158 static struct clk dsp_clk = {
 159         .name = "dsp",
 160         .parent = &pll1_sysclk1,
 161         .lpsc = DM646X_LPSC_C64X_CPU,
 162         .flags = PSC_DSP,
 163         .usecount = 1,                  /* REVISIT how to disable? */
 164 };
 165
 166 static struct clk arm_clk = {
 167         .name = "arm",
 168         .parent = &pll1_sysclk2,
 169         .lpsc = DM646X_LPSC_ARM,
 170         .flags = ALWAYS_ENABLED,
 171 };
 172
 173 static struct clk edma_cc_clk = {
 174         .name = "edma_cc",
 175         .parent = &pll1_sysclk2,
 176         .lpsc = DM646X_LPSC_TPCC,
 177         .flags = ALWAYS_ENABLED,
 178 };
 179
 180 static struct clk edma_tc0_clk = {
 181         .name = "edma_tc0",
 182         .parent = &pll1_sysclk2,
 183         .lpsc = DM646X_LPSC_TPTC0,
 184         .flags = ALWAYS_ENABLED,
 185 };
 186
 187 static struct clk edma_tc1_clk = {
 188         .name = "edma_tc1",
 189         .parent = &pll1_sysclk2,
 190         .lpsc = DM646X_LPSC_TPTC1,
 191         .flags = ALWAYS_ENABLED,
 192 };
 193
 194 static struct clk edma_tc2_clk = {
 195         .name = "edma_tc2",
 196         .parent = &pll1_sysclk2,
 197         .lpsc = DM646X_LPSC_TPTC2,
 198         .flags = ALWAYS_ENABLED,
 199 };
 200
 201 static struct clk edma_tc3_clk = {
 202         .name = "edma_tc3",
 203         .parent = &pll1_sysclk2,
 204         .lpsc = DM646X_LPSC_TPTC3,
 205         .flags = ALWAYS_ENABLED,
 206 };
 207
 208 static struct clk uart0_clk = {
 209         .name = "uart0",
 210         .parent = &aux_clkin,
 211         .lpsc = DM646X_LPSC_UART0,
 212 };
 213
 214 static struct clk uart1_clk = {
 215         .name = "uart1",
 216         .parent = &aux_clkin,
 217         .lpsc = DM646X_LPSC_UART1,
 218 };
 219
 220 static struct clk uart2_clk = {
 221         .name = "uart2",
 222         .parent = &aux_clkin,
 223         .lpsc = DM646X_LPSC_UART2,
 224 };
 225
 226 static struct clk i2c_clk = {
 227         .name = "I2CCLK",
 228         .parent = &pll1_sysclk3,
 229         .lpsc = DM646X_LPSC_I2C,
 230 };
 231
 232 static struct clk gpio_clk = {
 233         .name = "gpio",
 234         .parent = &pll1_sysclk3,
 235         .lpsc = DM646X_LPSC_GPIO,
 236 };
 237
 238 static struct clk mcasp0_clk = {
 239         .name = "mcasp0",
 240         .parent = &pll1_sysclk3,
 241         .lpsc = DM646X_LPSC_McASP0,
 242 };
 243
 244 static struct clk mcasp1_clk = {
 245         .name = "mcasp1",
 246         .parent = &pll1_sysclk3,
 247         .lpsc = DM646X_LPSC_McASP1,
 248 };
 249
 250 static struct clk aemif_clk = {
 251         .name = "aemif",
 252         .parent = &pll1_sysclk3,
 253         .lpsc = DM646X_LPSC_AEMIF,
 254         .flags = ALWAYS_ENABLED,
 255 };
 256
 257 static struct clk emac_clk = {
 258         .name = "emac",
 259         .parent = &pll1_sysclk3,
 260         .lpsc = DM646X_LPSC_EMAC,
 261 };
 262
 263 static struct clk pwm0_clk = {
 264         .name = "pwm0",
 265         .parent = &pll1_sysclk3,
 266         .lpsc = DM646X_LPSC_PWM0,
 267         .usecount = 1,            /* REVIST: disabling hangs system */
 268 };
 269
 270 static struct clk pwm1_clk = {
 271         .name = "pwm1",
 272         .parent = &pll1_sysclk3,
 273         .lpsc = DM646X_LPSC_PWM1,
 274         .usecount = 1,            /* REVIST: disabling hangs system */
 275 };
 276
 277 static struct clk timer0_clk = {
 278         .name = "timer0",
 279         .parent = &pll1_sysclk3,
 280         .lpsc = DM646X_LPSC_TIMER0,
 281 };
 282
 283 static struct clk timer1_clk = {
 284         .name = "timer1",
 285         .parent = &pll1_sysclk3,
 286         .lpsc = DM646X_LPSC_TIMER1,
 287 };
 288
 289 static struct clk timer2_clk = {
 290         .name = "timer2",
 291         .parent = &pll1_sysclk3,
 292         .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
 293 };
 294
 295
 296 static struct clk ide_clk = {
 297         .name = "ide",
 298         .parent = &pll1_sysclk4,
 299         .lpsc = DAVINCI_LPSC_ATA,
 300 };
 301
 302 static struct clk vpif0_clk = {
 303         .name = "vpif0",
 304         .parent = &ref_clk,
 305         .lpsc = DM646X_LPSC_VPSSMSTR,
 306         .flags = ALWAYS_ENABLED,
 307 };
 308
 309 static struct clk vpif1_clk = {
 310         .name = "vpif1",
 311         .parent = &ref_clk,
 312         .lpsc = DM646X_LPSC_VPSSSLV,
 313         .flags = ALWAYS_ENABLED,
 314 };
 315
 316 struct davinci_clk dm646x_clks[] = {
 317         CLK(NULL, "ref", &ref_clk),
 318         CLK(NULL, "aux", &aux_clkin),
 319         CLK(NULL, "pll1", &pll1_clk),
 320         CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
 321         CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
 322         CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
 323         CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
 324         CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
 325         CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
 326         CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
 327         CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
 328         CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
 329         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 330         CLK(NULL, "pll2", &pll2_clk),
 331         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 332         CLK(NULL, "dsp", &dsp_clk),
 333         CLK(NULL, "arm", &arm_clk),
 334         CLK(NULL, "edma_cc", &edma_cc_clk),
 335         CLK(NULL, "edma_tc0", &edma_tc0_clk),
 336         CLK(NULL, "edma_tc1", &edma_tc1_clk),
 337         CLK(NULL, "edma_tc2", &edma_tc2_clk),
 338         CLK(NULL, "edma_tc3", &edma_tc3_clk),
 339         CLK(NULL, "uart0", &uart0_clk),
 340         CLK(NULL, "uart1", &uart1_clk),
 341         CLK(NULL, "uart2", &uart2_clk),
 342         CLK("i2c_davinci.1", NULL, &i2c_clk),
 343         CLK(NULL, "gpio", &gpio_clk),
 344         CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
 345         CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
 346         CLK(NULL, "aemif", &aemif_clk),
 347         CLK("davinci_emac.1", NULL, &emac_clk),
 348         CLK(NULL, "pwm0", &pwm0_clk),
 349         CLK(NULL, "pwm1", &pwm1_clk),
 350         CLK(NULL, "timer0", &timer0_clk),
 351         CLK(NULL, "timer1", &timer1_clk),
 352         CLK("watchdog", NULL, &timer2_clk),
 353         CLK("palm_bk3710", NULL, &ide_clk),
 354         CLK(NULL, "vpif0", &vpif0_clk),
 355         CLK(NULL, "vpif1", &vpif1_clk),
 356         CLK(NULL, NULL, NULL),
 357 };
 358
 359 static struct emac_platform_data dm646x_emac_pdata = {
 360         .ctrl_reg_offset        = DM646X_EMAC_CNTRL_OFFSET,
 361         .ctrl_mod_reg_offset    = DM646X_EMAC_CNTRL_MOD_OFFSET,
 362         .ctrl_ram_offset        = DM646X_EMAC_CNTRL_RAM_OFFSET,
 363         .mdio_reg_offset        = DM646X_EMAC_MDIO_OFFSET,
 364         .ctrl_ram_size          = DM646X_EMAC_CNTRL_RAM_SIZE,
 365         .version                = EMAC_VERSION_2,
 366 };
 367
 368 static struct resource dm646x_emac_resources[] = {
 369         {
 370                 .start  = DM646X_EMAC_BASE,
 371                 .end    = DM646X_EMAC_BASE + 0x47ff,
 372                 .flags  = IORESOURCE_MEM,
 373         },
 374         {
 375                 .start  = IRQ_DM646X_EMACRXTHINT,
 376                 .end    = IRQ_DM646X_EMACRXTHINT,
 377                 .flags  = IORESOURCE_IRQ,
 378         },
 379         {
 380                 .start  = IRQ_DM646X_EMACRXINT,
 381                 .end    = IRQ_DM646X_EMACRXINT,
 382                 .flags  = IORESOURCE_IRQ,
 383         },
 384         {
 385                 .start  = IRQ_DM646X_EMACTXINT,
 386                 .end    = IRQ_DM646X_EMACTXINT,
 387                 .flags  = IORESOURCE_IRQ,
 388         },
 389         {
 390                 .start  = IRQ_DM646X_EMACMISCINT,
 391                 .end    = IRQ_DM646X_EMACMISCINT,
 392                 .flags  = IORESOURCE_IRQ,
 393         },
 394 };
 395
 396 static struct platform_device dm646x_emac_device = {
 397         .name           = "davinci_emac",
 398         .id             = 1,
 399         .dev = {
 400                 .platform_data  = &dm646x_emac_pdata,
 401         },
 402         .num_resources  = ARRAY_SIZE(dm646x_emac_resources),
 403         .resource       = dm646x_emac_resources,
 404 };
 405
 406 #define PINMUX0         0x00
 407 #define PINMUX1         0x04
 408
 409 /*
 410  * Device specific mux setup
 411  *
 412  *      soc     description     mux  mode   mode  mux    dbg
 413  *                              reg  offset mask  mode
 414  */
 415 static const struct mux_config dm646x_pins[] = {
 416 #ifdef CONFIG_DAVINCI_MUX
 417 MUX_CFG(DM646X, ATAEN,          0,   0,     5,    1,     true)
 418
 419 MUX_CFG(DM646X, AUDCK1,         0,   29,    1,    0,     false)
 420
 421 MUX_CFG(DM646X, AUDCK0,         0,   28,    1,    0,     false)
 422
 423 MUX_CFG(DM646X, CRGMUX,                 0,   24,    7,    5,     true)
 424
 425 MUX_CFG(DM646X, STSOMUX_DISABLE,        0,   22,    3,    0,     true)
 426
 427 MUX_CFG(DM646X, STSIMUX_DISABLE,        0,   20,    3,    0,     true)
 428
 429 MUX_CFG(DM646X, PTSOMUX_DISABLE,        0,   18,    3,    0,     true)
 430
 431 MUX_CFG(DM646X, PTSIMUX_DISABLE,        0,   16,    3,    0,     true)
 432
 433 MUX_CFG(DM646X, STSOMUX,                0,   22,    3,    2,     true)
 434
 435 MUX_CFG(DM646X, STSIMUX,                0,   20,    3,    2,     true)
 436
 437 MUX_CFG(DM646X, PTSOMUX_PARALLEL,       0,   18,    3,    2,     true)
 438
 439 MUX_CFG(DM646X, PTSIMUX_PARALLEL,       0,   16,    3,    2,     true)
 440
 441 MUX_CFG(DM646X, PTSOMUX_SERIAL,         0,   18,    3,    3,     true)
 442
 443 MUX_CFG(DM646X, PTSIMUX_SERIAL,         0,   16,    3,    3,     true)
 444 #endif
 445 };
 446
 447 static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 448         [IRQ_DM646X_VP_VERTINT0]        = 7,
 449         [IRQ_DM646X_VP_VERTINT1]        = 7,
 450         [IRQ_DM646X_VP_VERTINT2]        = 7,
 451         [IRQ_DM646X_VP_VERTINT3]        = 7,
 452         [IRQ_DM646X_VP_ERRINT]          = 7,
 453         [IRQ_DM646X_RESERVED_1]         = 7,
 454         [IRQ_DM646X_RESERVED_2]         = 7,
 455         [IRQ_DM646X_WDINT]              = 7,
 456         [IRQ_DM646X_CRGENINT0]          = 7,
 457         [IRQ_DM646X_CRGENINT1]          = 7,
 458         [IRQ_DM646X_TSIFINT0]           = 7,
 459         [IRQ_DM646X_TSIFINT1]           = 7,
 460         [IRQ_DM646X_VDCEINT]            = 7,
 461         [IRQ_DM646X_USBINT]             = 7,
 462         [IRQ_DM646X_USBDMAINT]          = 7,
 463         [IRQ_DM646X_PCIINT]             = 7,
 464         [IRQ_CCINT0]                    = 7,    /* dma */
 465         [IRQ_CCERRINT]                  = 7,    /* dma */
 466         [IRQ_TCERRINT0]                 = 7,    /* dma */
 467         [IRQ_TCERRINT]                  = 7,    /* dma */
 468         [IRQ_DM646X_TCERRINT2]          = 7,
 469         [IRQ_DM646X_TCERRINT3]          = 7,
 470         [IRQ_DM646X_IDE]                = 7,
 471         [IRQ_DM646X_HPIINT]             = 7,
 472         [IRQ_DM646X_EMACRXTHINT]        = 7,
 473         [IRQ_DM646X_EMACRXINT]          = 7,
 474         [IRQ_DM646X_EMACTXINT]          = 7,
 475         [IRQ_DM646X_EMACMISCINT]        = 7,
 476         [IRQ_DM646X_MCASP0TXINT]        = 7,
 477         [IRQ_DM646X_MCASP0RXINT]        = 7,
 478         [IRQ_AEMIFINT]                  = 7,
 479         [IRQ_DM646X_RESERVED_3]         = 7,
 480         [IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */
 481         [IRQ_TINT0_TINT34]              = 7,    /* clocksource */
 482         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 483         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 484         [IRQ_PWMINT0]                   = 7,
 485         [IRQ_PWMINT1]                   = 7,
 486         [IRQ_DM646X_VLQINT]             = 7,
 487         [IRQ_I2C]                       = 7,
 488         [IRQ_UARTINT0]                  = 7,
 489         [IRQ_UARTINT1]                  = 7,
 490         [IRQ_DM646X_UARTINT2]           = 7,
 491         [IRQ_DM646X_SPINT0]             = 7,
 492         [IRQ_DM646X_SPINT1]             = 7,
 493         [IRQ_DM646X_DSP2ARMINT]         = 7,
 494         [IRQ_DM646X_RESERVED_4]         = 7,
 495         [IRQ_DM646X_PSCINT]             = 7,
 496         [IRQ_DM646X_GPIO0]              = 7,
 497         [IRQ_DM646X_GPIO1]              = 7,
 498         [IRQ_DM646X_GPIO2]              = 7,
 499         [IRQ_DM646X_GPIO3]              = 7,
 500         [IRQ_DM646X_GPIO4]              = 7,
 501         [IRQ_DM646X_GPIO5]              = 7,
 502         [IRQ_DM646X_GPIO6]              = 7,
 503         [IRQ_DM646X_GPIO7]              = 7,
 504         [IRQ_DM646X_GPIOBNK0]           = 7,
 505         [IRQ_DM646X_GPIOBNK1]           = 7,
 506         [IRQ_DM646X_GPIOBNK2]           = 7,
 507         [IRQ_DM646X_DDRINT]             = 7,
 508         [IRQ_DM646X_AEMIFINT]           = 7,
 509         [IRQ_COMMTX]                    = 7,
 510         [IRQ_COMMRX]                    = 7,
 511         [IRQ_EMUINT]                    = 7,
 512 };
 513
 514 /*----------------------------------------------------------------------*/
 515
 516 static const s8 dma_chan_dm646x_no_event[] = {
 517          0,  1,  2,  3, 13,
 518         14, 15, 24, 25, 26,
 519         27, 30, 31, 54, 55,
 520         56,
 521         -1
 522 };
 523
 524 /* Four Transfer Controllers on DM646x */
 525 static const s8
 526 dm646x_queue_tc_mapping[][2] = {
 527         /* {event queue no, TC no} */
 528         {0, 0},
 529         {1, 1},
 530         {2, 2},
 531         {3, 3},
 532         {-1, -1},
 533 };
 534
 535 static const s8
 536 dm646x_queue_priority_mapping[][2] = {
 537         /* {event queue no, Priority} */
 538         {0, 4},
 539         {1, 0},
 540         {2, 5},
 541         {3, 1},
 542         {-1, -1},
 543 };
 544
 545 static struct edma_soc_info dm646x_edma_info[] = {
 546         {
 547                 .n_channel              = 64,
 548                 .n_region               = 6,    /* 0-1, 4-7 */
 549                 .n_slot                 = 512,
 550                 .n_tc                   = 4,
 551                 .n_cc                   = 1,
 552                 .noevent                = dma_chan_dm646x_no_event,
 553                 .queue_tc_mapping       = dm646x_queue_tc_mapping,
 554                 .queue_priority_mapping = dm646x_queue_priority_mapping,
 555         },
 556 };
 557
 558 static struct resource edma_resources[] = {
 559         {
 560                 .name   = "edma_cc0",
 561                 .start  = 0x01c00000,
 562                 .end    = 0x01c00000 + SZ_64K - 1,
 563                 .flags  = IORESOURCE_MEM,
 564         },
 565         {
 566                 .name   = "edma_tc0",
 567                 .start  = 0x01c10000,
 568                 .end    = 0x01c10000 + SZ_1K - 1,
 569                 .flags  = IORESOURCE_MEM,
 570         },
 571         {
 572                 .name   = "edma_tc1",
 573                 .start  = 0x01c10400,
 574                 .end    = 0x01c10400 + SZ_1K - 1,
 575                 .flags  = IORESOURCE_MEM,
 576         },
 577         {
 578                 .name   = "edma_tc2",
 579                 .start  = 0x01c10800,
 580                 .end    = 0x01c10800 + SZ_1K - 1,
 581                 .flags  = IORESOURCE_MEM,
 582         },
 583         {
 584                 .name   = "edma_tc3",
 585                 .start  = 0x01c10c00,
 586                 .end    = 0x01c10c00 + SZ_1K - 1,
 587                 .flags  = IORESOURCE_MEM,
 588         },
 589         {
 590                 .name   = "edma0",
 591                 .start  = IRQ_CCINT0,
 592                 .flags  = IORESOURCE_IRQ,
 593         },
 594         {
 595                 .name   = "edma0_err",
 596                 .start  = IRQ_CCERRINT,
 597                 .flags  = IORESOURCE_IRQ,
 598         },
 599         /* not using TC*_ERR */
 600 };
 601
 602 static struct platform_device dm646x_edma_device = {
 603         .name                   = "edma",
 604         .id                     = 0,
 605         .dev.platform_data      = dm646x_edma_info,
 606         .num_resources          = ARRAY_SIZE(edma_resources),
 607         .resource               = edma_resources,
 608 };
 609
 610 static struct resource ide_resources[] = {
 611         {
 612                 .start          = DM646X_ATA_REG_BASE,
 613                 .end            = DM646X_ATA_REG_BASE + 0x7ff,
 614                 .flags          = IORESOURCE_MEM,
 615         },
 616         {
 617                 .start          = IRQ_DM646X_IDE,
 618                 .end            = IRQ_DM646X_IDE,
 619                 .flags          = IORESOURCE_IRQ,
 620         },
 621 };
 622
 623 static u64 ide_dma_mask = DMA_BIT_MASK(32);
 624
 625 static struct platform_device ide_dev = {
 626         .name           = "palm_bk3710",
 627         .id             = -1,
 628         .resource       = ide_resources,
 629         .num_resources  = ARRAY_SIZE(ide_resources),
 630         .dev = {
 631                 .dma_mask               = &ide_dma_mask,
 632                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 633         },
 634 };
 635
 636 static struct resource dm646x_mcasp0_resources[] = {
 637         {
 638                 .name   = "mcasp0",
 639                 .start  = DAVINCI_DM646X_MCASP0_REG_BASE,
 640                 .end    = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
 641                 .flags  = IORESOURCE_MEM,
 642         },
 643         /* first TX, then RX */
 644         {
 645                 .start  = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
 646                 .end    = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
 647                 .flags  = IORESOURCE_DMA,
 648         },
 649         {
 650                 .start  = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
 651                 .end    = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
 652                 .flags  = IORESOURCE_DMA,
 653         },
 654 };
 655
 656 static struct resource dm646x_mcasp1_resources[] = {
 657         {
 658                 .name   = "mcasp1",
 659                 .start  = DAVINCI_DM646X_MCASP1_REG_BASE,
 660                 .end    = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
 661                 .flags  = IORESOURCE_MEM,
 662         },
 663         /* DIT mode, only TX event */
 664         {
 665                 .start  = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
 666                 .end    = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
 667                 .flags  = IORESOURCE_DMA,
 668         },
 669         /* DIT mode, dummy entry */
 670         {
 671                 .start  = -1,
 672                 .end    = -1,
 673                 .flags  = IORESOURCE_DMA,
 674         },
 675 };
 676
 677 static struct platform_device dm646x_mcasp0_device = {
 678         .name           = "davinci-mcasp",
 679         .id             = 0,
 680         .num_resources  = ARRAY_SIZE(dm646x_mcasp0_resources),
 681         .resource       = dm646x_mcasp0_resources,
 682 };
 683
 684 static struct platform_device dm646x_mcasp1_device = {
 685         .name           = "davinci-mcasp",
 686         .id             = 1,
 687         .num_resources  = ARRAY_SIZE(dm646x_mcasp1_resources),
 688         .resource       = dm646x_mcasp1_resources,
 689 };
 690
 691 static struct platform_device dm646x_dit_device = {
 692         .name   = "spdif-dit",
 693         .id     = -1,
 694 };
 695
 696 static u64 vpif_dma_mask = DMA_BIT_MASK(32);
 697
 698 static struct resource vpif_resource[] = {
 699         {
 700                 .start  = DAVINCI_VPIF_BASE,
 701                 .end    = DAVINCI_VPIF_BASE + 0x03ff,
 702                 .flags  = IORESOURCE_MEM,
 703         }
 704 };
 705
 706 static struct platform_device vpif_dev = {
 707         .name           = "vpif",
 708         .id             = -1,
 709         .dev            = {
 710                         .dma_mask               = &vpif_dma_mask,
 711                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 712         },
 713         .resource       = vpif_resource,
 714         .num_resources  = ARRAY_SIZE(vpif_resource),
 715 };
 716
 717 static struct resource vpif_display_resource[] = {
 718         {
 719                 .start = IRQ_DM646X_VP_VERTINT2,
 720                 .end   = IRQ_DM646X_VP_VERTINT2,
 721                 .flags = IORESOURCE_IRQ,
 722         },
 723         {
 724                 .start = IRQ_DM646X_VP_VERTINT3,
 725                 .end   = IRQ_DM646X_VP_VERTINT3,
 726                 .flags = IORESOURCE_IRQ,
 727         },
 728 };
 729
 730 static struct platform_device vpif_display_dev = {
 731         .name           = "vpif_display",
 732         .id             = -1,
 733         .dev            = {
 734                         .dma_mask               = &vpif_dma_mask,
 735                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 736         },
 737         .resource       = vpif_display_resource,
 738         .num_resources  = ARRAY_SIZE(vpif_display_resource),
 739 };
 740
 741 static struct resource vpif_capture_resource[] = {
 742         {
 743                 .start = IRQ_DM646X_VP_VERTINT0,
 744                 .end   = IRQ_DM646X_VP_VERTINT0,
 745                 .flags = IORESOURCE_IRQ,
 746         },
 747         {
 748                 .start = IRQ_DM646X_VP_VERTINT1,
 749                 .end   = IRQ_DM646X_VP_VERTINT1,
 750                 .flags = IORESOURCE_IRQ,
 751         },
 752 };
 753
 754 static struct platform_device vpif_capture_dev = {
 755         .name           = "vpif_capture",
 756         .id             = -1,
 757         .dev            = {
 758                         .dma_mask               = &vpif_dma_mask,
 759                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 760         },
 761         .resource       = vpif_capture_resource,
 762         .num_resources  = ARRAY_SIZE(vpif_capture_resource),
 763 };
 764
 765 /*----------------------------------------------------------------------*/
 766
 767 static struct map_desc dm646x_io_desc[] = {
 768         {
 769                 .virtual        = IO_VIRT,
 770                 .pfn            = __phys_to_pfn(IO_PHYS),
 771                 .length         = IO_SIZE,
 772                 .type           = MT_DEVICE
 773         },
 774         {
 775                 .virtual        = SRAM_VIRT,
 776                 .pfn            = __phys_to_pfn(0x00010000),
 777                 .length         = SZ_32K,
 778                 /* MT_MEMORY_NONCACHED requires supersection alignment */
 779                 .type           = MT_DEVICE,
 780         },
 781 };
 782
 783 /* Contents of JTAG ID register used to identify exact cpu type */
 784 static struct davinci_id dm646x_ids[] = {
 785         {
 786                 .variant        = 0x0,
 787                 .part_no        = 0xb770,
 788                 .manufacturer   = 0x017,
 789                 .cpu_id         = DAVINCI_CPU_ID_DM6467,
 790                 .name           = "dm6467_rev1.x",
 791         },
 792         {
 793                 .variant        = 0x1,
 794                 .part_no        = 0xb770,
 795                 .manufacturer   = 0x017,
 796                 .cpu_id         = DAVINCI_CPU_ID_DM6467,
 797                 .name           = "dm6467_rev3.x",
 798         },
 799 };
 800
 801 static void __iomem *dm646x_psc_bases[] = {
 802         IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
 803 };
 804
 805 /*
 806  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 807  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 808  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 809  * T1_TOP: Timer 1, top   :  <unused>
 810  */
 811 struct davinci_timer_info dm646x_timer_info = {
 812         .timers         = davinci_timer_instance,
 813         .clockevent_id  = T0_BOT,
 814         .clocksource_id = T0_TOP,
 815 };
 816
 817 static struct plat_serial8250_port dm646x_serial_platform_data[] = {
 818         {
 819                 .mapbase        = DAVINCI_UART0_BASE,
 820                 .irq            = IRQ_UARTINT0,
 821                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 822                                   UPF_IOREMAP,
 823                 .iotype         = UPIO_MEM32,
 824                 .regshift       = 2,
 825         },
 826         {
 827                 .mapbase        = DAVINCI_UART1_BASE,
 828                 .irq            = IRQ_UARTINT1,
 829                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 830                                   UPF_IOREMAP,
 831                 .iotype         = UPIO_MEM32,
 832                 .regshift       = 2,
 833         },
 834         {
 835                 .mapbase        = DAVINCI_UART2_BASE,
 836                 .irq            = IRQ_DM646X_UARTINT2,
 837                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 838                                   UPF_IOREMAP,
 839                 .iotype         = UPIO_MEM32,
 840                 .regshift       = 2,
 841         },
 842         {
 843                 .flags          = 0
 844         },
 845 };
 846
 847 static struct platform_device dm646x_serial_device = {
 848         .name                   = "serial8250",
 849         .id                     = PLAT8250_DEV_PLATFORM,
 850         .dev                    = {
 851                 .platform_data  = dm646x_serial_platform_data,
 852         },
 853 };
 854
 855 static struct davinci_soc_info davinci_soc_info_dm646x = {
 856         .io_desc                = dm646x_io_desc,
 857         .io_desc_num            = ARRAY_SIZE(dm646x_io_desc),
 858         .jtag_id_base           = IO_ADDRESS(0x01c40028),
 859         .ids                    = dm646x_ids,
 860         .ids_num                = ARRAY_SIZE(dm646x_ids),
 861         .cpu_clks               = dm646x_clks,
 862         .psc_bases              = dm646x_psc_bases,
 863         .psc_bases_num          = ARRAY_SIZE(dm646x_psc_bases),
 864         .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 865         .pinmux_pins            = dm646x_pins,
 866         .pinmux_pins_num        = ARRAY_SIZE(dm646x_pins),
 867         .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
 868         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 869         .intc_irq_prios         = dm646x_default_priorities,
 870         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 871         .timer_info             = &dm646x_timer_info,
 872         .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
 873         .gpio_num               = 43, /* Only 33 usable */
 874         .gpio_irq               = IRQ_DM646X_GPIOBNK0,
 875         .serial_dev             = &dm646x_serial_device,
 876         .emac_pdata             = &dm646x_emac_pdata,
 877         .sram_dma               = 0x10010000,
 878         .sram_len               = SZ_32K,
 879 };
 880
 881 void __init dm646x_init_ide()
 882 {
 883         davinci_cfg_reg(DM646X_ATAEN);
 884         platform_device_register(&ide_dev);
 885 }
 886
 887 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
 888 {
 889         dm646x_mcasp0_device.dev.platform_data = pdata;
 890         platform_device_register(&dm646x_mcasp0_device);
 891 }
 892
 893 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
 894 {
 895         dm646x_mcasp1_device.dev.platform_data = pdata;
 896         platform_device_register(&dm646x_mcasp1_device);
 897         platform_device_register(&dm646x_dit_device);
 898 }
 899
 900 void dm646x_setup_vpif(struct vpif_display_config *display_config,
 901                        struct vpif_capture_config *capture_config)
 902 {
 903         unsigned int value;
 904         void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
 905
 906         value = __raw_readl(base + VSCLKDIS_OFFSET);
 907         value &= ~VSCLKDIS_MASK;
 908         __raw_writel(value, base + VSCLKDIS_OFFSET);
 909
 910         value = __raw_readl(base + VDD3P3V_PWDN_OFFSET);
 911         value &= ~VDD3P3V_VID_MASK;
 912         __raw_writel(value, base + VDD3P3V_PWDN_OFFSET);
 913
 914         davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
 915         davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
 916         davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
 917         davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
 918
 919         vpif_display_dev.dev.platform_data = display_config;
 920         vpif_capture_dev.dev.platform_data = capture_config;
 921         platform_device_register(&vpif_dev);
 922         platform_device_register(&vpif_display_dev);
 923         platform_device_register(&vpif_capture_dev);
 924 }
 925
 926 void __init dm646x_init(void)
 927 {
 928         davinci_common_init(&davinci_soc_info_dm646x);
 929 }
 930
 931 static int __init dm646x_init_devices(void)
 932 {
 933         if (!cpu_is_davinci_dm646x())
 934                 return 0;
 935
 936         platform_device_register(&dm646x_edma_device);
 937         platform_device_register(&dm646x_emac_device);
 938         return 0;
 939 }
 940 postcore_initcall(dm646x_init_devices);