arch/arm/mach-davinci/dm646x.c

   1 /*
   2  * TI DaVinci DM644x chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/clk.h>
  13 #include <linux/serial_8250.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/gpio.h>
  16
  17 #include <asm/mach/map.h>
  18
  19 #include <mach/dm646x.h>
  20 #include <mach/cputype.h>
  21 #include <mach/edma.h>
  22 #include <mach/irqs.h>
  23 #include <mach/psc.h>
  24 #include <mach/mux.h>
  25 #include <mach/time.h>
  26 #include <mach/serial.h>
  27 #include <mach/common.h>
  28 #include <mach/asp.h>
  29
  30 #include "clock.h"
  31 #include "mux.h"
  32
  33 #define DAVINCI_VPIF_BASE       (0x01C12000)
  34 #define VDD3P3V_PWDN_OFFSET     (0x48)
  35 #define VSCLKDIS_OFFSET         (0x6C)
  36
  37 #define VDD3P3V_VID_MASK        (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
  38                                         BIT_MASK(0))
  39 #define VSCLKDIS_MASK           (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
  40                                         BIT_MASK(8))
  41
  42 /*
  43  * Device specific clocks
  44  */
  45 #define DM646X_AUX_FREQ         24000000
  46
  47 static struct pll_data pll1_data = {
  48         .num       = 1,
  49         .phys_base = DAVINCI_PLL1_BASE,
  50 };
  51
  52 static struct pll_data pll2_data = {
  53         .num       = 2,
  54         .phys_base = DAVINCI_PLL2_BASE,
  55 };
  56
  57 static struct clk ref_clk = {
  58         .name = "ref_clk",
  59 };
  60
  61 static struct clk aux_clkin = {
  62         .name = "aux_clkin",
  63         .rate = DM646X_AUX_FREQ,
  64 };
  65
  66 static struct clk pll1_clk = {
  67         .name = "pll1",
  68         .parent = &ref_clk,
  69         .pll_data = &pll1_data,
  70         .flags = CLK_PLL,
  71 };
  72
  73 static struct clk pll1_sysclk1 = {
  74         .name = "pll1_sysclk1",
  75         .parent = &pll1_clk,
  76         .flags = CLK_PLL,
  77         .div_reg = PLLDIV1,
  78 };
  79
  80 static struct clk pll1_sysclk2 = {
  81         .name = "pll1_sysclk2",
  82         .parent = &pll1_clk,
  83         .flags = CLK_PLL,
  84         .div_reg = PLLDIV2,
  85 };
  86
  87 static struct clk pll1_sysclk3 = {
  88         .name = "pll1_sysclk3",
  89         .parent = &pll1_clk,
  90         .flags = CLK_PLL,
  91         .div_reg = PLLDIV3,
  92 };
  93
  94 static struct clk pll1_sysclk4 = {
  95         .name = "pll1_sysclk4",
  96         .parent = &pll1_clk,
  97         .flags = CLK_PLL,
  98         .div_reg = PLLDIV4,
  99 };
 100
 101 static struct clk pll1_sysclk5 = {
 102         .name = "pll1_sysclk5",
 103         .parent = &pll1_clk,
 104         .flags = CLK_PLL,
 105         .div_reg = PLLDIV5,
 106 };
 107
 108 static struct clk pll1_sysclk6 = {
 109         .name = "pll1_sysclk6",
 110         .parent = &pll1_clk,
 111         .flags = CLK_PLL,
 112         .div_reg = PLLDIV6,
 113 };
 114
 115 static struct clk pll1_sysclk8 = {
 116         .name = "pll1_sysclk8",
 117         .parent = &pll1_clk,
 118         .flags = CLK_PLL,
 119         .div_reg = PLLDIV8,
 120 };
 121
 122 static struct clk pll1_sysclk9 = {
 123         .name = "pll1_sysclk9",
 124         .parent = &pll1_clk,
 125         .flags = CLK_PLL,
 126         .div_reg = PLLDIV9,
 127 };
 128
 129 static struct clk pll1_sysclkbp = {
 130         .name = "pll1_sysclkbp",
 131         .parent = &pll1_clk,
 132         .flags = CLK_PLL | PRE_PLL,
 133         .div_reg = BPDIV,
 134 };
 135
 136 static struct clk pll1_aux_clk = {
 137         .name = "pll1_aux_clk",
 138         .parent = &pll1_clk,
 139         .flags = CLK_PLL | PRE_PLL,
 140 };
 141
 142 static struct clk pll2_clk = {
 143         .name = "pll2_clk",
 144         .parent = &ref_clk,
 145         .pll_data = &pll2_data,
 146         .flags = CLK_PLL,
 147 };
 148
 149 static struct clk pll2_sysclk1 = {
 150         .name = "pll2_sysclk1",
 151         .parent = &pll2_clk,
 152         .flags = CLK_PLL,
 153         .div_reg = PLLDIV1,
 154 };
 155
 156 static struct clk dsp_clk = {
 157         .name = "dsp",
 158         .parent = &pll1_sysclk1,
 159         .lpsc = DM646X_LPSC_C64X_CPU,
 160         .flags = PSC_DSP,
 161         .usecount = 1,                  /* REVISIT how to disable? */
 162 };
 163
 164 static struct clk arm_clk = {
 165         .name = "arm",
 166         .parent = &pll1_sysclk2,
 167         .lpsc = DM646X_LPSC_ARM,
 168         .flags = ALWAYS_ENABLED,
 169 };
 170
 171 static struct clk edma_cc_clk = {
 172         .name = "edma_cc",
 173         .parent = &pll1_sysclk2,
 174         .lpsc = DM646X_LPSC_TPCC,
 175         .flags = ALWAYS_ENABLED,
 176 };
 177
 178 static struct clk edma_tc0_clk = {
 179         .name = "edma_tc0",
 180         .parent = &pll1_sysclk2,
 181         .lpsc = DM646X_LPSC_TPTC0,
 182         .flags = ALWAYS_ENABLED,
 183 };
 184
 185 static struct clk edma_tc1_clk = {
 186         .name = "edma_tc1",
 187         .parent = &pll1_sysclk2,
 188         .lpsc = DM646X_LPSC_TPTC1,
 189         .flags = ALWAYS_ENABLED,
 190 };
 191
 192 static struct clk edma_tc2_clk = {
 193         .name = "edma_tc2",
 194         .parent = &pll1_sysclk2,
 195         .lpsc = DM646X_LPSC_TPTC2,
 196         .flags = ALWAYS_ENABLED,
 197 };
 198
 199 static struct clk edma_tc3_clk = {
 200         .name = "edma_tc3",
 201         .parent = &pll1_sysclk2,
 202         .lpsc = DM646X_LPSC_TPTC3,
 203         .flags = ALWAYS_ENABLED,
 204 };
 205
 206 static struct clk uart0_clk = {
 207         .name = "uart0",
 208         .parent = &aux_clkin,
 209         .lpsc = DM646X_LPSC_UART0,
 210 };
 211
 212 static struct clk uart1_clk = {
 213         .name = "uart1",
 214         .parent = &aux_clkin,
 215         .lpsc = DM646X_LPSC_UART1,
 216 };
 217
 218 static struct clk uart2_clk = {
 219         .name = "uart2",
 220         .parent = &aux_clkin,
 221         .lpsc = DM646X_LPSC_UART2,
 222 };
 223
 224 static struct clk i2c_clk = {
 225         .name = "I2CCLK",
 226         .parent = &pll1_sysclk3,
 227         .lpsc = DM646X_LPSC_I2C,
 228 };
 229
 230 static struct clk gpio_clk = {
 231         .name = "gpio",
 232         .parent = &pll1_sysclk3,
 233         .lpsc = DM646X_LPSC_GPIO,
 234 };
 235
 236 static struct clk mcasp0_clk = {
 237         .name = "mcasp0",
 238         .parent = &pll1_sysclk3,
 239         .lpsc = DM646X_LPSC_McASP0,
 240 };
 241
 242 static struct clk mcasp1_clk = {
 243         .name = "mcasp1",
 244         .parent = &pll1_sysclk3,
 245         .lpsc = DM646X_LPSC_McASP1,
 246 };
 247
 248 static struct clk aemif_clk = {
 249         .name = "aemif",
 250         .parent = &pll1_sysclk3,
 251         .lpsc = DM646X_LPSC_AEMIF,
 252         .flags = ALWAYS_ENABLED,
 253 };
 254
 255 static struct clk emac_clk = {
 256         .name = "emac",
 257         .parent = &pll1_sysclk3,
 258         .lpsc = DM646X_LPSC_EMAC,
 259 };
 260
 261 static struct clk pwm0_clk = {
 262         .name = "pwm0",
 263         .parent = &pll1_sysclk3,
 264         .lpsc = DM646X_LPSC_PWM0,
 265         .usecount = 1,            /* REVIST: disabling hangs system */
 266 };
 267
 268 static struct clk pwm1_clk = {
 269         .name = "pwm1",
 270         .parent = &pll1_sysclk3,
 271         .lpsc = DM646X_LPSC_PWM1,
 272         .usecount = 1,            /* REVIST: disabling hangs system */
 273 };
 274
 275 static struct clk timer0_clk = {
 276         .name = "timer0",
 277         .parent = &pll1_sysclk3,
 278         .lpsc = DM646X_LPSC_TIMER0,
 279 };
 280
 281 static struct clk timer1_clk = {
 282         .name = "timer1",
 283         .parent = &pll1_sysclk3,
 284         .lpsc = DM646X_LPSC_TIMER1,
 285 };
 286
 287 static struct clk timer2_clk = {
 288         .name = "timer2",
 289         .parent = &pll1_sysclk3,
 290         .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
 291 };
 292
 293
 294 static struct clk ide_clk = {
 295         .name = "ide",
 296         .parent = &pll1_sysclk4,
 297         .lpsc = DAVINCI_LPSC_ATA,
 298 };
 299
 300 static struct clk vpif0_clk = {
 301         .name = "vpif0",
 302         .parent = &ref_clk,
 303         .lpsc = DM646X_LPSC_VPSSMSTR,
 304         .flags = ALWAYS_ENABLED,
 305 };
 306
 307 static struct clk vpif1_clk = {
 308         .name = "vpif1",
 309         .parent = &ref_clk,
 310         .lpsc = DM646X_LPSC_VPSSSLV,
 311         .flags = ALWAYS_ENABLED,
 312 };
 313
 314 static struct clk_lookup dm646x_clks[] = {
 315         CLK(NULL, "ref", &ref_clk),
 316         CLK(NULL, "aux", &aux_clkin),
 317         CLK(NULL, "pll1", &pll1_clk),
 318         CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
 319         CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
 320         CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
 321         CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
 322         CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
 323         CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
 324         CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
 325         CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
 326         CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
 327         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 328         CLK(NULL, "pll2", &pll2_clk),
 329         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 330         CLK(NULL, "dsp", &dsp_clk),
 331         CLK(NULL, "arm", &arm_clk),
 332         CLK(NULL, "edma_cc", &edma_cc_clk),
 333         CLK(NULL, "edma_tc0", &edma_tc0_clk),
 334         CLK(NULL, "edma_tc1", &edma_tc1_clk),
 335         CLK(NULL, "edma_tc2", &edma_tc2_clk),
 336         CLK(NULL, "edma_tc3", &edma_tc3_clk),
 337         CLK(NULL, "uart0", &uart0_clk),
 338         CLK(NULL, "uart1", &uart1_clk),
 339         CLK(NULL, "uart2", &uart2_clk),
 340         CLK("i2c_davinci.1", NULL, &i2c_clk),
 341         CLK(NULL, "gpio", &gpio_clk),
 342         CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
 343         CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
 344         CLK(NULL, "aemif", &aemif_clk),
 345         CLK("davinci_emac.1", NULL, &emac_clk),
 346         CLK(NULL, "pwm0", &pwm0_clk),
 347         CLK(NULL, "pwm1", &pwm1_clk),
 348         CLK(NULL, "timer0", &timer0_clk),
 349         CLK(NULL, "timer1", &timer1_clk),
 350         CLK("watchdog", NULL, &timer2_clk),
 351         CLK("palm_bk3710", NULL, &ide_clk),
 352         CLK(NULL, "vpif0", &vpif0_clk),
 353         CLK(NULL, "vpif1", &vpif1_clk),
 354         CLK(NULL, NULL, NULL),
 355 };
 356
 357 static struct emac_platform_data dm646x_emac_pdata = {
 358         .ctrl_reg_offset        = DM646X_EMAC_CNTRL_OFFSET,
 359         .ctrl_mod_reg_offset    = DM646X_EMAC_CNTRL_MOD_OFFSET,
 360         .ctrl_ram_offset        = DM646X_EMAC_CNTRL_RAM_OFFSET,
 361         .ctrl_ram_size          = DM646X_EMAC_CNTRL_RAM_SIZE,
 362         .version                = EMAC_VERSION_2,
 363 };
 364
 365 static struct resource dm646x_emac_resources[] = {
 366         {
 367                 .start  = DM646X_EMAC_BASE,
 368                 .end    = DM646X_EMAC_BASE + SZ_16K - 1,
 369                 .flags  = IORESOURCE_MEM,
 370         },
 371         {
 372                 .start  = IRQ_DM646X_EMACRXTHINT,
 373                 .end    = IRQ_DM646X_EMACRXTHINT,
 374                 .flags  = IORESOURCE_IRQ,
 375         },
 376         {
 377                 .start  = IRQ_DM646X_EMACRXINT,
 378                 .end    = IRQ_DM646X_EMACRXINT,
 379                 .flags  = IORESOURCE_IRQ,
 380         },
 381         {
 382                 .start  = IRQ_DM646X_EMACTXINT,
 383                 .end    = IRQ_DM646X_EMACTXINT,
 384                 .flags  = IORESOURCE_IRQ,
 385         },
 386         {
 387                 .start  = IRQ_DM646X_EMACMISCINT,
 388                 .end    = IRQ_DM646X_EMACMISCINT,
 389                 .flags  = IORESOURCE_IRQ,
 390         },
 391 };
 392
 393 static struct platform_device dm646x_emac_device = {
 394         .name           = "davinci_emac",
 395         .id             = 1,
 396         .dev = {
 397                 .platform_data  = &dm646x_emac_pdata,
 398         },
 399         .num_resources  = ARRAY_SIZE(dm646x_emac_resources),
 400         .resource       = dm646x_emac_resources,
 401 };
 402
 403 static struct resource dm646x_mdio_resources[] = {
 404         {
 405                 .start  = DM646X_EMAC_MDIO_BASE,
 406                 .end    = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
 407                 .flags  = IORESOURCE_MEM,
 408         },
 409 };
 410
 411 static struct platform_device dm646x_mdio_device = {
 412         .name           = "davinci_mdio",
 413         .id             = 0,
 414         .num_resources  = ARRAY_SIZE(dm646x_mdio_resources),
 415         .resource       = dm646x_mdio_resources,
 416 };
 417
 418 /*
 419  * Device specific mux setup
 420  *
 421  *      soc     description     mux  mode   mode  mux    dbg
 422  *                              reg  offset mask  mode
 423  */
 424 static const struct mux_config dm646x_pins[] = {
 425 #ifdef CONFIG_DAVINCI_MUX
 426 MUX_CFG(DM646X, ATAEN,          0,   0,     5,    1,     true)
 427
 428 MUX_CFG(DM646X, AUDCK1,         0,   29,    1,    0,     false)
 429
 430 MUX_CFG(DM646X, AUDCK0,         0,   28,    1,    0,     false)
 431
 432 MUX_CFG(DM646X, CRGMUX,                 0,   24,    7,    5,     true)
 433
 434 MUX_CFG(DM646X, STSOMUX_DISABLE,        0,   22,    3,    0,     true)
 435
 436 MUX_CFG(DM646X, STSIMUX_DISABLE,        0,   20,    3,    0,     true)
 437
 438 MUX_CFG(DM646X, PTSOMUX_DISABLE,        0,   18,    3,    0,     true)
 439
 440 MUX_CFG(DM646X, PTSIMUX_DISABLE,        0,   16,    3,    0,     true)
 441
 442 MUX_CFG(DM646X, STSOMUX,                0,   22,    3,    2,     true)
 443
 444 MUX_CFG(DM646X, STSIMUX,                0,   20,    3,    2,     true)
 445
 446 MUX_CFG(DM646X, PTSOMUX_PARALLEL,       0,   18,    3,    2,     true)
 447
 448 MUX_CFG(DM646X, PTSIMUX_PARALLEL,       0,   16,    3,    2,     true)
 449
 450 MUX_CFG(DM646X, PTSOMUX_SERIAL,         0,   18,    3,    3,     true)
 451
 452 MUX_CFG(DM646X, PTSIMUX_SERIAL,         0,   16,    3,    3,     true)
 453 #endif
 454 };
 455
 456 static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 457         [IRQ_DM646X_VP_VERTINT0]        = 7,
 458         [IRQ_DM646X_VP_VERTINT1]        = 7,
 459         [IRQ_DM646X_VP_VERTINT2]        = 7,
 460         [IRQ_DM646X_VP_VERTINT3]        = 7,
 461         [IRQ_DM646X_VP_ERRINT]          = 7,
 462         [IRQ_DM646X_RESERVED_1]         = 7,
 463         [IRQ_DM646X_RESERVED_2]         = 7,
 464         [IRQ_DM646X_WDINT]              = 7,
 465         [IRQ_DM646X_CRGENINT0]          = 7,
 466         [IRQ_DM646X_CRGENINT1]          = 7,
 467         [IRQ_DM646X_TSIFINT0]           = 7,
 468         [IRQ_DM646X_TSIFINT1]           = 7,
 469         [IRQ_DM646X_VDCEINT]            = 7,
 470         [IRQ_DM646X_USBINT]             = 7,
 471         [IRQ_DM646X_USBDMAINT]          = 7,
 472         [IRQ_DM646X_PCIINT]             = 7,
 473         [IRQ_CCINT0]                    = 7,    /* dma */
 474         [IRQ_CCERRINT]                  = 7,    /* dma */
 475         [IRQ_TCERRINT0]                 = 7,    /* dma */
 476         [IRQ_TCERRINT]                  = 7,    /* dma */
 477         [IRQ_DM646X_TCERRINT2]          = 7,
 478         [IRQ_DM646X_TCERRINT3]          = 7,
 479         [IRQ_DM646X_IDE]                = 7,
 480         [IRQ_DM646X_HPIINT]             = 7,
 481         [IRQ_DM646X_EMACRXTHINT]        = 7,
 482         [IRQ_DM646X_EMACRXINT]          = 7,
 483         [IRQ_DM646X_EMACTXINT]          = 7,
 484         [IRQ_DM646X_EMACMISCINT]        = 7,
 485         [IRQ_DM646X_MCASP0TXINT]        = 7,
 486         [IRQ_DM646X_MCASP0RXINT]        = 7,
 487         [IRQ_AEMIFINT]                  = 7,
 488         [IRQ_DM646X_RESERVED_3]         = 7,
 489         [IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */
 490         [IRQ_TINT0_TINT34]              = 7,    /* clocksource */
 491         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 492         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 493         [IRQ_PWMINT0]                   = 7,
 494         [IRQ_PWMINT1]                   = 7,
 495         [IRQ_DM646X_VLQINT]             = 7,
 496         [IRQ_I2C]                       = 7,
 497         [IRQ_UARTINT0]                  = 7,
 498         [IRQ_UARTINT1]                  = 7,
 499         [IRQ_DM646X_UARTINT2]           = 7,
 500         [IRQ_DM646X_SPINT0]             = 7,
 501         [IRQ_DM646X_SPINT1]             = 7,
 502         [IRQ_DM646X_DSP2ARMINT]         = 7,
 503         [IRQ_DM646X_RESERVED_4]         = 7,
 504         [IRQ_DM646X_PSCINT]             = 7,
 505         [IRQ_DM646X_GPIO0]              = 7,
 506         [IRQ_DM646X_GPIO1]              = 7,
 507         [IRQ_DM646X_GPIO2]              = 7,
 508         [IRQ_DM646X_GPIO3]              = 7,
 509         [IRQ_DM646X_GPIO4]              = 7,
 510         [IRQ_DM646X_GPIO5]              = 7,
 511         [IRQ_DM646X_GPIO6]              = 7,
 512         [IRQ_DM646X_GPIO7]              = 7,
 513         [IRQ_DM646X_GPIOBNK0]           = 7,
 514         [IRQ_DM646X_GPIOBNK1]           = 7,
 515         [IRQ_DM646X_GPIOBNK2]           = 7,
 516         [IRQ_DM646X_DDRINT]             = 7,
 517         [IRQ_DM646X_AEMIFINT]           = 7,
 518         [IRQ_COMMTX]                    = 7,
 519         [IRQ_COMMRX]                    = 7,
 520         [IRQ_EMUINT]                    = 7,
 521 };
 522
 523 /*----------------------------------------------------------------------*/
 524
 525 /* Four Transfer Controllers on DM646x */
 526 static const s8
 527 dm646x_queue_tc_mapping[][2] = {
 528         /* {event queue no, TC no} */
 529         {0, 0},
 530         {1, 1},
 531         {2, 2},
 532         {3, 3},
 533         {-1, -1},
 534 };
 535
 536 static const s8
 537 dm646x_queue_priority_mapping[][2] = {
 538         /* {event queue no, Priority} */
 539         {0, 4},
 540         {1, 0},
 541         {2, 5},
 542         {3, 1},
 543         {-1, -1},
 544 };
 545
 546 static struct edma_soc_info edma_cc0_info = {
 547         .n_channel              = 64,
 548         .n_region               = 6,    /* 0-1, 4-7 */
 549         .n_slot                 = 512,
 550         .n_tc                   = 4,
 551         .n_cc                   = 1,
 552         .queue_tc_mapping       = dm646x_queue_tc_mapping,
 553         .queue_priority_mapping = dm646x_queue_priority_mapping,
 554 };
 555
 556 static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = {
 557         &edma_cc0_info,
 558 };
 559
 560 static struct resource edma_resources[] = {
 561         {
 562                 .name   = "edma_cc0",
 563                 .start  = 0x01c00000,
 564                 .end    = 0x01c00000 + SZ_64K - 1,
 565                 .flags  = IORESOURCE_MEM,
 566         },
 567         {
 568                 .name   = "edma_tc0",
 569                 .start  = 0x01c10000,
 570                 .end    = 0x01c10000 + SZ_1K - 1,
 571                 .flags  = IORESOURCE_MEM,
 572         },
 573         {
 574                 .name   = "edma_tc1",
 575                 .start  = 0x01c10400,
 576                 .end    = 0x01c10400 + SZ_1K - 1,
 577                 .flags  = IORESOURCE_MEM,
 578         },
 579         {
 580                 .name   = "edma_tc2",
 581                 .start  = 0x01c10800,
 582                 .end    = 0x01c10800 + SZ_1K - 1,
 583                 .flags  = IORESOURCE_MEM,
 584         },
 585         {
 586                 .name   = "edma_tc3",
 587                 .start  = 0x01c10c00,
 588                 .end    = 0x01c10c00 + SZ_1K - 1,
 589                 .flags  = IORESOURCE_MEM,
 590         },
 591         {
 592                 .name   = "edma0",
 593                 .start  = IRQ_CCINT0,
 594                 .flags  = IORESOURCE_IRQ,
 595         },
 596         {
 597                 .name   = "edma0_err",
 598                 .start  = IRQ_CCERRINT,
 599                 .flags  = IORESOURCE_IRQ,
 600         },
 601         /* not using TC*_ERR */
 602 };
 603
 604 static struct platform_device dm646x_edma_device = {
 605         .name                   = "edma",
 606         .id                     = 0,
 607         .dev.platform_data      = dm646x_edma_info,
 608         .num_resources          = ARRAY_SIZE(edma_resources),
 609         .resource               = edma_resources,
 610 };
 611
 612 static struct resource dm646x_mcasp0_resources[] = {
 613         {
 614                 .name   = "mcasp0",
 615                 .start  = DAVINCI_DM646X_MCASP0_REG_BASE,
 616                 .end    = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
 617                 .flags  = IORESOURCE_MEM,
 618         },
 619         /* first TX, then RX */
 620         {
 621                 .start  = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
 622                 .end    = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
 623                 .flags  = IORESOURCE_DMA,
 624         },
 625         {
 626                 .start  = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
 627                 .end    = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
 628                 .flags  = IORESOURCE_DMA,
 629         },
 630 };
 631
 632 static struct resource dm646x_mcasp1_resources[] = {
 633         {
 634                 .name   = "mcasp1",
 635                 .start  = DAVINCI_DM646X_MCASP1_REG_BASE,
 636                 .end    = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
 637                 .flags  = IORESOURCE_MEM,
 638         },
 639         /* DIT mode, only TX event */
 640         {
 641                 .start  = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
 642                 .end    = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
 643                 .flags  = IORESOURCE_DMA,
 644         },
 645         /* DIT mode, dummy entry */
 646         {
 647                 .start  = -1,
 648                 .end    = -1,
 649                 .flags  = IORESOURCE_DMA,
 650         },
 651 };
 652
 653 static struct platform_device dm646x_mcasp0_device = {
 654         .name           = "davinci-mcasp",
 655         .id             = 0,
 656         .num_resources  = ARRAY_SIZE(dm646x_mcasp0_resources),
 657         .resource       = dm646x_mcasp0_resources,
 658 };
 659
 660 static struct platform_device dm646x_mcasp1_device = {
 661         .name           = "davinci-mcasp",
 662         .id             = 1,
 663         .num_resources  = ARRAY_SIZE(dm646x_mcasp1_resources),
 664         .resource       = dm646x_mcasp1_resources,
 665 };
 666
 667 static struct platform_device dm646x_dit_device = {
 668         .name   = "spdif-dit",
 669         .id     = -1,
 670 };
 671
 672 static u64 vpif_dma_mask = DMA_BIT_MASK(32);
 673
 674 static struct resource vpif_resource[] = {
 675         {
 676                 .start  = DAVINCI_VPIF_BASE,
 677                 .end    = DAVINCI_VPIF_BASE + 0x03ff,
 678                 .flags  = IORESOURCE_MEM,
 679         }
 680 };
 681
 682 static struct platform_device vpif_dev = {
 683         .name           = "vpif",
 684         .id             = -1,
 685         .dev            = {
 686                         .dma_mask               = &vpif_dma_mask,
 687                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 688         },
 689         .resource       = vpif_resource,
 690         .num_resources  = ARRAY_SIZE(vpif_resource),
 691 };
 692
 693 static struct resource vpif_display_resource[] = {
 694         {
 695                 .start = IRQ_DM646X_VP_VERTINT2,
 696                 .end   = IRQ_DM646X_VP_VERTINT2,
 697                 .flags = IORESOURCE_IRQ,
 698         },
 699         {
 700                 .start = IRQ_DM646X_VP_VERTINT3,
 701                 .end   = IRQ_DM646X_VP_VERTINT3,
 702                 .flags = IORESOURCE_IRQ,
 703         },
 704 };
 705
 706 static struct platform_device vpif_display_dev = {
 707         .name           = "vpif_display",
 708         .id             = -1,
 709         .dev            = {
 710                         .dma_mask               = &vpif_dma_mask,
 711                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 712         },
 713         .resource       = vpif_display_resource,
 714         .num_resources  = ARRAY_SIZE(vpif_display_resource),
 715 };
 716
 717 static struct resource vpif_capture_resource[] = {
 718         {
 719                 .start = IRQ_DM646X_VP_VERTINT0,
 720                 .end   = IRQ_DM646X_VP_VERTINT0,
 721                 .flags = IORESOURCE_IRQ,
 722         },
 723         {
 724                 .start = IRQ_DM646X_VP_VERTINT1,
 725                 .end   = IRQ_DM646X_VP_VERTINT1,
 726                 .flags = IORESOURCE_IRQ,
 727         },
 728 };
 729
 730 static struct platform_device vpif_capture_dev = {
 731         .name           = "vpif_capture",
 732         .id             = -1,
 733         .dev            = {
 734                         .dma_mask               = &vpif_dma_mask,
 735                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 736         },
 737         .resource       = vpif_capture_resource,
 738         .num_resources  = ARRAY_SIZE(vpif_capture_resource),
 739 };
 740
 741 /*----------------------------------------------------------------------*/
 742
 743 static struct map_desc dm646x_io_desc[] = {
 744         {
 745                 .virtual        = IO_VIRT,
 746                 .pfn            = __phys_to_pfn(IO_PHYS),
 747                 .length         = IO_SIZE,
 748                 .type           = MT_DEVICE
 749         },
 750         {
 751                 .virtual        = SRAM_VIRT,
 752                 .pfn            = __phys_to_pfn(0x00010000),
 753                 .length         = SZ_32K,
 754                 .type           = MT_MEMORY_NONCACHED,
 755         },
 756 };
 757
 758 /* Contents of JTAG ID register used to identify exact cpu type */
 759 static struct davinci_id dm646x_ids[] = {
 760         {
 761                 .variant        = 0x0,
 762                 .part_no        = 0xb770,
 763                 .manufacturer   = 0x017,
 764                 .cpu_id         = DAVINCI_CPU_ID_DM6467,
 765                 .name           = "dm6467_rev1.x",
 766         },
 767         {
 768                 .variant        = 0x1,
 769                 .part_no        = 0xb770,
 770                 .manufacturer   = 0x017,
 771                 .cpu_id         = DAVINCI_CPU_ID_DM6467,
 772                 .name           = "dm6467_rev3.x",
 773         },
 774 };
 775
 776 static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
 777
 778 /*
 779  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 780  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 781  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 782  * T1_TOP: Timer 1, top   :  <unused>
 783  */
 784 static struct davinci_timer_info dm646x_timer_info = {
 785         .timers         = davinci_timer_instance,
 786         .clockevent_id  = T0_BOT,
 787         .clocksource_id = T0_TOP,
 788 };
 789
 790 static struct plat_serial8250_port dm646x_serial_platform_data[] = {
 791         {
 792                 .mapbase        = DAVINCI_UART0_BASE,
 793                 .irq            = IRQ_UARTINT0,
 794                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 795                                   UPF_IOREMAP,
 796                 .iotype         = UPIO_MEM32,
 797                 .regshift       = 2,
 798         },
 799         {
 800                 .mapbase        = DAVINCI_UART1_BASE,
 801                 .irq            = IRQ_UARTINT1,
 802                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 803                                   UPF_IOREMAP,
 804                 .iotype         = UPIO_MEM32,
 805                 .regshift       = 2,
 806         },
 807         {
 808                 .mapbase        = DAVINCI_UART2_BASE,
 809                 .irq            = IRQ_DM646X_UARTINT2,
 810                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 811                                   UPF_IOREMAP,
 812                 .iotype         = UPIO_MEM32,
 813                 .regshift       = 2,
 814         },
 815         {
 816                 .flags          = 0
 817         },
 818 };
 819
 820 static struct platform_device dm646x_serial_device = {
 821         .name                   = "serial8250",
 822         .id                     = PLAT8250_DEV_PLATFORM,
 823         .dev                    = {
 824                 .platform_data  = dm646x_serial_platform_data,
 825         },
 826 };
 827
 828 static struct davinci_soc_info davinci_soc_info_dm646x = {
 829         .io_desc                = dm646x_io_desc,
 830         .io_desc_num            = ARRAY_SIZE(dm646x_io_desc),
 831         .jtag_id_reg            = 0x01c40028,
 832         .ids                    = dm646x_ids,
 833         .ids_num                = ARRAY_SIZE(dm646x_ids),
 834         .cpu_clks               = dm646x_clks,
 835         .psc_bases              = dm646x_psc_bases,
 836         .psc_bases_num          = ARRAY_SIZE(dm646x_psc_bases),
 837         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
 838         .pinmux_pins            = dm646x_pins,
 839         .pinmux_pins_num        = ARRAY_SIZE(dm646x_pins),
 840         .intc_base              = DAVINCI_ARM_INTC_BASE,
 841         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 842         .intc_irq_prios         = dm646x_default_priorities,
 843         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 844         .timer_info             = &dm646x_timer_info,
 845         .gpio_type              = GPIO_TYPE_DAVINCI,
 846         .gpio_base              = DAVINCI_GPIO_BASE,
 847         .gpio_num               = 43, /* Only 33 usable */
 848         .gpio_irq               = IRQ_DM646X_GPIOBNK0,
 849         .serial_dev             = &dm646x_serial_device,
 850         .emac_pdata             = &dm646x_emac_pdata,
 851         .sram_dma               = 0x10010000,
 852         .sram_len               = SZ_32K,
 853         .reset_device           = &davinci_wdt_device,
 854 };
 855
 856 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
 857 {
 858         dm646x_mcasp0_device.dev.platform_data = pdata;
 859         platform_device_register(&dm646x_mcasp0_device);
 860 }
 861
 862 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
 863 {
 864         dm646x_mcasp1_device.dev.platform_data = pdata;
 865         platform_device_register(&dm646x_mcasp1_device);
 866         platform_device_register(&dm646x_dit_device);
 867 }
 868
 869 void dm646x_setup_vpif(struct vpif_display_config *display_config,
 870                        struct vpif_capture_config *capture_config)
 871 {
 872         unsigned int value;
 873         void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
 874
 875         value = __raw_readl(base + VSCLKDIS_OFFSET);
 876         value &= ~VSCLKDIS_MASK;
 877         __raw_writel(value, base + VSCLKDIS_OFFSET);
 878
 879         value = __raw_readl(base + VDD3P3V_PWDN_OFFSET);
 880         value &= ~VDD3P3V_VID_MASK;
 881         __raw_writel(value, base + VDD3P3V_PWDN_OFFSET);
 882
 883         davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
 884         davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
 885         davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
 886         davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
 887
 888         vpif_display_dev.dev.platform_data = display_config;
 889         vpif_capture_dev.dev.platform_data = capture_config;
 890         platform_device_register(&vpif_dev);
 891         platform_device_register(&vpif_display_dev);
 892         platform_device_register(&vpif_capture_dev);
 893 }
 894
 895 int __init dm646x_init_edma(struct edma_rsv_info *rsv)
 896 {
 897         edma_cc0_info.rsv = rsv;
 898
 899         return platform_device_register(&dm646x_edma_device);
 900 }
 901
 902 void __init dm646x_init(void)
 903 {
 904         dm646x_board_setup_refclk(&ref_clk);
 905         davinci_common_init(&davinci_soc_info_dm646x);
 906 }
 907
 908 static int __init dm646x_init_devices(void)
 909 {
 910         if (!cpu_is_davinci_dm646x())
 911                 return 0;
 912
 913         platform_device_register(&dm646x_mdio_device);
 914         platform_device_register(&dm646x_emac_device);
 915         clk_add_alias(NULL, dev_name(&dm646x_mdio_device.dev),
 916                       NULL, &dm646x_emac_device.dev);
 917
 918         return 0;
 919 }
 920 postcore_initcall(dm646x_init_devices);