arch/arm/mach-davinci/dm355.c

   1 /*
   2  * TI DaVinci DM355 chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/clk.h>
  13 #include <linux/serial_8250.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/gpio.h>
  17
  18 #include <linux/spi/spi.h>
  19
  20 #include <asm/mach/map.h>
  21
  22 #include <mach/dm355.h>
  23 #include <mach/cputype.h>
  24 #include <mach/edma.h>
  25 #include <mach/psc.h>
  26 #include <mach/mux.h>
  27 #include <mach/irqs.h>
  28 #include <mach/time.h>
  29 #include <mach/serial.h>
  30 #include <mach/common.h>
  31 #include <mach/asp.h>
  32 #include <mach/spi.h>
  33
  34 #include "clock.h"
  35 #include "mux.h"
  36
  37 #define DM355_UART2_BASE        (IO_PHYS + 0x206000)
  38
  39 /*
  40  * Device specific clocks
  41  */
  42 #define DM355_REF_FREQ          24000000        /* 24 or 36 MHz */
  43
  44 static struct pll_data pll1_data = {
  45         .num       = 1,
  46         .phys_base = DAVINCI_PLL1_BASE,
  47         .flags     = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
  48 };
  49
  50 static struct pll_data pll2_data = {
  51         .num       = 2,
  52         .phys_base = DAVINCI_PLL2_BASE,
  53         .flags     = PLL_HAS_PREDIV,
  54 };
  55
  56 static struct clk ref_clk = {
  57         .name = "ref_clk",
  58         /* FIXME -- crystal rate is board-specific */
  59         .rate = DM355_REF_FREQ,
  60 };
  61
  62 static struct clk pll1_clk = {
  63         .name = "pll1",
  64         .parent = &ref_clk,
  65         .flags = CLK_PLL,
  66         .pll_data = &pll1_data,
  67 };
  68
  69 static struct clk pll1_aux_clk = {
  70         .name = "pll1_aux_clk",
  71         .parent = &pll1_clk,
  72         .flags = CLK_PLL | PRE_PLL,
  73 };
  74
  75 static struct clk pll1_sysclk1 = {
  76         .name = "pll1_sysclk1",
  77         .parent = &pll1_clk,
  78         .flags = CLK_PLL,
  79         .div_reg = PLLDIV1,
  80 };
  81
  82 static struct clk pll1_sysclk2 = {
  83         .name = "pll1_sysclk2",
  84         .parent = &pll1_clk,
  85         .flags = CLK_PLL,
  86         .div_reg = PLLDIV2,
  87 };
  88
  89 static struct clk pll1_sysclk3 = {
  90         .name = "pll1_sysclk3",
  91         .parent = &pll1_clk,
  92         .flags = CLK_PLL,
  93         .div_reg = PLLDIV3,
  94 };
  95
  96 static struct clk pll1_sysclk4 = {
  97         .name = "pll1_sysclk4",
  98         .parent = &pll1_clk,
  99         .flags = CLK_PLL,
 100         .div_reg = PLLDIV4,
 101 };
 102
 103 static struct clk pll1_sysclkbp = {
 104         .name = "pll1_sysclkbp",
 105         .parent = &pll1_clk,
 106         .flags = CLK_PLL | PRE_PLL,
 107         .div_reg = BPDIV
 108 };
 109
 110 static struct clk vpss_dac_clk = {
 111         .name = "vpss_dac",
 112         .parent = &pll1_sysclk3,
 113         .lpsc = DM355_LPSC_VPSS_DAC,
 114 };
 115
 116 static struct clk vpss_master_clk = {
 117         .name = "vpss_master",
 118         .parent = &pll1_sysclk4,
 119         .lpsc = DAVINCI_LPSC_VPSSMSTR,
 120         .flags = CLK_PSC,
 121 };
 122
 123 static struct clk vpss_slave_clk = {
 124         .name = "vpss_slave",
 125         .parent = &pll1_sysclk4,
 126         .lpsc = DAVINCI_LPSC_VPSSSLV,
 127 };
 128
 129 static struct clk clkout1_clk = {
 130         .name = "clkout1",
 131         .parent = &pll1_aux_clk,
 132         /* NOTE:  clkout1 can be externally gated by muxing GPIO-18 */
 133 };
 134
 135 static struct clk clkout2_clk = {
 136         .name = "clkout2",
 137         .parent = &pll1_sysclkbp,
 138 };
 139
 140 static struct clk pll2_clk = {
 141         .name = "pll2",
 142         .parent = &ref_clk,
 143         .flags = CLK_PLL,
 144         .pll_data = &pll2_data,
 145 };
 146
 147 static struct clk pll2_sysclk1 = {
 148         .name = "pll2_sysclk1",
 149         .parent = &pll2_clk,
 150         .flags = CLK_PLL,
 151         .div_reg = PLLDIV1,
 152 };
 153
 154 static struct clk pll2_sysclkbp = {
 155         .name = "pll2_sysclkbp",
 156         .parent = &pll2_clk,
 157         .flags = CLK_PLL | PRE_PLL,
 158         .div_reg = BPDIV
 159 };
 160
 161 static struct clk clkout3_clk = {
 162         .name = "clkout3",
 163         .parent = &pll2_sysclkbp,
 164         /* NOTE:  clkout3 can be externally gated by muxing GPIO-16 */
 165 };
 166
 167 static struct clk arm_clk = {
 168         .name = "arm_clk",
 169         .parent = &pll1_sysclk1,
 170         .lpsc = DAVINCI_LPSC_ARM,
 171         .flags = ALWAYS_ENABLED,
 172 };
 173
 174 /*
 175  * NOT LISTED below, and not touched by Linux
 176  *   - in SyncReset state by default
 177  *      .lpsc = DAVINCI_LPSC_TPCC,
 178  *      .lpsc = DAVINCI_LPSC_TPTC0,
 179  *      .lpsc = DAVINCI_LPSC_TPTC1,
 180  *      .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
 181  *      .lpsc = DAVINCI_LPSC_MEMSTICK,
 182  *   - in Enabled state by default
 183  *      .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
 184  *      .lpsc = DAVINCI_LPSC_SCR2,      // "bus"
 185  *      .lpsc = DAVINCI_LPSC_SCR3,      // "bus"
 186  *      .lpsc = DAVINCI_LPSC_SCR4,      // "bus"
 187  *      .lpsc = DAVINCI_LPSC_CROSSBAR,  // "emulation"
 188  *      .lpsc = DAVINCI_LPSC_CFG27,     // "test"
 189  *      .lpsc = DAVINCI_LPSC_CFG3,      // "test"
 190  *      .lpsc = DAVINCI_LPSC_CFG5,      // "test"
 191  */
 192
 193 static struct clk mjcp_clk = {
 194         .name = "mjcp",
 195         .parent = &pll1_sysclk1,
 196         .lpsc = DAVINCI_LPSC_IMCOP,
 197 };
 198
 199 static struct clk uart0_clk = {
 200         .name = "uart0",
 201         .parent = &pll1_aux_clk,
 202         .lpsc = DAVINCI_LPSC_UART0,
 203 };
 204
 205 static struct clk uart1_clk = {
 206         .name = "uart1",
 207         .parent = &pll1_aux_clk,
 208         .lpsc = DAVINCI_LPSC_UART1,
 209 };
 210
 211 static struct clk uart2_clk = {
 212         .name = "uart2",
 213         .parent = &pll1_sysclk2,
 214         .lpsc = DAVINCI_LPSC_UART2,
 215 };
 216
 217 static struct clk i2c_clk = {
 218         .name = "i2c",
 219         .parent = &pll1_aux_clk,
 220         .lpsc = DAVINCI_LPSC_I2C,
 221 };
 222
 223 static struct clk asp0_clk = {
 224         .name = "asp0",
 225         .parent = &pll1_sysclk2,
 226         .lpsc = DAVINCI_LPSC_McBSP,
 227 };
 228
 229 static struct clk asp1_clk = {
 230         .name = "asp1",
 231         .parent = &pll1_sysclk2,
 232         .lpsc = DM355_LPSC_McBSP1,
 233 };
 234
 235 static struct clk mmcsd0_clk = {
 236         .name = "mmcsd0",
 237         .parent = &pll1_sysclk2,
 238         .lpsc = DAVINCI_LPSC_MMC_SD,
 239 };
 240
 241 static struct clk mmcsd1_clk = {
 242         .name = "mmcsd1",
 243         .parent = &pll1_sysclk2,
 244         .lpsc = DM355_LPSC_MMC_SD1,
 245 };
 246
 247 static struct clk spi0_clk = {
 248         .name = "spi0",
 249         .parent = &pll1_sysclk2,
 250         .lpsc = DAVINCI_LPSC_SPI,
 251 };
 252
 253 static struct clk spi1_clk = {
 254         .name = "spi1",
 255         .parent = &pll1_sysclk2,
 256         .lpsc = DM355_LPSC_SPI1,
 257 };
 258
 259 static struct clk spi2_clk = {
 260         .name = "spi2",
 261         .parent = &pll1_sysclk2,
 262         .lpsc = DM355_LPSC_SPI2,
 263 };
 264
 265 static struct clk gpio_clk = {
 266         .name = "gpio",
 267         .parent = &pll1_sysclk2,
 268         .lpsc = DAVINCI_LPSC_GPIO,
 269 };
 270
 271 static struct clk aemif_clk = {
 272         .name = "aemif",
 273         .parent = &pll1_sysclk2,
 274         .lpsc = DAVINCI_LPSC_AEMIF,
 275 };
 276
 277 static struct clk pwm0_clk = {
 278         .name = "pwm0",
 279         .parent = &pll1_aux_clk,
 280         .lpsc = DAVINCI_LPSC_PWM0,
 281 };
 282
 283 static struct clk pwm1_clk = {
 284         .name = "pwm1",
 285         .parent = &pll1_aux_clk,
 286         .lpsc = DAVINCI_LPSC_PWM1,
 287 };
 288
 289 static struct clk pwm2_clk = {
 290         .name = "pwm2",
 291         .parent = &pll1_aux_clk,
 292         .lpsc = DAVINCI_LPSC_PWM2,
 293 };
 294
 295 static struct clk pwm3_clk = {
 296         .name = "pwm3",
 297         .parent = &pll1_aux_clk,
 298         .lpsc = DM355_LPSC_PWM3,
 299 };
 300
 301 static struct clk timer0_clk = {
 302         .name = "timer0",
 303         .parent = &pll1_aux_clk,
 304         .lpsc = DAVINCI_LPSC_TIMER0,
 305 };
 306
 307 static struct clk timer1_clk = {
 308         .name = "timer1",
 309         .parent = &pll1_aux_clk,
 310         .lpsc = DAVINCI_LPSC_TIMER1,
 311 };
 312
 313 static struct clk timer2_clk = {
 314         .name = "timer2",
 315         .parent = &pll1_aux_clk,
 316         .lpsc = DAVINCI_LPSC_TIMER2,
 317         .usecount = 1,              /* REVISIT: why cant' this be disabled? */
 318 };
 319
 320 static struct clk timer3_clk = {
 321         .name = "timer3",
 322         .parent = &pll1_aux_clk,
 323         .lpsc = DM355_LPSC_TIMER3,
 324 };
 325
 326 static struct clk rto_clk = {
 327         .name = "rto",
 328         .parent = &pll1_aux_clk,
 329         .lpsc = DM355_LPSC_RTO,
 330 };
 331
 332 static struct clk usb_clk = {
 333         .name = "usb",
 334         .parent = &pll1_sysclk2,
 335         .lpsc = DAVINCI_LPSC_USB,
 336 };
 337
 338 static struct clk_lookup dm355_clks[] = {
 339         CLK(NULL, "ref", &ref_clk),
 340         CLK(NULL, "pll1", &pll1_clk),
 341         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
 342         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
 343         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
 344         CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
 345         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 346         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
 347         CLK(NULL, "vpss_dac", &vpss_dac_clk),
 348         CLK(NULL, "vpss_master", &vpss_master_clk),
 349         CLK(NULL, "vpss_slave", &vpss_slave_clk),
 350         CLK(NULL, "clkout1", &clkout1_clk),
 351         CLK(NULL, "clkout2", &clkout2_clk),
 352         CLK(NULL, "pll2", &pll2_clk),
 353         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 354         CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
 355         CLK(NULL, "clkout3", &clkout3_clk),
 356         CLK(NULL, "arm", &arm_clk),
 357         CLK(NULL, "mjcp", &mjcp_clk),
 358         CLK(NULL, "uart0", &uart0_clk),
 359         CLK(NULL, "uart1", &uart1_clk),
 360         CLK(NULL, "uart2", &uart2_clk),
 361         CLK("i2c_davinci.1", NULL, &i2c_clk),
 362         CLK("davinci-asp.0", NULL, &asp0_clk),
 363         CLK("davinci-asp.1", NULL, &asp1_clk),
 364         CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
 365         CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
 366         CLK("spi_davinci.0", NULL, &spi0_clk),
 367         CLK("spi_davinci.1", NULL, &spi1_clk),
 368         CLK("spi_davinci.2", NULL, &spi2_clk),
 369         CLK(NULL, "gpio", &gpio_clk),
 370         CLK(NULL, "aemif", &aemif_clk),
 371         CLK(NULL, "pwm0", &pwm0_clk),
 372         CLK(NULL, "pwm1", &pwm1_clk),
 373         CLK(NULL, "pwm2", &pwm2_clk),
 374         CLK(NULL, "pwm3", &pwm3_clk),
 375         CLK(NULL, "timer0", &timer0_clk),
 376         CLK(NULL, "timer1", &timer1_clk),
 377         CLK("watchdog", NULL, &timer2_clk),
 378         CLK(NULL, "timer3", &timer3_clk),
 379         CLK(NULL, "rto", &rto_clk),
 380         CLK(NULL, "usb", &usb_clk),
 381         CLK(NULL, NULL, NULL),
 382 };
 383
 384 /*----------------------------------------------------------------------*/
 385
 386 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
 387
 388 static struct resource dm355_spi0_resources[] = {
 389         {
 390                 .start = 0x01c66000,
 391                 .end   = 0x01c667ff,
 392                 .flags = IORESOURCE_MEM,
 393         },
 394         {
 395                 .start = IRQ_DM355_SPINT0_0,
 396                 .flags = IORESOURCE_IRQ,
 397         },
 398         {
 399                 .start = 17,
 400                 .flags = IORESOURCE_DMA,
 401         },
 402         {
 403                 .start = 16,
 404                 .flags = IORESOURCE_DMA,
 405         },
 406         {
 407                 .start = EVENTQ_1,
 408                 .flags = IORESOURCE_DMA,
 409         },
 410 };
 411
 412 static struct davinci_spi_platform_data dm355_spi0_pdata = {
 413         .version        = SPI_VERSION_1,
 414         .num_chipselect = 2,
 415         .clk_internal   = 1,
 416         .cs_hold        = 1,
 417         .intr_level     = 0,
 418         .poll_mode      = 1,    /* 0 -> interrupt mode 1-> polling mode */
 419         .c2tdelay       = 0,
 420         .t2cdelay       = 0,
 421 };
 422 static struct platform_device dm355_spi0_device = {
 423         .name = "spi_davinci",
 424         .id = 0,
 425         .dev = {
 426                 .dma_mask = &dm355_spi0_dma_mask,
 427                 .coherent_dma_mask = DMA_BIT_MASK(32),
 428                 .platform_data = &dm355_spi0_pdata,
 429         },
 430         .num_resources = ARRAY_SIZE(dm355_spi0_resources),
 431         .resource = dm355_spi0_resources,
 432 };
 433
 434 void __init dm355_init_spi0(unsigned chipselect_mask,
 435                 struct spi_board_info *info, unsigned len)
 436 {
 437         /* for now, assume we need MISO */
 438         davinci_cfg_reg(DM355_SPI0_SDI);
 439
 440         /* not all slaves will be wired up */
 441         if (chipselect_mask & BIT(0))
 442                 davinci_cfg_reg(DM355_SPI0_SDENA0);
 443         if (chipselect_mask & BIT(1))
 444                 davinci_cfg_reg(DM355_SPI0_SDENA1);
 445
 446         spi_register_board_info(info, len);
 447
 448         platform_device_register(&dm355_spi0_device);
 449 }
 450
 451 /*----------------------------------------------------------------------*/
 452
 453 #define INTMUX          0x18
 454 #define EVTMUX          0x1c
 455
 456 /*
 457  * Device specific mux setup
 458  *
 459  *      soc     description     mux  mode   mode  mux    dbg
 460  *                              reg  offset mask  mode
 461  */
 462 static const struct mux_config dm355_pins[] = {
 463 #ifdef CONFIG_DAVINCI_MUX
 464 MUX_CFG(DM355,  MMCSD0,         4,   2,     1,    0,     false)
 465
 466 MUX_CFG(DM355,  SD1_CLK,        3,   6,     1,    1,     false)
 467 MUX_CFG(DM355,  SD1_CMD,        3,   7,     1,    1,     false)
 468 MUX_CFG(DM355,  SD1_DATA3,      3,   8,     3,    1,     false)
 469 MUX_CFG(DM355,  SD1_DATA2,      3,   10,    3,    1,     false)
 470 MUX_CFG(DM355,  SD1_DATA1,      3,   12,    3,    1,     false)
 471 MUX_CFG(DM355,  SD1_DATA0,      3,   14,    3,    1,     false)
 472
 473 MUX_CFG(DM355,  I2C_SDA,        3,   19,    1,    1,     false)
 474 MUX_CFG(DM355,  I2C_SCL,        3,   20,    1,    1,     false)
 475
 476 MUX_CFG(DM355,  MCBSP0_BDX,     3,   0,     1,    1,     false)
 477 MUX_CFG(DM355,  MCBSP0_X,       3,   1,     1,    1,     false)
 478 MUX_CFG(DM355,  MCBSP0_BFSX,    3,   2,     1,    1,     false)
 479 MUX_CFG(DM355,  MCBSP0_BDR,     3,   3,     1,    1,     false)
 480 MUX_CFG(DM355,  MCBSP0_R,       3,   4,     1,    1,     false)
 481 MUX_CFG(DM355,  MCBSP0_BFSR,    3,   5,     1,    1,     false)
 482
 483 MUX_CFG(DM355,  SPI0_SDI,       4,   1,     1,    0,     false)
 484 MUX_CFG(DM355,  SPI0_SDENA0,    4,   0,     1,    0,     false)
 485 MUX_CFG(DM355,  SPI0_SDENA1,    3,   28,    1,    1,     false)
 486
 487 INT_CFG(DM355,  INT_EDMA_CC,          2,    1,    1,     false)
 488 INT_CFG(DM355,  INT_EDMA_TC0_ERR,     3,    1,    1,     false)
 489 INT_CFG(DM355,  INT_EDMA_TC1_ERR,     4,    1,    1,     false)
 490
 491 EVT_CFG(DM355,  EVT8_ASP1_TX,         0,    1,    0,     false)
 492 EVT_CFG(DM355,  EVT9_ASP1_RX,         1,    1,    0,     false)
 493 EVT_CFG(DM355,  EVT26_MMC0_RX,        2,    1,    0,     false)
 494
 495 MUX_CFG(DM355,  VOUT_FIELD,     1,   18,    3,    1,     false)
 496 MUX_CFG(DM355,  VOUT_FIELD_G70, 1,   18,    3,    0,     false)
 497 MUX_CFG(DM355,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
 498 MUX_CFG(DM355,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
 499 MUX_CFG(DM355,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
 500
 501 MUX_CFG(DM355,  VIN_PCLK,       0,   14,    1,    1,     false)
 502 MUX_CFG(DM355,  VIN_CAM_WEN,    0,   13,    1,    1,     false)
 503 MUX_CFG(DM355,  VIN_CAM_VD,     0,   12,    1,    1,     false)
 504 MUX_CFG(DM355,  VIN_CAM_HD,     0,   11,    1,    1,     false)
 505 MUX_CFG(DM355,  VIN_YIN_EN,     0,   10,    1,    1,     false)
 506 MUX_CFG(DM355,  VIN_CINL_EN,    0,   0,   0xff, 0x55,    false)
 507 MUX_CFG(DM355,  VIN_CINH_EN,    0,   8,     3,    3,     false)
 508 #endif
 509 };
 510
 511 static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 512         [IRQ_DM355_CCDC_VDINT0]         = 2,
 513         [IRQ_DM355_CCDC_VDINT1]         = 6,
 514         [IRQ_DM355_CCDC_VDINT2]         = 6,
 515         [IRQ_DM355_IPIPE_HST]           = 6,
 516         [IRQ_DM355_H3AINT]              = 6,
 517         [IRQ_DM355_IPIPE_SDR]           = 6,
 518         [IRQ_DM355_IPIPEIFINT]          = 6,
 519         [IRQ_DM355_OSDINT]              = 7,
 520         [IRQ_DM355_VENCINT]             = 6,
 521         [IRQ_ASQINT]                    = 6,
 522         [IRQ_IMXINT]                    = 6,
 523         [IRQ_USBINT]                    = 4,
 524         [IRQ_DM355_RTOINT]              = 4,
 525         [IRQ_DM355_UARTINT2]            = 7,
 526         [IRQ_DM355_TINT6]               = 7,
 527         [IRQ_CCINT0]                    = 5,    /* dma */
 528         [IRQ_CCERRINT]                  = 5,    /* dma */
 529         [IRQ_TCERRINT0]                 = 5,    /* dma */
 530         [IRQ_TCERRINT]                  = 5,    /* dma */
 531         [IRQ_DM355_SPINT2_1]            = 7,
 532         [IRQ_DM355_TINT7]               = 4,
 533         [IRQ_DM355_SDIOINT0]            = 7,
 534         [IRQ_MBXINT]                    = 7,
 535         [IRQ_MBRINT]                    = 7,
 536         [IRQ_MMCINT]                    = 7,
 537         [IRQ_DM355_MMCINT1]             = 7,
 538         [IRQ_DM355_PWMINT3]             = 7,
 539         [IRQ_DDRINT]                    = 7,
 540         [IRQ_AEMIFINT]                  = 7,
 541         [IRQ_DM355_SDIOINT1]            = 4,
 542         [IRQ_TINT0_TINT12]              = 2,    /* clockevent */
 543         [IRQ_TINT0_TINT34]              = 2,    /* clocksource */
 544         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 545         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 546         [IRQ_PWMINT0]                   = 7,
 547         [IRQ_PWMINT1]                   = 7,
 548         [IRQ_PWMINT2]                   = 7,
 549         [IRQ_I2C]                       = 3,
 550         [IRQ_UARTINT0]                  = 3,
 551         [IRQ_UARTINT1]                  = 3,
 552         [IRQ_DM355_SPINT0_0]            = 3,
 553         [IRQ_DM355_SPINT0_1]            = 3,
 554         [IRQ_DM355_GPIO0]               = 3,
 555         [IRQ_DM355_GPIO1]               = 7,
 556         [IRQ_DM355_GPIO2]               = 4,
 557         [IRQ_DM355_GPIO3]               = 4,
 558         [IRQ_DM355_GPIO4]               = 7,
 559         [IRQ_DM355_GPIO5]               = 7,
 560         [IRQ_DM355_GPIO6]               = 7,
 561         [IRQ_DM355_GPIO7]               = 7,
 562         [IRQ_DM355_GPIO8]               = 7,
 563         [IRQ_DM355_GPIO9]               = 7,
 564         [IRQ_DM355_GPIOBNK0]            = 7,
 565         [IRQ_DM355_GPIOBNK1]            = 7,
 566         [IRQ_DM355_GPIOBNK2]            = 7,
 567         [IRQ_DM355_GPIOBNK3]            = 7,
 568         [IRQ_DM355_GPIOBNK4]            = 7,
 569         [IRQ_DM355_GPIOBNK5]            = 7,
 570         [IRQ_DM355_GPIOBNK6]            = 7,
 571         [IRQ_COMMTX]                    = 7,
 572         [IRQ_COMMRX]                    = 7,
 573         [IRQ_EMUINT]                    = 7,
 574 };
 575
 576 /*----------------------------------------------------------------------*/
 577
 578 static const s8
 579 queue_tc_mapping[][2] = {
 580         /* {event queue no, TC no} */
 581         {0, 0},
 582         {1, 1},
 583         {-1, -1},
 584 };
 585
 586 static const s8
 587 queue_priority_mapping[][2] = {
 588         /* {event queue no, Priority} */
 589         {0, 3},
 590         {1, 7},
 591         {-1, -1},
 592 };
 593
 594 static struct edma_soc_info edma_cc0_info = {
 595         .n_channel              = 64,
 596         .n_region               = 4,
 597         .n_slot                 = 128,
 598         .n_tc                   = 2,
 599         .n_cc                   = 1,
 600         .queue_tc_mapping       = queue_tc_mapping,
 601         .queue_priority_mapping = queue_priority_mapping,
 602 };
 603
 604 static struct edma_soc_info *dm355_edma_info[EDMA_MAX_CC] = {
 605        &edma_cc0_info,
 606 };
 607
 608 static struct resource edma_resources[] = {
 609         {
 610                 .name   = "edma_cc0",
 611                 .start  = 0x01c00000,
 612                 .end    = 0x01c00000 + SZ_64K - 1,
 613                 .flags  = IORESOURCE_MEM,
 614         },
 615         {
 616                 .name   = "edma_tc0",
 617                 .start  = 0x01c10000,
 618                 .end    = 0x01c10000 + SZ_1K - 1,
 619                 .flags  = IORESOURCE_MEM,
 620         },
 621         {
 622                 .name   = "edma_tc1",
 623                 .start  = 0x01c10400,
 624                 .end    = 0x01c10400 + SZ_1K - 1,
 625                 .flags  = IORESOURCE_MEM,
 626         },
 627         {
 628                 .name   = "edma0",
 629                 .start  = IRQ_CCINT0,
 630                 .flags  = IORESOURCE_IRQ,
 631         },
 632         {
 633                 .name   = "edma0_err",
 634                 .start  = IRQ_CCERRINT,
 635                 .flags  = IORESOURCE_IRQ,
 636         },
 637         /* not using (or muxing) TC*_ERR */
 638 };
 639
 640 static struct platform_device dm355_edma_device = {
 641         .name                   = "edma",
 642         .id                     = 0,
 643         .dev.platform_data      = dm355_edma_info,
 644         .num_resources          = ARRAY_SIZE(edma_resources),
 645         .resource               = edma_resources,
 646 };
 647
 648 static struct resource dm355_asp1_resources[] = {
 649         {
 650                 .start  = DAVINCI_ASP1_BASE,
 651                 .end    = DAVINCI_ASP1_BASE + SZ_8K - 1,
 652                 .flags  = IORESOURCE_MEM,
 653         },
 654         {
 655                 .start  = DAVINCI_DMA_ASP1_TX,
 656                 .end    = DAVINCI_DMA_ASP1_TX,
 657                 .flags  = IORESOURCE_DMA,
 658         },
 659         {
 660                 .start  = DAVINCI_DMA_ASP1_RX,
 661                 .end    = DAVINCI_DMA_ASP1_RX,
 662                 .flags  = IORESOURCE_DMA,
 663         },
 664 };
 665
 666 static struct platform_device dm355_asp1_device = {
 667         .name           = "davinci-asp",
 668         .id             = 1,
 669         .num_resources  = ARRAY_SIZE(dm355_asp1_resources),
 670         .resource       = dm355_asp1_resources,
 671 };
 672
 673 static void dm355_ccdc_setup_pinmux(void)
 674 {
 675         davinci_cfg_reg(DM355_VIN_PCLK);
 676         davinci_cfg_reg(DM355_VIN_CAM_WEN);
 677         davinci_cfg_reg(DM355_VIN_CAM_VD);
 678         davinci_cfg_reg(DM355_VIN_CAM_HD);
 679         davinci_cfg_reg(DM355_VIN_YIN_EN);
 680         davinci_cfg_reg(DM355_VIN_CINL_EN);
 681         davinci_cfg_reg(DM355_VIN_CINH_EN);
 682 }
 683
 684 static struct resource dm355_vpss_resources[] = {
 685         {
 686                 /* VPSS BL Base address */
 687                 .name           = "vpss",
 688                 .start          = 0x01c70800,
 689                 .end            = 0x01c70800 + 0xff,
 690                 .flags          = IORESOURCE_MEM,
 691         },
 692         {
 693                 /* VPSS CLK Base address */
 694                 .name           = "vpss",
 695                 .start          = 0x01c70000,
 696                 .end            = 0x01c70000 + 0xf,
 697                 .flags          = IORESOURCE_MEM,
 698         },
 699 };
 700
 701 static struct platform_device dm355_vpss_device = {
 702         .name                   = "vpss",
 703         .id                     = -1,
 704         .dev.platform_data      = "dm355_vpss",
 705         .num_resources          = ARRAY_SIZE(dm355_vpss_resources),
 706         .resource               = dm355_vpss_resources,
 707 };
 708
 709 static struct resource vpfe_resources[] = {
 710         {
 711                 .start          = IRQ_VDINT0,
 712                 .end            = IRQ_VDINT0,
 713                 .flags          = IORESOURCE_IRQ,
 714         },
 715         {
 716                 .start          = IRQ_VDINT1,
 717                 .end            = IRQ_VDINT1,
 718                 .flags          = IORESOURCE_IRQ,
 719         },
 720 };
 721
 722 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
 723 static struct resource dm355_ccdc_resource[] = {
 724         /* CCDC Base address */
 725         {
 726                 .flags          = IORESOURCE_MEM,
 727                 .start          = 0x01c70600,
 728                 .end            = 0x01c70600 + 0x1ff,
 729         },
 730 };
 731 static struct platform_device dm355_ccdc_dev = {
 732         .name           = "dm355_ccdc",
 733         .id             = -1,
 734         .num_resources  = ARRAY_SIZE(dm355_ccdc_resource),
 735         .resource       = dm355_ccdc_resource,
 736         .dev = {
 737                 .dma_mask               = &vpfe_capture_dma_mask,
 738                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 739                 .platform_data          = dm355_ccdc_setup_pinmux,
 740         },
 741 };
 742
 743 static struct platform_device vpfe_capture_dev = {
 744         .name           = CAPTURE_DRV_NAME,
 745         .id             = -1,
 746         .num_resources  = ARRAY_SIZE(vpfe_resources),
 747         .resource       = vpfe_resources,
 748         .dev = {
 749                 .dma_mask               = &vpfe_capture_dma_mask,
 750                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 751         },
 752 };
 753
 754 void dm355_set_vpfe_config(struct vpfe_config *cfg)
 755 {
 756         vpfe_capture_dev.dev.platform_data = cfg;
 757 }
 758
 759 /*----------------------------------------------------------------------*/
 760
 761 static struct map_desc dm355_io_desc[] = {
 762         {
 763                 .virtual        = IO_VIRT,
 764                 .pfn            = __phys_to_pfn(IO_PHYS),
 765                 .length         = IO_SIZE,
 766                 .type           = MT_DEVICE
 767         },
 768         {
 769                 .virtual        = SRAM_VIRT,
 770                 .pfn            = __phys_to_pfn(0x00010000),
 771                 .length         = SZ_32K,
 772                 .type           = MT_MEMORY_NONCACHED,
 773         },
 774 };
 775
 776 /* Contents of JTAG ID register used to identify exact cpu type */
 777 static struct davinci_id dm355_ids[] = {
 778         {
 779                 .variant        = 0x0,
 780                 .part_no        = 0xb73b,
 781                 .manufacturer   = 0x00f,
 782                 .cpu_id         = DAVINCI_CPU_ID_DM355,
 783                 .name           = "dm355",
 784         },
 785 };
 786
 787 static u32 dm355_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
 788
 789 /*
 790  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 791  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 792  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 793  * T1_TOP: Timer 1, top   :  <unused>
 794  */
 795 static struct davinci_timer_info dm355_timer_info = {
 796         .timers         = davinci_timer_instance,
 797         .clockevent_id  = T0_BOT,
 798         .clocksource_id = T0_TOP,
 799 };
 800
 801 static struct plat_serial8250_port dm355_serial_platform_data[] = {
 802         {
 803                 .mapbase        = DAVINCI_UART0_BASE,
 804                 .irq            = IRQ_UARTINT0,
 805                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 806                                   UPF_IOREMAP,
 807                 .iotype         = UPIO_MEM,
 808                 .regshift       = 2,
 809         },
 810         {
 811                 .mapbase        = DAVINCI_UART1_BASE,
 812                 .irq            = IRQ_UARTINT1,
 813                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 814                                   UPF_IOREMAP,
 815                 .iotype         = UPIO_MEM,
 816                 .regshift       = 2,
 817         },
 818         {
 819                 .mapbase        = DM355_UART2_BASE,
 820                 .irq            = IRQ_DM355_UARTINT2,
 821                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 822                                   UPF_IOREMAP,
 823                 .iotype         = UPIO_MEM,
 824                 .regshift       = 2,
 825         },
 826         {
 827                 .flags          = 0
 828         },
 829 };
 830
 831 static struct platform_device dm355_serial_device = {
 832         .name                   = "serial8250",
 833         .id                     = PLAT8250_DEV_PLATFORM,
 834         .dev                    = {
 835                 .platform_data  = dm355_serial_platform_data,
 836         },
 837 };
 838
 839 static struct davinci_soc_info davinci_soc_info_dm355 = {
 840         .io_desc                = dm355_io_desc,
 841         .io_desc_num            = ARRAY_SIZE(dm355_io_desc),
 842         .jtag_id_reg            = 0x01c40028,
 843         .ids                    = dm355_ids,
 844         .ids_num                = ARRAY_SIZE(dm355_ids),
 845         .cpu_clks               = dm355_clks,
 846         .psc_bases              = dm355_psc_bases,
 847         .psc_bases_num          = ARRAY_SIZE(dm355_psc_bases),
 848         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
 849         .pinmux_pins            = dm355_pins,
 850         .pinmux_pins_num        = ARRAY_SIZE(dm355_pins),
 851         .intc_base              = DAVINCI_ARM_INTC_BASE,
 852         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 853         .intc_irq_prios         = dm355_default_priorities,
 854         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 855         .timer_info             = &dm355_timer_info,
 856         .gpio_type              = GPIO_TYPE_DAVINCI,
 857         .gpio_base              = DAVINCI_GPIO_BASE,
 858         .gpio_num               = 104,
 859         .gpio_irq               = IRQ_DM355_GPIOBNK0,
 860         .serial_dev             = &dm355_serial_device,
 861         .sram_dma               = 0x00010000,
 862         .sram_len               = SZ_32K,
 863         .reset_device           = &davinci_wdt_device,
 864 };
 865
 866 void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
 867 {
 868         /* we don't use ASP1 IRQs, or we'd need to mux them ... */
 869         if (evt_enable & ASP1_TX_EVT_EN)
 870                 davinci_cfg_reg(DM355_EVT8_ASP1_TX);
 871
 872         if (evt_enable & ASP1_RX_EVT_EN)
 873                 davinci_cfg_reg(DM355_EVT9_ASP1_RX);
 874
 875         dm355_asp1_device.dev.platform_data = pdata;
 876         platform_device_register(&dm355_asp1_device);
 877 }
 878
 879 void __init dm355_init(void)
 880 {
 881         davinci_common_init(&davinci_soc_info_dm355);
 882 }
 883
 884 static int __init dm355_init_devices(void)
 885 {
 886         if (!cpu_is_davinci_dm355())
 887                 return 0;
 888
 889         /* Add ccdc clock aliases */
 890         clk_add_alias("master", dm355_ccdc_dev.name, "vpss_master", NULL);
 891         clk_add_alias("slave", dm355_ccdc_dev.name, "vpss_master", NULL);
 892         davinci_cfg_reg(DM355_INT_EDMA_CC);
 893         platform_device_register(&dm355_edma_device);
 894         platform_device_register(&dm355_vpss_device);
 895         platform_device_register(&dm355_ccdc_dev);
 896         platform_device_register(&vpfe_capture_dev);
 897
 898         return 0;
 899 }
 900 postcore_initcall(dm355_init_devices);