arch/arm/mach-davinci/devices-da8xx.c

   1 /*
   2  * DA8XX/OMAP L1XX platform device data
   3  *
   4  * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
   5  * Derived from code that was:
   6  *      Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/serial_8250.h>
  17
  18 #include <mach/cputype.h>
  19 #include <mach/common.h>
  20 #include <mach/time.h>
  21 #include <mach/da8xx.h>
  22 #include <mach/cpuidle.h>
  23
  24 #include "clock.h"
  25
  26 #define DA8XX_TPCC_BASE                 0x01c00000
  27 #define DA850_MMCSD1_BASE               0x01e1b000
  28 #define DA850_TPCC1_BASE                0x01e30000
  29 #define DA8XX_TPTC0_BASE                0x01c08000
  30 #define DA8XX_TPTC1_BASE                0x01c08400
  31 #define DA850_TPTC2_BASE                0x01e38000
  32 #define DA8XX_WDOG_BASE                 0x01c21000 /* DA8XX_TIMER64P1_BASE */
  33 #define DA8XX_I2C0_BASE                 0x01c22000
  34 #define DA8XX_RTC_BASE                  0x01C23000
  35 #define DA8XX_EMAC_CPPI_PORT_BASE       0x01e20000
  36 #define DA8XX_EMAC_CPGMACSS_BASE        0x01e22000
  37 #define DA8XX_EMAC_CPGMAC_BASE          0x01e23000
  38 #define DA8XX_EMAC_MDIO_BASE            0x01e24000
  39 #define DA8XX_GPIO_BASE                 0x01e26000
  40 #define DA8XX_I2C1_BASE                 0x01e28000
  41 #define DA8XX_SPI0_BASE                 0x01c41000
  42 #define DA8XX_SPI1_BASE                 0x01f0e000
  43
  44 #define DA8XX_EMAC_CTRL_REG_OFFSET      0x3000
  45 #define DA8XX_EMAC_MOD_REG_OFFSET       0x2000
  46 #define DA8XX_EMAC_RAM_OFFSET           0x0000
  47 #define DA8XX_EMAC_CTRL_RAM_SIZE        SZ_8K
  48
  49 #define DA8XX_DMA_SPI0_RX       EDMA_CTLR_CHAN(0, 14)
  50 #define DA8XX_DMA_SPI0_TX       EDMA_CTLR_CHAN(0, 15)
  51 #define DA8XX_DMA_MMCSD0_RX     EDMA_CTLR_CHAN(0, 16)
  52 #define DA8XX_DMA_MMCSD0_TX     EDMA_CTLR_CHAN(0, 17)
  53 #define DA8XX_DMA_SPI1_RX       EDMA_CTLR_CHAN(0, 18)
  54 #define DA8XX_DMA_SPI1_TX       EDMA_CTLR_CHAN(0, 19)
  55 #define DA850_DMA_MMCSD1_RX     EDMA_CTLR_CHAN(1, 28)
  56 #define DA850_DMA_MMCSD1_TX     EDMA_CTLR_CHAN(1, 29)
  57
  58 void __iomem *da8xx_syscfg0_base;
  59 void __iomem *da8xx_syscfg1_base;
  60
  61 static struct plat_serial8250_port da8xx_serial_pdata[] = {
  62         {
  63                 .mapbase        = DA8XX_UART0_BASE,
  64                 .irq            = IRQ_DA8XX_UARTINT0,
  65                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  66                                         UPF_IOREMAP,
  67                 .iotype         = UPIO_MEM,
  68                 .regshift       = 2,
  69         },
  70         {
  71                 .mapbase        = DA8XX_UART1_BASE,
  72                 .irq            = IRQ_DA8XX_UARTINT1,
  73                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  74                                         UPF_IOREMAP,
  75                 .iotype         = UPIO_MEM,
  76                 .regshift       = 2,
  77         },
  78         {
  79                 .mapbase        = DA8XX_UART2_BASE,
  80                 .irq            = IRQ_DA8XX_UARTINT2,
  81                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  82                                         UPF_IOREMAP,
  83                 .iotype         = UPIO_MEM,
  84                 .regshift       = 2,
  85         },
  86         {
  87                 .flags  = 0,
  88         },
  89 };
  90
  91 struct platform_device da8xx_serial_device = {
  92         .name   = "serial8250",
  93         .id     = PLAT8250_DEV_PLATFORM,
  94         .dev    = {
  95                 .platform_data  = da8xx_serial_pdata,
  96         },
  97 };
  98
  99 static const s8 da8xx_queue_tc_mapping[][2] = {
 100         /* {event queue no, TC no} */
 101         {0, 0},
 102         {1, 1},
 103         {-1, -1}
 104 };
 105
 106 static const s8 da8xx_queue_priority_mapping[][2] = {
 107         /* {event queue no, Priority} */
 108         {0, 3},
 109         {1, 7},
 110         {-1, -1}
 111 };
 112
 113 static const s8 da850_queue_tc_mapping[][2] = {
 114         /* {event queue no, TC no} */
 115         {0, 0},
 116         {-1, -1}
 117 };
 118
 119 static const s8 da850_queue_priority_mapping[][2] = {
 120         /* {event queue no, Priority} */
 121         {0, 3},
 122         {-1, -1}
 123 };
 124
 125 static struct edma_soc_info da830_edma_cc0_info = {
 126         .n_channel              = 32,
 127         .n_region               = 4,
 128         .n_slot                 = 128,
 129         .n_tc                   = 2,
 130         .n_cc                   = 1,
 131         .queue_tc_mapping       = da8xx_queue_tc_mapping,
 132         .queue_priority_mapping = da8xx_queue_priority_mapping,
 133 };
 134
 135 static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
 136         &da830_edma_cc0_info,
 137 };
 138
 139 static struct edma_soc_info da850_edma_cc_info[] = {
 140         {
 141                 .n_channel              = 32,
 142                 .n_region               = 4,
 143                 .n_slot                 = 128,
 144                 .n_tc                   = 2,
 145                 .n_cc                   = 1,
 146                 .queue_tc_mapping       = da8xx_queue_tc_mapping,
 147                 .queue_priority_mapping = da8xx_queue_priority_mapping,
 148         },
 149         {
 150                 .n_channel              = 32,
 151                 .n_region               = 4,
 152                 .n_slot                 = 128,
 153                 .n_tc                   = 1,
 154                 .n_cc                   = 1,
 155                 .queue_tc_mapping       = da850_queue_tc_mapping,
 156                 .queue_priority_mapping = da850_queue_priority_mapping,
 157         },
 158 };
 159
 160 static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
 161         &da850_edma_cc_info[0],
 162         &da850_edma_cc_info[1],
 163 };
 164
 165 static struct resource da830_edma_resources[] = {
 166         {
 167                 .name   = "edma_cc0",
 168                 .start  = DA8XX_TPCC_BASE,
 169                 .end    = DA8XX_TPCC_BASE + SZ_32K - 1,
 170                 .flags  = IORESOURCE_MEM,
 171         },
 172         {
 173                 .name   = "edma_tc0",
 174                 .start  = DA8XX_TPTC0_BASE,
 175                 .end    = DA8XX_TPTC0_BASE + SZ_1K - 1,
 176                 .flags  = IORESOURCE_MEM,
 177         },
 178         {
 179                 .name   = "edma_tc1",
 180                 .start  = DA8XX_TPTC1_BASE,
 181                 .end    = DA8XX_TPTC1_BASE + SZ_1K - 1,
 182                 .flags  = IORESOURCE_MEM,
 183         },
 184         {
 185                 .name   = "edma0",
 186                 .start  = IRQ_DA8XX_CCINT0,
 187                 .flags  = IORESOURCE_IRQ,
 188         },
 189         {
 190                 .name   = "edma0_err",
 191                 .start  = IRQ_DA8XX_CCERRINT,
 192                 .flags  = IORESOURCE_IRQ,
 193         },
 194 };
 195
 196 static struct resource da850_edma_resources[] = {
 197         {
 198                 .name   = "edma_cc0",
 199                 .start  = DA8XX_TPCC_BASE,
 200                 .end    = DA8XX_TPCC_BASE + SZ_32K - 1,
 201                 .flags  = IORESOURCE_MEM,
 202         },
 203         {
 204                 .name   = "edma_tc0",
 205                 .start  = DA8XX_TPTC0_BASE,
 206                 .end    = DA8XX_TPTC0_BASE + SZ_1K - 1,
 207                 .flags  = IORESOURCE_MEM,
 208         },
 209         {
 210                 .name   = "edma_tc1",
 211                 .start  = DA8XX_TPTC1_BASE,
 212                 .end    = DA8XX_TPTC1_BASE + SZ_1K - 1,
 213                 .flags  = IORESOURCE_MEM,
 214         },
 215         {
 216                 .name   = "edma_cc1",
 217                 .start  = DA850_TPCC1_BASE,
 218                 .end    = DA850_TPCC1_BASE + SZ_32K - 1,
 219                 .flags  = IORESOURCE_MEM,
 220         },
 221         {
 222                 .name   = "edma_tc2",
 223                 .start  = DA850_TPTC2_BASE,
 224                 .end    = DA850_TPTC2_BASE + SZ_1K - 1,
 225                 .flags  = IORESOURCE_MEM,
 226         },
 227         {
 228                 .name   = "edma0",
 229                 .start  = IRQ_DA8XX_CCINT0,
 230                 .flags  = IORESOURCE_IRQ,
 231         },
 232         {
 233                 .name   = "edma0_err",
 234                 .start  = IRQ_DA8XX_CCERRINT,
 235                 .flags  = IORESOURCE_IRQ,
 236         },
 237         {
 238                 .name   = "edma1",
 239                 .start  = IRQ_DA850_CCINT1,
 240                 .flags  = IORESOURCE_IRQ,
 241         },
 242         {
 243                 .name   = "edma1_err",
 244                 .start  = IRQ_DA850_CCERRINT1,
 245                 .flags  = IORESOURCE_IRQ,
 246         },
 247 };
 248
 249 static struct platform_device da830_edma_device = {
 250         .name           = "edma",
 251         .id             = -1,
 252         .dev = {
 253                 .platform_data = da830_edma_info,
 254         },
 255         .num_resources  = ARRAY_SIZE(da830_edma_resources),
 256         .resource       = da830_edma_resources,
 257 };
 258
 259 static struct platform_device da850_edma_device = {
 260         .name           = "edma",
 261         .id             = -1,
 262         .dev = {
 263                 .platform_data = da850_edma_info,
 264         },
 265         .num_resources  = ARRAY_SIZE(da850_edma_resources),
 266         .resource       = da850_edma_resources,
 267 };
 268
 269 int __init da830_register_edma(struct edma_rsv_info *rsv)
 270 {
 271         da830_edma_cc0_info.rsv = rsv;
 272
 273         return platform_device_register(&da830_edma_device);
 274 }
 275
 276 int __init da850_register_edma(struct edma_rsv_info *rsv[2])
 277 {
 278         if (rsv) {
 279                 da850_edma_cc_info[0].rsv = rsv[0];
 280                 da850_edma_cc_info[1].rsv = rsv[1];
 281         }
 282
 283         return platform_device_register(&da850_edma_device);
 284 }
 285
 286 static struct resource da8xx_i2c_resources0[] = {
 287         {
 288                 .start  = DA8XX_I2C0_BASE,
 289                 .end    = DA8XX_I2C0_BASE + SZ_4K - 1,
 290                 .flags  = IORESOURCE_MEM,
 291         },
 292         {
 293                 .start  = IRQ_DA8XX_I2CINT0,
 294                 .end    = IRQ_DA8XX_I2CINT0,
 295                 .flags  = IORESOURCE_IRQ,
 296         },
 297 };
 298
 299 static struct platform_device da8xx_i2c_device0 = {
 300         .name           = "i2c_davinci",
 301         .id             = 1,
 302         .num_resources  = ARRAY_SIZE(da8xx_i2c_resources0),
 303         .resource       = da8xx_i2c_resources0,
 304 };
 305
 306 static struct resource da8xx_i2c_resources1[] = {
 307         {
 308                 .start  = DA8XX_I2C1_BASE,
 309                 .end    = DA8XX_I2C1_BASE + SZ_4K - 1,
 310                 .flags  = IORESOURCE_MEM,
 311         },
 312         {
 313                 .start  = IRQ_DA8XX_I2CINT1,
 314                 .end    = IRQ_DA8XX_I2CINT1,
 315                 .flags  = IORESOURCE_IRQ,
 316         },
 317 };
 318
 319 static struct platform_device da8xx_i2c_device1 = {
 320         .name           = "i2c_davinci",
 321         .id             = 2,
 322         .num_resources  = ARRAY_SIZE(da8xx_i2c_resources1),
 323         .resource       = da8xx_i2c_resources1,
 324 };
 325
 326 int __init da8xx_register_i2c(int instance,
 327                 struct davinci_i2c_platform_data *pdata)
 328 {
 329         struct platform_device *pdev;
 330
 331         if (instance == 0)
 332                 pdev = &da8xx_i2c_device0;
 333         else if (instance == 1)
 334                 pdev = &da8xx_i2c_device1;
 335         else
 336                 return -EINVAL;
 337
 338         pdev->dev.platform_data = pdata;
 339         return platform_device_register(pdev);
 340 }
 341
 342 static struct resource da8xx_watchdog_resources[] = {
 343         {
 344                 .start  = DA8XX_WDOG_BASE,
 345                 .end    = DA8XX_WDOG_BASE + SZ_4K - 1,
 346                 .flags  = IORESOURCE_MEM,
 347         },
 348 };
 349
 350 struct platform_device da8xx_wdt_device = {
 351         .name           = "watchdog",
 352         .id             = -1,
 353         .num_resources  = ARRAY_SIZE(da8xx_watchdog_resources),
 354         .resource       = da8xx_watchdog_resources,
 355 };
 356
 357 int __init da8xx_register_watchdog(void)
 358 {
 359         return platform_device_register(&da8xx_wdt_device);
 360 }
 361
 362 static struct resource da8xx_emac_resources[] = {
 363         {
 364                 .start  = DA8XX_EMAC_CPPI_PORT_BASE,
 365                 .end    = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
 366                 .flags  = IORESOURCE_MEM,
 367         },
 368         {
 369                 .start  = IRQ_DA8XX_C0_RX_THRESH_PULSE,
 370                 .end    = IRQ_DA8XX_C0_RX_THRESH_PULSE,
 371                 .flags  = IORESOURCE_IRQ,
 372         },
 373         {
 374                 .start  = IRQ_DA8XX_C0_RX_PULSE,
 375                 .end    = IRQ_DA8XX_C0_RX_PULSE,
 376                 .flags  = IORESOURCE_IRQ,
 377         },
 378         {
 379                 .start  = IRQ_DA8XX_C0_TX_PULSE,
 380                 .end    = IRQ_DA8XX_C0_TX_PULSE,
 381                 .flags  = IORESOURCE_IRQ,
 382         },
 383         {
 384                 .start  = IRQ_DA8XX_C0_MISC_PULSE,
 385                 .end    = IRQ_DA8XX_C0_MISC_PULSE,
 386                 .flags  = IORESOURCE_IRQ,
 387         },
 388 };
 389
 390 struct emac_platform_data da8xx_emac_pdata = {
 391         .ctrl_reg_offset        = DA8XX_EMAC_CTRL_REG_OFFSET,
 392         .ctrl_mod_reg_offset    = DA8XX_EMAC_MOD_REG_OFFSET,
 393         .ctrl_ram_offset        = DA8XX_EMAC_RAM_OFFSET,
 394         .ctrl_ram_size          = DA8XX_EMAC_CTRL_RAM_SIZE,
 395         .version                = EMAC_VERSION_2,
 396 };
 397
 398 static struct platform_device da8xx_emac_device = {
 399         .name           = "davinci_emac",
 400         .id             = 1,
 401         .dev = {
 402                 .platform_data  = &da8xx_emac_pdata,
 403         },
 404         .num_resources  = ARRAY_SIZE(da8xx_emac_resources),
 405         .resource       = da8xx_emac_resources,
 406 };
 407
 408 static struct resource da8xx_mdio_resources[] = {
 409         {
 410                 .start  = DA8XX_EMAC_MDIO_BASE,
 411                 .end    = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
 412                 .flags  = IORESOURCE_MEM,
 413         },
 414 };
 415
 416 static struct platform_device da8xx_mdio_device = {
 417         .name           = "davinci_mdio",
 418         .id             = 0,
 419         .num_resources  = ARRAY_SIZE(da8xx_mdio_resources),
 420         .resource       = da8xx_mdio_resources,
 421 };
 422
 423 int __init da8xx_register_emac(void)
 424 {
 425         int ret;
 426
 427         ret = platform_device_register(&da8xx_mdio_device);
 428         if (ret < 0)
 429                 return ret;
 430         ret = platform_device_register(&da8xx_emac_device);
 431         if (ret < 0)
 432                 return ret;
 433         ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev),
 434                             NULL, &da8xx_emac_device.dev);
 435         return ret;
 436 }
 437
 438 static struct resource da830_mcasp1_resources[] = {
 439         {
 440                 .name   = "mcasp1",
 441                 .start  = DAVINCI_DA830_MCASP1_REG_BASE,
 442                 .end    = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
 443                 .flags  = IORESOURCE_MEM,
 444         },
 445         /* TX event */
 446         {
 447                 .start  = DAVINCI_DA830_DMA_MCASP1_AXEVT,
 448                 .end    = DAVINCI_DA830_DMA_MCASP1_AXEVT,
 449                 .flags  = IORESOURCE_DMA,
 450         },
 451         /* RX event */
 452         {
 453                 .start  = DAVINCI_DA830_DMA_MCASP1_AREVT,
 454                 .end    = DAVINCI_DA830_DMA_MCASP1_AREVT,
 455                 .flags  = IORESOURCE_DMA,
 456         },
 457 };
 458
 459 static struct platform_device da830_mcasp1_device = {
 460         .name           = "davinci-mcasp",
 461         .id             = 1,
 462         .num_resources  = ARRAY_SIZE(da830_mcasp1_resources),
 463         .resource       = da830_mcasp1_resources,
 464 };
 465
 466 static struct resource da850_mcasp_resources[] = {
 467         {
 468                 .name   = "mcasp",
 469                 .start  = DAVINCI_DA8XX_MCASP0_REG_BASE,
 470                 .end    = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
 471                 .flags  = IORESOURCE_MEM,
 472         },
 473         /* TX event */
 474         {
 475                 .start  = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
 476                 .end    = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
 477                 .flags  = IORESOURCE_DMA,
 478         },
 479         /* RX event */
 480         {
 481                 .start  = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
 482                 .end    = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
 483                 .flags  = IORESOURCE_DMA,
 484         },
 485 };
 486
 487 static struct platform_device da850_mcasp_device = {
 488         .name           = "davinci-mcasp",
 489         .id             = 0,
 490         .num_resources  = ARRAY_SIZE(da850_mcasp_resources),
 491         .resource       = da850_mcasp_resources,
 492 };
 493
 494 struct platform_device davinci_pcm_device = {
 495         .name   = "davinci-pcm-audio",
 496         .id     = -1,
 497 };
 498
 499 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
 500 {
 501         platform_device_register(&davinci_pcm_device);
 502
 503         /* DA830/OMAP-L137 has 3 instances of McASP */
 504         if (cpu_is_davinci_da830() && id == 1) {
 505                 da830_mcasp1_device.dev.platform_data = pdata;
 506                 platform_device_register(&da830_mcasp1_device);
 507         } else if (cpu_is_davinci_da850()) {
 508                 da850_mcasp_device.dev.platform_data = pdata;
 509                 platform_device_register(&da850_mcasp_device);
 510         }
 511 }
 512
 513 static const struct display_panel disp_panel = {
 514         QVGA,
 515         16,
 516         16,
 517         COLOR_ACTIVE,
 518 };
 519
 520 static struct lcd_ctrl_config lcd_cfg = {
 521         &disp_panel,
 522         .ac_bias                = 255,
 523         .ac_bias_intrpt         = 0,
 524         .dma_burst_sz           = 16,
 525         .bpp                    = 16,
 526         .fdd                    = 255,
 527         .tft_alt_mode           = 0,
 528         .stn_565_mode           = 0,
 529         .mono_8bit_mode         = 0,
 530         .invert_line_clock      = 1,
 531         .invert_frm_clock       = 1,
 532         .sync_edge              = 0,
 533         .sync_ctrl              = 1,
 534         .raster_order           = 0,
 535 };
 536
 537 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
 538         .manu_name              = "sharp",
 539         .controller_data        = &lcd_cfg,
 540         .type                   = "Sharp_LCD035Q3DG01",
 541 };
 542
 543 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
 544         .manu_name              = "sharp",
 545         .controller_data        = &lcd_cfg,
 546         .type                   = "Sharp_LK043T1DG01",
 547 };
 548
 549 static struct resource da8xx_lcdc_resources[] = {
 550         [0] = { /* registers */
 551                 .start  = DA8XX_LCD_CNTRL_BASE,
 552                 .end    = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
 553                 .flags  = IORESOURCE_MEM,
 554         },
 555         [1] = { /* interrupt */
 556                 .start  = IRQ_DA8XX_LCDINT,
 557                 .end    = IRQ_DA8XX_LCDINT,
 558                 .flags  = IORESOURCE_IRQ,
 559         },
 560 };
 561
 562 static struct platform_device da8xx_lcdc_device = {
 563         .name           = "da8xx_lcdc",
 564         .id             = 0,
 565         .num_resources  = ARRAY_SIZE(da8xx_lcdc_resources),
 566         .resource       = da8xx_lcdc_resources,
 567 };
 568
 569 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
 570 {
 571         da8xx_lcdc_device.dev.platform_data = pdata;
 572         return platform_device_register(&da8xx_lcdc_device);
 573 }
 574
 575 static struct resource da8xx_mmcsd0_resources[] = {
 576         {               /* registers */
 577                 .start  = DA8XX_MMCSD0_BASE,
 578                 .end    = DA8XX_MMCSD0_BASE + SZ_4K - 1,
 579                 .flags  = IORESOURCE_MEM,
 580         },
 581         {               /* interrupt */
 582                 .start  = IRQ_DA8XX_MMCSDINT0,
 583                 .end    = IRQ_DA8XX_MMCSDINT0,
 584                 .flags  = IORESOURCE_IRQ,
 585         },
 586         {               /* DMA RX */
 587                 .start  = DA8XX_DMA_MMCSD0_RX,
 588                 .end    = DA8XX_DMA_MMCSD0_RX,
 589                 .flags  = IORESOURCE_DMA,
 590         },
 591         {               /* DMA TX */
 592                 .start  = DA8XX_DMA_MMCSD0_TX,
 593                 .end    = DA8XX_DMA_MMCSD0_TX,
 594                 .flags  = IORESOURCE_DMA,
 595         },
 596 };
 597
 598 static struct platform_device da8xx_mmcsd0_device = {
 599         .name           = "davinci_mmc",
 600         .id             = 0,
 601         .num_resources  = ARRAY_SIZE(da8xx_mmcsd0_resources),
 602         .resource       = da8xx_mmcsd0_resources,
 603 };
 604
 605 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
 606 {
 607         da8xx_mmcsd0_device.dev.platform_data = config;
 608         return platform_device_register(&da8xx_mmcsd0_device);
 609 }
 610
 611 #ifdef CONFIG_ARCH_DAVINCI_DA850
 612 static struct resource da850_mmcsd1_resources[] = {
 613         {               /* registers */
 614                 .start  = DA850_MMCSD1_BASE,
 615                 .end    = DA850_MMCSD1_BASE + SZ_4K - 1,
 616                 .flags  = IORESOURCE_MEM,
 617         },
 618         {               /* interrupt */
 619                 .start  = IRQ_DA850_MMCSDINT0_1,
 620                 .end    = IRQ_DA850_MMCSDINT0_1,
 621                 .flags  = IORESOURCE_IRQ,
 622         },
 623         {               /* DMA RX */
 624                 .start  = DA850_DMA_MMCSD1_RX,
 625                 .end    = DA850_DMA_MMCSD1_RX,
 626                 .flags  = IORESOURCE_DMA,
 627         },
 628         {               /* DMA TX */
 629                 .start  = DA850_DMA_MMCSD1_TX,
 630                 .end    = DA850_DMA_MMCSD1_TX,
 631                 .flags  = IORESOURCE_DMA,
 632         },
 633 };
 634
 635 static struct platform_device da850_mmcsd1_device = {
 636         .name           = "davinci_mmc",
 637         .id             = 1,
 638         .num_resources  = ARRAY_SIZE(da850_mmcsd1_resources),
 639         .resource       = da850_mmcsd1_resources,
 640 };
 641
 642 int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
 643 {
 644         da850_mmcsd1_device.dev.platform_data = config;
 645         return platform_device_register(&da850_mmcsd1_device);
 646 }
 647 #endif
 648
 649 static struct resource da8xx_rtc_resources[] = {
 650         {
 651                 .start          = DA8XX_RTC_BASE,
 652                 .end            = DA8XX_RTC_BASE + SZ_4K - 1,
 653                 .flags          = IORESOURCE_MEM,
 654         },
 655         { /* timer irq */
 656                 .start          = IRQ_DA8XX_RTC,
 657                 .end            = IRQ_DA8XX_RTC,
 658                 .flags          = IORESOURCE_IRQ,
 659         },
 660         { /* alarm irq */
 661                 .start          = IRQ_DA8XX_RTC,
 662                 .end            = IRQ_DA8XX_RTC,
 663                 .flags          = IORESOURCE_IRQ,
 664         },
 665 };
 666
 667 static struct platform_device da8xx_rtc_device = {
 668         .name           = "omap_rtc",
 669         .id             = -1,
 670         .num_resources  = ARRAY_SIZE(da8xx_rtc_resources),
 671         .resource       = da8xx_rtc_resources,
 672 };
 673
 674 int da8xx_register_rtc(void)
 675 {
 676         int ret;
 677         void __iomem *base;
 678
 679         base = ioremap(DA8XX_RTC_BASE, SZ_4K);
 680         if (WARN_ON(!base))
 681                 return -ENOMEM;
 682
 683         /* Unlock the rtc's registers */
 684         __raw_writel(0x83e70b13, base + 0x6c);
 685         __raw_writel(0x95a4f1e0, base + 0x70);
 686
 687         iounmap(base);
 688
 689         ret = platform_device_register(&da8xx_rtc_device);
 690         if (!ret)
 691                 /* Atleast on DA850, RTC is a wakeup source */
 692                 device_init_wakeup(&da8xx_rtc_device.dev, true);
 693
 694         return ret;
 695 }
 696
 697 static void __iomem *da8xx_ddr2_ctlr_base;
 698 void __iomem * __init da8xx_get_mem_ctlr(void)
 699 {
 700         if (da8xx_ddr2_ctlr_base)
 701                 return da8xx_ddr2_ctlr_base;
 702
 703         da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
 704         if (!da8xx_ddr2_ctlr_base)
 705                 pr_warning("%s: Unable to map DDR2 controller", __func__);
 706
 707         return da8xx_ddr2_ctlr_base;
 708 }
 709
 710 static struct resource da8xx_cpuidle_resources[] = {
 711         {
 712                 .start          = DA8XX_DDR2_CTL_BASE,
 713                 .end            = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
 714                 .flags          = IORESOURCE_MEM,
 715         },
 716 };
 717
 718 /* DA8XX devices support DDR2 power down */
 719 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
 720         .ddr2_pdown     = 1,
 721 };
 722
 723
 724 static struct platform_device da8xx_cpuidle_device = {
 725         .name                   = "cpuidle-davinci",
 726         .num_resources          = ARRAY_SIZE(da8xx_cpuidle_resources),
 727         .resource               = da8xx_cpuidle_resources,
 728         .dev = {
 729                 .platform_data  = &da8xx_cpuidle_pdata,
 730         },
 731 };
 732
 733 int __init da8xx_register_cpuidle(void)
 734 {
 735         da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
 736
 737         return platform_device_register(&da8xx_cpuidle_device);
 738 }
 739
 740 static struct resource da8xx_spi0_resources[] = {
 741         [0] = {
 742                 .start  = DA8XX_SPI0_BASE,
 743                 .end    = DA8XX_SPI0_BASE + SZ_4K - 1,
 744                 .flags  = IORESOURCE_MEM,
 745         },
 746         [1] = {
 747                 .start  = IRQ_DA8XX_SPINT0,
 748                 .end    = IRQ_DA8XX_SPINT0,
 749                 .flags  = IORESOURCE_IRQ,
 750         },
 751         [2] = {
 752                 .start  = DA8XX_DMA_SPI0_RX,
 753                 .end    = DA8XX_DMA_SPI0_RX,
 754                 .flags  = IORESOURCE_DMA,
 755         },
 756         [3] = {
 757                 .start  = DA8XX_DMA_SPI0_TX,
 758                 .end    = DA8XX_DMA_SPI0_TX,
 759                 .flags  = IORESOURCE_DMA,
 760         },
 761 };
 762
 763 static struct resource da8xx_spi1_resources[] = {
 764         [0] = {
 765                 .start  = DA8XX_SPI1_BASE,
 766                 .end    = DA8XX_SPI1_BASE + SZ_4K - 1,
 767                 .flags  = IORESOURCE_MEM,
 768         },
 769         [1] = {
 770                 .start  = IRQ_DA8XX_SPINT1,
 771                 .end    = IRQ_DA8XX_SPINT1,
 772                 .flags  = IORESOURCE_IRQ,
 773         },
 774         [2] = {
 775                 .start  = DA8XX_DMA_SPI1_RX,
 776                 .end    = DA8XX_DMA_SPI1_RX,
 777                 .flags  = IORESOURCE_DMA,
 778         },
 779         [3] = {
 780                 .start  = DA8XX_DMA_SPI1_TX,
 781                 .end    = DA8XX_DMA_SPI1_TX,
 782                 .flags  = IORESOURCE_DMA,
 783         },
 784 };
 785
 786 struct davinci_spi_platform_data da8xx_spi_pdata[] = {
 787         [0] = {
 788                 .version        = SPI_VERSION_2,
 789                 .intr_line      = 1,
 790                 .dma_event_q    = EVENTQ_0,
 791         },
 792         [1] = {
 793                 .version        = SPI_VERSION_2,
 794                 .intr_line      = 1,
 795                 .dma_event_q    = EVENTQ_0,
 796         },
 797 };
 798
 799 static struct platform_device da8xx_spi_device[] = {
 800         [0] = {
 801                 .name           = "spi_davinci",
 802                 .id             = 0,
 803                 .num_resources  = ARRAY_SIZE(da8xx_spi0_resources),
 804                 .resource       = da8xx_spi0_resources,
 805                 .dev            = {
 806                         .platform_data = &da8xx_spi_pdata[0],
 807                 },
 808         },
 809         [1] = {
 810                 .name           = "spi_davinci",
 811                 .id             = 1,
 812                 .num_resources  = ARRAY_SIZE(da8xx_spi1_resources),
 813                 .resource       = da8xx_spi1_resources,
 814                 .dev            = {
 815                         .platform_data = &da8xx_spi_pdata[1],
 816                 },
 817         },
 818 };
 819
 820 int __init da8xx_register_spi(int instance, struct spi_board_info *info,
 821                               unsigned len)
 822 {
 823         int ret;
 824
 825         if (instance < 0 || instance > 1)
 826                 return -EINVAL;
 827
 828         ret = spi_register_board_info(info, len);
 829         if (ret)
 830                 pr_warning("%s: failed to register board info for spi %d :"
 831                            " %d\n", __func__, instance, ret);
 832
 833         da8xx_spi_pdata[instance].num_chipselect = len;
 834
 835         return platform_device_register(&da8xx_spi_device[instance]);
 836 }