arch/arm/mach-davinci/da850.c

   1 /*
   2  * TI DA850/OMAP-L138 chip specific setup
   3  *
   4  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * Derived from: arch/arm/mach-davinci/da830.c
   7  * Original Copyrights follow:
   8  *
   9  * 2009 (c) MontaVista Software, Inc. This file is licensed under
  10  * the terms of the GNU General Public License version 2. This program
  11  * is licensed "as is" without any warranty of any kind, whether express
  12  * or implied.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/clk.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/cpufreq.h>
  18 #include <linux/regulator/consumer.h>
  19
  20 #include <asm/mach/map.h>
  21
  22 #include <mach/psc.h>
  23 #include <mach/irqs.h>
  24 #include <mach/cputype.h>
  25 #include <mach/common.h>
  26 #include <mach/time.h>
  27 #include <mach/da8xx.h>
  28 #include <mach/cpufreq.h>
  29 #include <mach/pm.h>
  30 #include <mach/gpio.h>
  31
  32 #include "clock.h"
  33 #include "mux.h"
  34
  35 /* SoC specific clock flags */
  36 #define DA850_CLK_ASYNC3        BIT(16)
  37
  38 #define DA850_PLL1_BASE         0x01e1a000
  39 #define DA850_TIMER64P2_BASE    0x01f0c000
  40 #define DA850_TIMER64P3_BASE    0x01f0d000
  41
  42 #define DA850_REF_FREQ          24000000
  43
  44 #define CFGCHIP3_ASYNC3_CLKSRC  BIT(4)
  45 #define CFGCHIP3_PLL1_MASTER_LOCK       BIT(5)
  46 #define CFGCHIP0_PLL_MASTER_LOCK        BIT(4)
  47
  48 static int da850_set_armrate(struct clk *clk, unsigned long rate);
  49 static int da850_round_armrate(struct clk *clk, unsigned long rate);
  50 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
  51
  52 static struct pll_data pll0_data = {
  53         .num            = 1,
  54         .phys_base      = DA8XX_PLL0_BASE,
  55         .flags          = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
  56 };
  57
  58 static struct clk ref_clk = {
  59         .name           = "ref_clk",
  60         .rate           = DA850_REF_FREQ,
  61 };
  62
  63 static struct clk pll0_clk = {
  64         .name           = "pll0",
  65         .parent         = &ref_clk,
  66         .pll_data       = &pll0_data,
  67         .flags          = CLK_PLL,
  68         .set_rate       = da850_set_pll0rate,
  69 };
  70
  71 static struct clk pll0_aux_clk = {
  72         .name           = "pll0_aux_clk",
  73         .parent         = &pll0_clk,
  74         .flags          = CLK_PLL | PRE_PLL,
  75 };
  76
  77 static struct clk pll0_sysclk2 = {
  78         .name           = "pll0_sysclk2",
  79         .parent         = &pll0_clk,
  80         .flags          = CLK_PLL,
  81         .div_reg        = PLLDIV2,
  82 };
  83
  84 static struct clk pll0_sysclk3 = {
  85         .name           = "pll0_sysclk3",
  86         .parent         = &pll0_clk,
  87         .flags          = CLK_PLL,
  88         .div_reg        = PLLDIV3,
  89 };
  90
  91 static struct clk pll0_sysclk4 = {
  92         .name           = "pll0_sysclk4",
  93         .parent         = &pll0_clk,
  94         .flags          = CLK_PLL,
  95         .div_reg        = PLLDIV4,
  96 };
  97
  98 static struct clk pll0_sysclk5 = {
  99         .name           = "pll0_sysclk5",
 100         .parent         = &pll0_clk,
 101         .flags          = CLK_PLL,
 102         .div_reg        = PLLDIV5,
 103 };
 104
 105 static struct clk pll0_sysclk6 = {
 106         .name           = "pll0_sysclk6",
 107         .parent         = &pll0_clk,
 108         .flags          = CLK_PLL,
 109         .div_reg        = PLLDIV6,
 110 };
 111
 112 static struct clk pll0_sysclk7 = {
 113         .name           = "pll0_sysclk7",
 114         .parent         = &pll0_clk,
 115         .flags          = CLK_PLL,
 116         .div_reg        = PLLDIV7,
 117 };
 118
 119 static struct pll_data pll1_data = {
 120         .num            = 2,
 121         .phys_base      = DA850_PLL1_BASE,
 122         .flags          = PLL_HAS_POSTDIV,
 123 };
 124
 125 static struct clk pll1_clk = {
 126         .name           = "pll1",
 127         .parent         = &ref_clk,
 128         .pll_data       = &pll1_data,
 129         .flags          = CLK_PLL,
 130 };
 131
 132 static struct clk pll1_aux_clk = {
 133         .name           = "pll1_aux_clk",
 134         .parent         = &pll1_clk,
 135         .flags          = CLK_PLL | PRE_PLL,
 136 };
 137
 138 static struct clk pll1_sysclk2 = {
 139         .name           = "pll1_sysclk2",
 140         .parent         = &pll1_clk,
 141         .flags          = CLK_PLL,
 142         .div_reg        = PLLDIV2,
 143 };
 144
 145 static struct clk pll1_sysclk3 = {
 146         .name           = "pll1_sysclk3",
 147         .parent         = &pll1_clk,
 148         .flags          = CLK_PLL,
 149         .div_reg        = PLLDIV3,
 150 };
 151
 152 static struct clk pll1_sysclk4 = {
 153         .name           = "pll1_sysclk4",
 154         .parent         = &pll1_clk,
 155         .flags          = CLK_PLL,
 156         .div_reg        = PLLDIV4,
 157 };
 158
 159 static struct clk pll1_sysclk5 = {
 160         .name           = "pll1_sysclk5",
 161         .parent         = &pll1_clk,
 162         .flags          = CLK_PLL,
 163         .div_reg        = PLLDIV5,
 164 };
 165
 166 static struct clk pll1_sysclk6 = {
 167         .name           = "pll0_sysclk6",
 168         .parent         = &pll0_clk,
 169         .flags          = CLK_PLL,
 170         .div_reg        = PLLDIV6,
 171 };
 172
 173 static struct clk pll1_sysclk7 = {
 174         .name           = "pll1_sysclk7",
 175         .parent         = &pll1_clk,
 176         .flags          = CLK_PLL,
 177         .div_reg        = PLLDIV7,
 178 };
 179
 180 static struct clk i2c0_clk = {
 181         .name           = "i2c0",
 182         .parent         = &pll0_aux_clk,
 183 };
 184
 185 static struct clk timerp64_0_clk = {
 186         .name           = "timer0",
 187         .parent         = &pll0_aux_clk,
 188 };
 189
 190 static struct clk timerp64_1_clk = {
 191         .name           = "timer1",
 192         .parent         = &pll0_aux_clk,
 193 };
 194
 195 static struct clk arm_rom_clk = {
 196         .name           = "arm_rom",
 197         .parent         = &pll0_sysclk2,
 198         .lpsc           = DA8XX_LPSC0_ARM_RAM_ROM,
 199         .flags          = ALWAYS_ENABLED,
 200 };
 201
 202 static struct clk tpcc0_clk = {
 203         .name           = "tpcc0",
 204         .parent         = &pll0_sysclk2,
 205         .lpsc           = DA8XX_LPSC0_TPCC,
 206         .flags          = ALWAYS_ENABLED | CLK_PSC,
 207 };
 208
 209 static struct clk tptc0_clk = {
 210         .name           = "tptc0",
 211         .parent         = &pll0_sysclk2,
 212         .lpsc           = DA8XX_LPSC0_TPTC0,
 213         .flags          = ALWAYS_ENABLED,
 214 };
 215
 216 static struct clk tptc1_clk = {
 217         .name           = "tptc1",
 218         .parent         = &pll0_sysclk2,
 219         .lpsc           = DA8XX_LPSC0_TPTC1,
 220         .flags          = ALWAYS_ENABLED,
 221 };
 222
 223 static struct clk tpcc1_clk = {
 224         .name           = "tpcc1",
 225         .parent         = &pll0_sysclk2,
 226         .lpsc           = DA850_LPSC1_TPCC1,
 227         .gpsc           = 1,
 228         .flags          = CLK_PSC | ALWAYS_ENABLED,
 229 };
 230
 231 static struct clk tptc2_clk = {
 232         .name           = "tptc2",
 233         .parent         = &pll0_sysclk2,
 234         .lpsc           = DA850_LPSC1_TPTC2,
 235         .gpsc           = 1,
 236         .flags          = ALWAYS_ENABLED,
 237 };
 238
 239 static struct clk uart0_clk = {
 240         .name           = "uart0",
 241         .parent         = &pll0_sysclk2,
 242         .lpsc           = DA8XX_LPSC0_UART0,
 243 };
 244
 245 static struct clk uart1_clk = {
 246         .name           = "uart1",
 247         .parent         = &pll0_sysclk2,
 248         .lpsc           = DA8XX_LPSC1_UART1,
 249         .gpsc           = 1,
 250         .flags          = DA850_CLK_ASYNC3,
 251 };
 252
 253 static struct clk uart2_clk = {
 254         .name           = "uart2",
 255         .parent         = &pll0_sysclk2,
 256         .lpsc           = DA8XX_LPSC1_UART2,
 257         .gpsc           = 1,
 258         .flags          = DA850_CLK_ASYNC3,
 259 };
 260
 261 static struct clk aintc_clk = {
 262         .name           = "aintc",
 263         .parent         = &pll0_sysclk4,
 264         .lpsc           = DA8XX_LPSC0_AINTC,
 265         .flags          = ALWAYS_ENABLED,
 266 };
 267
 268 static struct clk gpio_clk = {
 269         .name           = "gpio",
 270         .parent         = &pll0_sysclk4,
 271         .lpsc           = DA8XX_LPSC1_GPIO,
 272         .gpsc           = 1,
 273 };
 274
 275 static struct clk i2c1_clk = {
 276         .name           = "i2c1",
 277         .parent         = &pll0_sysclk4,
 278         .lpsc           = DA8XX_LPSC1_I2C,
 279         .gpsc           = 1,
 280 };
 281
 282 static struct clk emif3_clk = {
 283         .name           = "emif3",
 284         .parent         = &pll0_sysclk5,
 285         .lpsc           = DA8XX_LPSC1_EMIF3C,
 286         .gpsc           = 1,
 287         .flags          = ALWAYS_ENABLED,
 288 };
 289
 290 static struct clk arm_clk = {
 291         .name           = "arm",
 292         .parent         = &pll0_sysclk6,
 293         .lpsc           = DA8XX_LPSC0_ARM,
 294         .flags          = ALWAYS_ENABLED,
 295         .set_rate       = da850_set_armrate,
 296         .round_rate     = da850_round_armrate,
 297 };
 298
 299 static struct clk rmii_clk = {
 300         .name           = "rmii",
 301         .parent         = &pll0_sysclk7,
 302 };
 303
 304 static struct clk emac_clk = {
 305         .name           = "emac",
 306         .parent         = &pll0_sysclk4,
 307         .lpsc           = DA8XX_LPSC1_CPGMAC,
 308         .gpsc           = 1,
 309 };
 310
 311 static struct clk mcasp_clk = {
 312         .name           = "mcasp",
 313         .parent         = &pll0_sysclk2,
 314         .lpsc           = DA8XX_LPSC1_McASP0,
 315         .gpsc           = 1,
 316         .flags          = DA850_CLK_ASYNC3,
 317 };
 318
 319 static struct clk lcdc_clk = {
 320         .name           = "lcdc",
 321         .parent         = &pll0_sysclk2,
 322         .lpsc           = DA8XX_LPSC1_LCDC,
 323         .gpsc           = 1,
 324 };
 325
 326 static struct clk mmcsd_clk = {
 327         .name           = "mmcsd",
 328         .parent         = &pll0_sysclk2,
 329         .lpsc           = DA8XX_LPSC0_MMC_SD,
 330 };
 331
 332 static struct clk aemif_clk = {
 333         .name           = "aemif",
 334         .parent         = &pll0_sysclk3,
 335         .lpsc           = DA8XX_LPSC0_EMIF25,
 336         .flags          = ALWAYS_ENABLED,
 337 };
 338
 339 static struct clk_lookup da850_clks[] = {
 340         CLK(NULL,               "ref",          &ref_clk),
 341         CLK(NULL,               "pll0",         &pll0_clk),
 342         CLK(NULL,               "pll0_aux",     &pll0_aux_clk),
 343         CLK(NULL,               "pll0_sysclk2", &pll0_sysclk2),
 344         CLK(NULL,               "pll0_sysclk3", &pll0_sysclk3),
 345         CLK(NULL,               "pll0_sysclk4", &pll0_sysclk4),
 346         CLK(NULL,               "pll0_sysclk5", &pll0_sysclk5),
 347         CLK(NULL,               "pll0_sysclk6", &pll0_sysclk6),
 348         CLK(NULL,               "pll0_sysclk7", &pll0_sysclk7),
 349         CLK(NULL,               "pll1",         &pll1_clk),
 350         CLK(NULL,               "pll1_aux",     &pll1_aux_clk),
 351         CLK(NULL,               "pll1_sysclk2", &pll1_sysclk2),
 352         CLK(NULL,               "pll1_sysclk3", &pll1_sysclk3),
 353         CLK(NULL,               "pll1_sysclk4", &pll1_sysclk4),
 354         CLK(NULL,               "pll1_sysclk5", &pll1_sysclk5),
 355         CLK(NULL,               "pll1_sysclk6", &pll1_sysclk6),
 356         CLK(NULL,               "pll1_sysclk7", &pll1_sysclk7),
 357         CLK("i2c_davinci.1",    NULL,           &i2c0_clk),
 358         CLK(NULL,               "timer0",       &timerp64_0_clk),
 359         CLK("watchdog",         NULL,           &timerp64_1_clk),
 360         CLK(NULL,               "arm_rom",      &arm_rom_clk),
 361         CLK(NULL,               "tpcc0",        &tpcc0_clk),
 362         CLK(NULL,               "tptc0",        &tptc0_clk),
 363         CLK(NULL,               "tptc1",        &tptc1_clk),
 364         CLK(NULL,               "tpcc1",        &tpcc1_clk),
 365         CLK(NULL,               "tptc2",        &tptc2_clk),
 366         CLK(NULL,               "uart0",        &uart0_clk),
 367         CLK(NULL,               "uart1",        &uart1_clk),
 368         CLK(NULL,               "uart2",        &uart2_clk),
 369         CLK(NULL,               "aintc",        &aintc_clk),
 370         CLK(NULL,               "gpio",         &gpio_clk),
 371         CLK("i2c_davinci.2",    NULL,           &i2c1_clk),
 372         CLK(NULL,               "emif3",        &emif3_clk),
 373         CLK(NULL,               "arm",          &arm_clk),
 374         CLK(NULL,               "rmii",         &rmii_clk),
 375         CLK("davinci_emac.1",   NULL,           &emac_clk),
 376         CLK("davinci-mcasp.0",  NULL,           &mcasp_clk),
 377         CLK("da8xx_lcdc.0",     NULL,           &lcdc_clk),
 378         CLK("davinci_mmc.0",    NULL,           &mmcsd_clk),
 379         CLK(NULL,               "aemif",        &aemif_clk),
 380         CLK(NULL,               NULL,           NULL),
 381 };
 382
 383 /*
 384  * Device specific mux setup
 385  *
 386  *              soc     description     mux     mode    mode    mux     dbg
 387  *                                      reg     offset  mask    mode
 388  */
 389 static const struct mux_config da850_pins[] = {
 390 #ifdef CONFIG_DAVINCI_MUX
 391         /* UART0 function */
 392         MUX_CFG(DA850, NUART0_CTS,      3,      24,     15,     2,      false)
 393         MUX_CFG(DA850, NUART0_RTS,      3,      28,     15,     2,      false)
 394         MUX_CFG(DA850, UART0_RXD,       3,      16,     15,     2,      false)
 395         MUX_CFG(DA850, UART0_TXD,       3,      20,     15,     2,      false)
 396         /* UART1 function */
 397         MUX_CFG(DA850, UART1_RXD,       4,      24,     15,     2,      false)
 398         MUX_CFG(DA850, UART1_TXD,       4,      28,     15,     2,      false)
 399         /* UART2 function */
 400         MUX_CFG(DA850, UART2_RXD,       4,      16,     15,     2,      false)
 401         MUX_CFG(DA850, UART2_TXD,       4,      20,     15,     2,      false)
 402         /* I2C1 function */
 403         MUX_CFG(DA850, I2C1_SCL,        4,      16,     15,     4,      false)
 404         MUX_CFG(DA850, I2C1_SDA,        4,      20,     15,     4,      false)
 405         /* I2C0 function */
 406         MUX_CFG(DA850, I2C0_SDA,        4,      12,     15,     2,      false)
 407         MUX_CFG(DA850, I2C0_SCL,        4,      8,      15,     2,      false)
 408         /* EMAC function */
 409         MUX_CFG(DA850, MII_TXEN,        2,      4,      15,     8,      false)
 410         MUX_CFG(DA850, MII_TXCLK,       2,      8,      15,     8,      false)
 411         MUX_CFG(DA850, MII_COL,         2,      12,     15,     8,      false)
 412         MUX_CFG(DA850, MII_TXD_3,       2,      16,     15,     8,      false)
 413         MUX_CFG(DA850, MII_TXD_2,       2,      20,     15,     8,      false)
 414         MUX_CFG(DA850, MII_TXD_1,       2,      24,     15,     8,      false)
 415         MUX_CFG(DA850, MII_TXD_0,       2,      28,     15,     8,      false)
 416         MUX_CFG(DA850, MII_RXCLK,       3,      0,      15,     8,      false)
 417         MUX_CFG(DA850, MII_RXDV,        3,      4,      15,     8,      false)
 418         MUX_CFG(DA850, MII_RXER,        3,      8,      15,     8,      false)
 419         MUX_CFG(DA850, MII_CRS,         3,      12,     15,     8,      false)
 420         MUX_CFG(DA850, MII_RXD_3,       3,      16,     15,     8,      false)
 421         MUX_CFG(DA850, MII_RXD_2,       3,      20,     15,     8,      false)
 422         MUX_CFG(DA850, MII_RXD_1,       3,      24,     15,     8,      false)
 423         MUX_CFG(DA850, MII_RXD_0,       3,      28,     15,     8,      false)
 424         MUX_CFG(DA850, MDIO_CLK,        4,      0,      15,     8,      false)
 425         MUX_CFG(DA850, MDIO_D,          4,      4,      15,     8,      false)
 426         MUX_CFG(DA850, RMII_TXD_0,      14,     12,     15,     8,      false)
 427         MUX_CFG(DA850, RMII_TXD_1,      14,     8,      15,     8,      false)
 428         MUX_CFG(DA850, RMII_TXEN,       14,     16,     15,     8,      false)
 429         MUX_CFG(DA850, RMII_CRS_DV,     15,     4,      15,     8,      false)
 430         MUX_CFG(DA850, RMII_RXD_0,      14,     24,     15,     8,      false)
 431         MUX_CFG(DA850, RMII_RXD_1,      14,     20,     15,     8,      false)
 432         MUX_CFG(DA850, RMII_RXER,       14,     28,     15,     8,      false)
 433         MUX_CFG(DA850, RMII_MHZ_50_CLK, 15,     0,      15,     0,      false)
 434         /* McASP function */
 435         MUX_CFG(DA850,  ACLKR,          0,      0,      15,     1,      false)
 436         MUX_CFG(DA850,  ACLKX,          0,      4,      15,     1,      false)
 437         MUX_CFG(DA850,  AFSR,           0,      8,      15,     1,      false)
 438         MUX_CFG(DA850,  AFSX,           0,      12,     15,     1,      false)
 439         MUX_CFG(DA850,  AHCLKR,         0,      16,     15,     1,      false)
 440         MUX_CFG(DA850,  AHCLKX,         0,      20,     15,     1,      false)
 441         MUX_CFG(DA850,  AMUTE,          0,      24,     15,     1,      false)
 442         MUX_CFG(DA850,  AXR_15,         1,      0,      15,     1,      false)
 443         MUX_CFG(DA850,  AXR_14,         1,      4,      15,     1,      false)
 444         MUX_CFG(DA850,  AXR_13,         1,      8,      15,     1,      false)
 445         MUX_CFG(DA850,  AXR_12,         1,      12,     15,     1,      false)
 446         MUX_CFG(DA850,  AXR_11,         1,      16,     15,     1,      false)
 447         MUX_CFG(DA850,  AXR_10,         1,      20,     15,     1,      false)
 448         MUX_CFG(DA850,  AXR_9,          1,      24,     15,     1,      false)
 449         MUX_CFG(DA850,  AXR_8,          1,      28,     15,     1,      false)
 450         MUX_CFG(DA850,  AXR_7,          2,      0,      15,     1,      false)
 451         MUX_CFG(DA850,  AXR_6,          2,      4,      15,     1,      false)
 452         MUX_CFG(DA850,  AXR_5,          2,      8,      15,     1,      false)
 453         MUX_CFG(DA850,  AXR_4,          2,      12,     15,     1,      false)
 454         MUX_CFG(DA850,  AXR_3,          2,      16,     15,     1,      false)
 455         MUX_CFG(DA850,  AXR_2,          2,      20,     15,     1,      false)
 456         MUX_CFG(DA850,  AXR_1,          2,      24,     15,     1,      false)
 457         MUX_CFG(DA850,  AXR_0,          2,      28,     15,     1,      false)
 458         /* LCD function */
 459         MUX_CFG(DA850, LCD_D_7,         16,     8,      15,     2,      false)
 460         MUX_CFG(DA850, LCD_D_6,         16,     12,     15,     2,      false)
 461         MUX_CFG(DA850, LCD_D_5,         16,     16,     15,     2,      false)
 462         MUX_CFG(DA850, LCD_D_4,         16,     20,     15,     2,      false)
 463         MUX_CFG(DA850, LCD_D_3,         16,     24,     15,     2,      false)
 464         MUX_CFG(DA850, LCD_D_2,         16,     28,     15,     2,      false)
 465         MUX_CFG(DA850, LCD_D_1,         17,     0,      15,     2,      false)
 466         MUX_CFG(DA850, LCD_D_0,         17,     4,      15,     2,      false)
 467         MUX_CFG(DA850, LCD_D_15,        17,     8,      15,     2,      false)
 468         MUX_CFG(DA850, LCD_D_14,        17,     12,     15,     2,      false)
 469         MUX_CFG(DA850, LCD_D_13,        17,     16,     15,     2,      false)
 470         MUX_CFG(DA850, LCD_D_12,        17,     20,     15,     2,      false)
 471         MUX_CFG(DA850, LCD_D_11,        17,     24,     15,     2,      false)
 472         MUX_CFG(DA850, LCD_D_10,        17,     28,     15,     2,      false)
 473         MUX_CFG(DA850, LCD_D_9,         18,     0,      15,     2,      false)
 474         MUX_CFG(DA850, LCD_D_8,         18,     4,      15,     2,      false)
 475         MUX_CFG(DA850, LCD_PCLK,        18,     24,     15,     2,      false)
 476         MUX_CFG(DA850, LCD_HSYNC,       19,     0,      15,     2,      false)
 477         MUX_CFG(DA850, LCD_VSYNC,       19,     4,      15,     2,      false)
 478         MUX_CFG(DA850, NLCD_AC_ENB_CS,  19,     24,     15,     2,      false)
 479         /* MMC/SD0 function */
 480         MUX_CFG(DA850, MMCSD0_DAT_0,    10,     8,      15,     2,      false)
 481         MUX_CFG(DA850, MMCSD0_DAT_1,    10,     12,     15,     2,      false)
 482         MUX_CFG(DA850, MMCSD0_DAT_2,    10,     16,     15,     2,      false)
 483         MUX_CFG(DA850, MMCSD0_DAT_3,    10,     20,     15,     2,      false)
 484         MUX_CFG(DA850, MMCSD0_CLK,      10,     0,      15,     2,      false)
 485         MUX_CFG(DA850, MMCSD0_CMD,      10,     4,      15,     2,      false)
 486         /* EMIF2.5/EMIFA function */
 487         MUX_CFG(DA850, EMA_D_7,         9,      0,      15,     1,      false)
 488         MUX_CFG(DA850, EMA_D_6,         9,      4,      15,     1,      false)
 489         MUX_CFG(DA850, EMA_D_5,         9,      8,      15,     1,      false)
 490         MUX_CFG(DA850, EMA_D_4,         9,      12,     15,     1,      false)
 491         MUX_CFG(DA850, EMA_D_3,         9,      16,     15,     1,      false)
 492         MUX_CFG(DA850, EMA_D_2,         9,      20,     15,     1,      false)
 493         MUX_CFG(DA850, EMA_D_1,         9,      24,     15,     1,      false)
 494         MUX_CFG(DA850, EMA_D_0,         9,      28,     15,     1,      false)
 495         MUX_CFG(DA850, EMA_A_1,         12,     24,     15,     1,      false)
 496         MUX_CFG(DA850, EMA_A_2,         12,     20,     15,     1,      false)
 497         MUX_CFG(DA850, NEMA_CS_3,       7,      4,      15,     1,      false)
 498         MUX_CFG(DA850, NEMA_CS_4,       7,      8,      15,     1,      false)
 499         MUX_CFG(DA850, NEMA_WE,         7,      16,     15,     1,      false)
 500         MUX_CFG(DA850, NEMA_OE,         7,      20,     15,     1,      false)
 501         MUX_CFG(DA850, EMA_A_0,         12,     28,     15,     1,      false)
 502         MUX_CFG(DA850, EMA_A_3,         12,     16,     15,     1,      false)
 503         MUX_CFG(DA850, EMA_A_4,         12,     12,     15,     1,      false)
 504         MUX_CFG(DA850, EMA_A_5,         12,     8,      15,     1,      false)
 505         MUX_CFG(DA850, EMA_A_6,         12,     4,      15,     1,      false)
 506         MUX_CFG(DA850, EMA_A_7,         12,     0,      15,     1,      false)
 507         MUX_CFG(DA850, EMA_A_8,         11,     28,     15,     1,      false)
 508         MUX_CFG(DA850, EMA_A_9,         11,     24,     15,     1,      false)
 509         MUX_CFG(DA850, EMA_A_10,        11,     20,     15,     1,      false)
 510         MUX_CFG(DA850, EMA_A_11,        11,     16,     15,     1,      false)
 511         MUX_CFG(DA850, EMA_A_12,        11,     12,     15,     1,      false)
 512         MUX_CFG(DA850, EMA_A_13,        11,     8,      15,     1,      false)
 513         MUX_CFG(DA850, EMA_A_14,        11,     4,      15,     1,      false)
 514         MUX_CFG(DA850, EMA_A_15,        11,     0,      15,     1,      false)
 515         MUX_CFG(DA850, EMA_A_16,        10,     28,     15,     1,      false)
 516         MUX_CFG(DA850, EMA_A_17,        10,     24,     15,     1,      false)
 517         MUX_CFG(DA850, EMA_A_18,        10,     20,     15,     1,      false)
 518         MUX_CFG(DA850, EMA_A_19,        10,     16,     15,     1,      false)
 519         MUX_CFG(DA850, EMA_A_20,        10,     12,     15,     1,      false)
 520         MUX_CFG(DA850, EMA_A_21,        10,     8,      15,     1,      false)
 521         MUX_CFG(DA850, EMA_A_22,        10,     4,      15,     1,      false)
 522         MUX_CFG(DA850, EMA_A_23,        10,     0,      15,     1,      false)
 523         MUX_CFG(DA850, EMA_D_8,         8,      28,     15,     1,      false)
 524         MUX_CFG(DA850, EMA_D_9,         8,      24,     15,     1,      false)
 525         MUX_CFG(DA850, EMA_D_10,        8,      20,     15,     1,      false)
 526         MUX_CFG(DA850, EMA_D_11,        8,      16,     15,     1,      false)
 527         MUX_CFG(DA850, EMA_D_12,        8,      12,     15,     1,      false)
 528         MUX_CFG(DA850, EMA_D_13,        8,      8,      15,     1,      false)
 529         MUX_CFG(DA850, EMA_D_14,        8,      4,      15,     1,      false)
 530         MUX_CFG(DA850, EMA_D_15,        8,      0,      15,     1,      false)
 531         MUX_CFG(DA850, EMA_BA_1,        5,      24,     15,     1,      false)
 532         MUX_CFG(DA850, EMA_CLK,         6,      0,      15,     1,      false)
 533         MUX_CFG(DA850, EMA_WAIT_1,      6,      24,     15,     1,      false)
 534         MUX_CFG(DA850, NEMA_CS_2,       7,      0,      15,     1,      false)
 535         /* GPIO function */
 536         MUX_CFG(DA850, GPIO2_6,         6,      4,      15,     8,      false)
 537         MUX_CFG(DA850, GPIO2_8,         5,      28,     15,     8,      false)
 538         MUX_CFG(DA850, GPIO2_15,        5,      0,      15,     8,      false)
 539         MUX_CFG(DA850, GPIO4_0,         10,     28,     15,     8,      false)
 540         MUX_CFG(DA850, GPIO4_1,         10,     24,     15,     8,      false)
 541         MUX_CFG(DA850, RTC_ALARM,       0,      28,     15,     2,      false)
 542 #endif
 543 };
 544
 545 const short da850_uart0_pins[] __initdata = {
 546         DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
 547         -1
 548 };
 549
 550 const short da850_uart1_pins[] __initdata = {
 551         DA850_UART1_RXD, DA850_UART1_TXD,
 552         -1
 553 };
 554
 555 const short da850_uart2_pins[] __initdata = {
 556         DA850_UART2_RXD, DA850_UART2_TXD,
 557         -1
 558 };
 559
 560 const short da850_i2c0_pins[] __initdata = {
 561         DA850_I2C0_SDA, DA850_I2C0_SCL,
 562         -1
 563 };
 564
 565 const short da850_i2c1_pins[] __initdata = {
 566         DA850_I2C1_SCL, DA850_I2C1_SDA,
 567         -1
 568 };
 569
 570 const short da850_cpgmac_pins[] __initdata = {
 571         DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
 572         DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
 573         DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
 574         DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
 575         DA850_MDIO_D,
 576         -1
 577 };
 578
 579 const short da850_rmii_pins[] __initdata = {
 580         DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
 581         DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
 582         DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
 583         DA850_MDIO_D,
 584         -1
 585 };
 586
 587 const short da850_mcasp_pins[] __initdata = {
 588         DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
 589         DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
 590         DA850_AXR_11, DA850_AXR_12,
 591         -1
 592 };
 593
 594 const short da850_lcdcntl_pins[] __initdata = {
 595         DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
 596         DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
 597         DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
 598         DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
 599         DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
 600         -1
 601 };
 602
 603 const short da850_mmcsd0_pins[] __initdata = {
 604         DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
 605         DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
 606         DA850_GPIO4_0, DA850_GPIO4_1,
 607         -1
 608 };
 609
 610 const short da850_nand_pins[] __initdata = {
 611         DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4,
 612         DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0,
 613         DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
 614         DA850_NEMA_WE, DA850_NEMA_OE,
 615         -1
 616 };
 617
 618 const short da850_nor_pins[] __initdata = {
 619         DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
 620         DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
 621         DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
 622         DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
 623         DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
 624         DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
 625         DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
 626         DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
 627         DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
 628         DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
 629         DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
 630         DA850_EMA_A_22, DA850_EMA_A_23,
 631         -1
 632 };
 633
 634 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
 635 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
 636         [IRQ_DA8XX_COMMTX]              = 7,
 637         [IRQ_DA8XX_COMMRX]              = 7,
 638         [IRQ_DA8XX_NINT]                = 7,
 639         [IRQ_DA8XX_EVTOUT0]             = 7,
 640         [IRQ_DA8XX_EVTOUT1]             = 7,
 641         [IRQ_DA8XX_EVTOUT2]             = 7,
 642         [IRQ_DA8XX_EVTOUT3]             = 7,
 643         [IRQ_DA8XX_EVTOUT4]             = 7,
 644         [IRQ_DA8XX_EVTOUT5]             = 7,
 645         [IRQ_DA8XX_EVTOUT6]             = 7,
 646         [IRQ_DA8XX_EVTOUT6]             = 7,
 647         [IRQ_DA8XX_EVTOUT7]             = 7,
 648         [IRQ_DA8XX_CCINT0]              = 7,
 649         [IRQ_DA8XX_CCERRINT]            = 7,
 650         [IRQ_DA8XX_TCERRINT0]           = 7,
 651         [IRQ_DA8XX_AEMIFINT]            = 7,
 652         [IRQ_DA8XX_I2CINT0]             = 7,
 653         [IRQ_DA8XX_MMCSDINT0]           = 7,
 654         [IRQ_DA8XX_MMCSDINT1]           = 7,
 655         [IRQ_DA8XX_ALLINT0]             = 7,
 656         [IRQ_DA8XX_RTC]                 = 7,
 657         [IRQ_DA8XX_SPINT0]              = 7,
 658         [IRQ_DA8XX_TINT12_0]            = 7,
 659         [IRQ_DA8XX_TINT34_0]            = 7,
 660         [IRQ_DA8XX_TINT12_1]            = 7,
 661         [IRQ_DA8XX_TINT34_1]            = 7,
 662         [IRQ_DA8XX_UARTINT0]            = 7,
 663         [IRQ_DA8XX_KEYMGRINT]           = 7,
 664         [IRQ_DA8XX_SECINT]              = 7,
 665         [IRQ_DA8XX_SECKEYERR]           = 7,
 666         [IRQ_DA850_MPUADDRERR0]         = 7,
 667         [IRQ_DA850_MPUPROTERR0]         = 7,
 668         [IRQ_DA850_IOPUADDRERR0]        = 7,
 669         [IRQ_DA850_IOPUPROTERR0]        = 7,
 670         [IRQ_DA850_IOPUADDRERR1]        = 7,
 671         [IRQ_DA850_IOPUPROTERR1]        = 7,
 672         [IRQ_DA850_IOPUADDRERR2]        = 7,
 673         [IRQ_DA850_IOPUPROTERR2]        = 7,
 674         [IRQ_DA850_BOOTCFG_ADDR_ERR]    = 7,
 675         [IRQ_DA850_BOOTCFG_PROT_ERR]    = 7,
 676         [IRQ_DA850_MPUADDRERR1]         = 7,
 677         [IRQ_DA850_MPUPROTERR1]         = 7,
 678         [IRQ_DA850_IOPUADDRERR3]        = 7,
 679         [IRQ_DA850_IOPUPROTERR3]        = 7,
 680         [IRQ_DA850_IOPUADDRERR4]        = 7,
 681         [IRQ_DA850_IOPUPROTERR4]        = 7,
 682         [IRQ_DA850_IOPUADDRERR5]        = 7,
 683         [IRQ_DA850_IOPUPROTERR5]        = 7,
 684         [IRQ_DA850_MIOPU_BOOTCFG_ERR]   = 7,
 685         [IRQ_DA8XX_CHIPINT0]            = 7,
 686         [IRQ_DA8XX_CHIPINT1]            = 7,
 687         [IRQ_DA8XX_CHIPINT2]            = 7,
 688         [IRQ_DA8XX_CHIPINT3]            = 7,
 689         [IRQ_DA8XX_TCERRINT1]           = 7,
 690         [IRQ_DA8XX_C0_RX_THRESH_PULSE]  = 7,
 691         [IRQ_DA8XX_C0_RX_PULSE]         = 7,
 692         [IRQ_DA8XX_C0_TX_PULSE]         = 7,
 693         [IRQ_DA8XX_C0_MISC_PULSE]       = 7,
 694         [IRQ_DA8XX_C1_RX_THRESH_PULSE]  = 7,
 695         [IRQ_DA8XX_C1_RX_PULSE]         = 7,
 696         [IRQ_DA8XX_C1_TX_PULSE]         = 7,
 697         [IRQ_DA8XX_C1_MISC_PULSE]       = 7,
 698         [IRQ_DA8XX_MEMERR]              = 7,
 699         [IRQ_DA8XX_GPIO0]               = 7,
 700         [IRQ_DA8XX_GPIO1]               = 7,
 701         [IRQ_DA8XX_GPIO2]               = 7,
 702         [IRQ_DA8XX_GPIO3]               = 7,
 703         [IRQ_DA8XX_GPIO4]               = 7,
 704         [IRQ_DA8XX_GPIO5]               = 7,
 705         [IRQ_DA8XX_GPIO6]               = 7,
 706         [IRQ_DA8XX_GPIO7]               = 7,
 707         [IRQ_DA8XX_GPIO8]               = 7,
 708         [IRQ_DA8XX_I2CINT1]             = 7,
 709         [IRQ_DA8XX_LCDINT]              = 7,
 710         [IRQ_DA8XX_UARTINT1]            = 7,
 711         [IRQ_DA8XX_MCASPINT]            = 7,
 712         [IRQ_DA8XX_ALLINT1]             = 7,
 713         [IRQ_DA8XX_SPINT1]              = 7,
 714         [IRQ_DA8XX_UHPI_INT1]           = 7,
 715         [IRQ_DA8XX_USB_INT]             = 7,
 716         [IRQ_DA8XX_IRQN]                = 7,
 717         [IRQ_DA8XX_RWAKEUP]             = 7,
 718         [IRQ_DA8XX_UARTINT2]            = 7,
 719         [IRQ_DA8XX_DFTSSINT]            = 7,
 720         [IRQ_DA8XX_EHRPWM0]             = 7,
 721         [IRQ_DA8XX_EHRPWM0TZ]           = 7,
 722         [IRQ_DA8XX_EHRPWM1]             = 7,
 723         [IRQ_DA8XX_EHRPWM1TZ]           = 7,
 724         [IRQ_DA850_SATAINT]             = 7,
 725         [IRQ_DA850_TINT12_2]            = 7,
 726         [IRQ_DA850_TINT34_2]            = 7,
 727         [IRQ_DA850_TINTALL_2]           = 7,
 728         [IRQ_DA8XX_ECAP0]               = 7,
 729         [IRQ_DA8XX_ECAP1]               = 7,
 730         [IRQ_DA8XX_ECAP2]               = 7,
 731         [IRQ_DA850_MMCSDINT0_1]         = 7,
 732         [IRQ_DA850_MMCSDINT1_1]         = 7,
 733         [IRQ_DA850_T12CMPINT0_2]        = 7,
 734         [IRQ_DA850_T12CMPINT1_2]        = 7,
 735         [IRQ_DA850_T12CMPINT2_2]        = 7,
 736         [IRQ_DA850_T12CMPINT3_2]        = 7,
 737         [IRQ_DA850_T12CMPINT4_2]        = 7,
 738         [IRQ_DA850_T12CMPINT5_2]        = 7,
 739         [IRQ_DA850_T12CMPINT6_2]        = 7,
 740         [IRQ_DA850_T12CMPINT7_2]        = 7,
 741         [IRQ_DA850_T12CMPINT0_3]        = 7,
 742         [IRQ_DA850_T12CMPINT1_3]        = 7,
 743         [IRQ_DA850_T12CMPINT2_3]        = 7,
 744         [IRQ_DA850_T12CMPINT3_3]        = 7,
 745         [IRQ_DA850_T12CMPINT4_3]        = 7,
 746         [IRQ_DA850_T12CMPINT5_3]        = 7,
 747         [IRQ_DA850_T12CMPINT6_3]        = 7,
 748         [IRQ_DA850_T12CMPINT7_3]        = 7,
 749         [IRQ_DA850_RPIINT]              = 7,
 750         [IRQ_DA850_VPIFINT]             = 7,
 751         [IRQ_DA850_CCINT1]              = 7,
 752         [IRQ_DA850_CCERRINT1]           = 7,
 753         [IRQ_DA850_TCERRINT2]           = 7,
 754         [IRQ_DA850_TINT12_3]            = 7,
 755         [IRQ_DA850_TINT34_3]            = 7,
 756         [IRQ_DA850_TINTALL_3]           = 7,
 757         [IRQ_DA850_MCBSP0RINT]          = 7,
 758         [IRQ_DA850_MCBSP0XINT]          = 7,
 759         [IRQ_DA850_MCBSP1RINT]          = 7,
 760         [IRQ_DA850_MCBSP1XINT]          = 7,
 761         [IRQ_DA8XX_ARMCLKSTOPREQ]       = 7,
 762 };
 763
 764 static struct map_desc da850_io_desc[] = {
 765         {
 766                 .virtual        = IO_VIRT,
 767                 .pfn            = __phys_to_pfn(IO_PHYS),
 768                 .length         = IO_SIZE,
 769                 .type           = MT_DEVICE
 770         },
 771         {
 772                 .virtual        = DA8XX_CP_INTC_VIRT,
 773                 .pfn            = __phys_to_pfn(DA8XX_CP_INTC_BASE),
 774                 .length         = DA8XX_CP_INTC_SIZE,
 775                 .type           = MT_DEVICE
 776         },
 777         {
 778                 .virtual        = SRAM_VIRT,
 779                 .pfn            = __phys_to_pfn(DA8XX_ARM_RAM_BASE),
 780                 .length         = SZ_8K,
 781                 .type           = MT_DEVICE
 782         },
 783 };
 784
 785 static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
 786
 787 /* Contents of JTAG ID register used to identify exact cpu type */
 788 static struct davinci_id da850_ids[] = {
 789         {
 790                 .variant        = 0x0,
 791                 .part_no        = 0xb7d1,
 792                 .manufacturer   = 0x017,        /* 0x02f >> 1 */
 793                 .cpu_id         = DAVINCI_CPU_ID_DA850,
 794                 .name           = "da850/omap-l138",
 795         },
 796 };
 797
 798 static struct davinci_timer_instance da850_timer_instance[4] = {
 799         {
 800                 .base           = DA8XX_TIMER64P0_BASE,
 801                 .bottom_irq     = IRQ_DA8XX_TINT12_0,
 802                 .top_irq        = IRQ_DA8XX_TINT34_0,
 803         },
 804         {
 805                 .base           = DA8XX_TIMER64P1_BASE,
 806                 .bottom_irq     = IRQ_DA8XX_TINT12_1,
 807                 .top_irq        = IRQ_DA8XX_TINT34_1,
 808         },
 809         {
 810                 .base           = DA850_TIMER64P2_BASE,
 811                 .bottom_irq     = IRQ_DA850_TINT12_2,
 812                 .top_irq        = IRQ_DA850_TINT34_2,
 813         },
 814         {
 815                 .base           = DA850_TIMER64P3_BASE,
 816                 .bottom_irq     = IRQ_DA850_TINT12_3,
 817                 .top_irq        = IRQ_DA850_TINT34_3,
 818         },
 819 };
 820
 821 /*
 822  * T0_BOT: Timer 0, bottom              : Used for clock_event
 823  * T0_TOP: Timer 0, top                 : Used for clocksource
 824  * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
 825  */
 826 static struct davinci_timer_info da850_timer_info = {
 827         .timers         = da850_timer_instance,
 828         .clockevent_id  = T0_BOT,
 829         .clocksource_id = T0_TOP,
 830 };
 831
 832 static void da850_set_async3_src(int pllnum)
 833 {
 834         struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
 835         struct clk_lookup *c;
 836         unsigned int v;
 837         int ret;
 838
 839         for (c = da850_clks; c->clk; c++) {
 840                 clk = c->clk;
 841                 if (clk->flags & DA850_CLK_ASYNC3) {
 842                         ret = clk_set_parent(clk, newparent);
 843                         WARN(ret, "DA850: unable to re-parent clock %s",
 844                                                                 clk->name);
 845                 }
 846        }
 847
 848         v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
 849         if (pllnum)
 850                 v |= CFGCHIP3_ASYNC3_CLKSRC;
 851         else
 852                 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
 853         __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
 854 }
 855
 856 #ifdef CONFIG_CPU_FREQ
 857 /*
 858  * Notes:
 859  * According to the TRM, minimum PLLM results in maximum power savings.
 860  * The OPP definitions below should keep the PLLM as low as possible.
 861  *
 862  * The output of the PLLM must be between 400 to 600 MHz.
 863  * This rules out prediv of anything but divide-by-one for 24Mhz OSC input.
 864  */
 865 struct da850_opp {
 866         unsigned int    freq;   /* in KHz */
 867         unsigned int    prediv;
 868         unsigned int    mult;
 869         unsigned int    postdiv;
 870         unsigned int    cvdd_min; /* in uV */
 871         unsigned int    cvdd_max; /* in uV */
 872 };
 873
 874 static const struct da850_opp da850_opp_300 = {
 875         .freq           = 300000,
 876         .prediv         = 1,
 877         .mult           = 25,
 878         .postdiv        = 2,
 879         .cvdd_min       = 1140000,
 880         .cvdd_max       = 1320000,
 881 };
 882
 883 static const struct da850_opp da850_opp_200 = {
 884         .freq           = 200000,
 885         .prediv         = 1,
 886         .mult           = 25,
 887         .postdiv        = 3,
 888         .cvdd_min       = 1050000,
 889         .cvdd_max       = 1160000,
 890 };
 891
 892 static const struct da850_opp da850_opp_96 = {
 893         .freq           = 96000,
 894         .prediv         = 1,
 895         .mult           = 20,
 896         .postdiv        = 5,
 897         .cvdd_min       = 950000,
 898         .cvdd_max       = 1050000,
 899 };
 900
 901 #define OPP(freq)               \
 902         {                               \
 903                 .index = (unsigned int) &da850_opp_##freq,      \
 904                 .frequency = freq * 1000, \
 905         }
 906
 907 static struct cpufreq_frequency_table da850_freq_table[] = {
 908         OPP(300),
 909         OPP(200),
 910         OPP(96),
 911         {
 912                 .index          = 0,
 913                 .frequency      = CPUFREQ_TABLE_END,
 914         },
 915 };
 916
 917 #ifdef CONFIG_REGULATOR
 918 static struct regulator *cvdd;
 919
 920 static int da850_set_voltage(unsigned int index)
 921 {
 922         struct da850_opp *opp;
 923
 924         if (!cvdd)
 925                 return -ENODEV;
 926
 927         opp = (struct da850_opp *) da850_freq_table[index].index;
 928
 929         return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
 930 }
 931
 932 static int da850_regulator_init(void)
 933 {
 934         cvdd = regulator_get(NULL, "cvdd");
 935         if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
 936                                         " voltage scaling unsupported\n")) {
 937                 return PTR_ERR(cvdd);
 938         }
 939
 940         return 0;
 941 }
 942 #endif
 943
 944 static struct davinci_cpufreq_config cpufreq_info = {
 945         .freq_table = &da850_freq_table[0],
 946 #ifdef CONFIG_REGULATOR
 947         .init = da850_regulator_init,
 948         .set_voltage = da850_set_voltage,
 949 #endif
 950 };
 951
 952 static struct platform_device da850_cpufreq_device = {
 953         .name                   = "cpufreq-davinci",
 954         .dev = {
 955                 .platform_data  = &cpufreq_info,
 956         },
 957 };
 958
 959 int __init da850_register_cpufreq(void)
 960 {
 961         return platform_device_register(&da850_cpufreq_device);
 962 }
 963
 964 static int da850_round_armrate(struct clk *clk, unsigned long rate)
 965 {
 966         int i, ret = 0, diff;
 967         unsigned int best = (unsigned int) -1;
 968
 969         rate /= 1000; /* convert to kHz */
 970
 971         for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
 972                 diff = da850_freq_table[i].frequency - rate;
 973                 if (diff < 0)
 974                         diff = -diff;
 975
 976                 if (diff < best) {
 977                         best = diff;
 978                         ret = da850_freq_table[i].frequency;
 979                 }
 980         }
 981
 982         return ret * 1000;
 983 }
 984
 985 static int da850_set_armrate(struct clk *clk, unsigned long index)
 986 {
 987         struct clk *pllclk = &pll0_clk;
 988
 989         return clk_set_rate(pllclk, index);
 990 }
 991
 992 static int da850_set_pll0rate(struct clk *clk, unsigned long index)
 993 {
 994         unsigned int prediv, mult, postdiv;
 995         struct da850_opp *opp;
 996         struct pll_data *pll = clk->pll_data;
 997         int ret;
 998
 999         opp = (struct da850_opp *) da850_freq_table[index].index;
1000         prediv = opp->prediv;
1001         mult = opp->mult;
1002         postdiv = opp->postdiv;
1003
1004         ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
1005         if (WARN_ON(ret))
1006                 return ret;
1007
1008         return 0;
1009 }
1010 #else
1011 int __init da850_register_cpufreq(void)
1012 {
1013         return 0;
1014 }
1015
1016 static int da850_set_armrate(struct clk *clk, unsigned long rate)
1017 {
1018         return -EINVAL;
1019 }
1020
1021 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
1022 {
1023         return -EINVAL;
1024 }
1025
1026 static int da850_round_armrate(struct clk *clk, unsigned long rate)
1027 {
1028         return clk->rate;
1029 }
1030 #endif
1031
1032 int da850_register_pm(struct platform_device *pdev)
1033 {
1034         int ret;
1035         struct davinci_pm_config *pdata = pdev->dev.platform_data;
1036
1037         ret = davinci_cfg_reg(DA850_RTC_ALARM);
1038         if (ret)
1039                 return ret;
1040
1041         pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
1042         pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
1043         pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
1044
1045         pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
1046         if (!pdata->cpupll_reg_base)
1047                 return -ENOMEM;
1048
1049         pdata->ddrpll_reg_base = ioremap(DA8XX_PLL1_BASE, SZ_4K);
1050         if (!pdata->ddrpll_reg_base) {
1051                 ret = -ENOMEM;
1052                 goto no_ddrpll_mem;
1053         }
1054
1055         pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
1056         if (!pdata->ddrpsc_reg_base) {
1057                 ret = -ENOMEM;
1058                 goto no_ddrpsc_mem;
1059         }
1060
1061         return platform_device_register(pdev);
1062
1063 no_ddrpsc_mem:
1064         iounmap(pdata->ddrpll_reg_base);
1065 no_ddrpll_mem:
1066         iounmap(pdata->cpupll_reg_base);
1067         return ret;
1068 }
1069
1070 static struct davinci_soc_info davinci_soc_info_da850 = {
1071         .io_desc                = da850_io_desc,
1072         .io_desc_num            = ARRAY_SIZE(da850_io_desc),
1073         .jtag_id_reg            = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
1074         .ids                    = da850_ids,
1075         .ids_num                = ARRAY_SIZE(da850_ids),
1076         .cpu_clks               = da850_clks,
1077         .psc_bases              = da850_psc_bases,
1078         .psc_bases_num          = ARRAY_SIZE(da850_psc_bases),
1079         .pinmux_base            = DA8XX_SYSCFG0_BASE + 0x120,
1080         .pinmux_pins            = da850_pins,
1081         .pinmux_pins_num        = ARRAY_SIZE(da850_pins),
1082         .intc_base              = DA8XX_CP_INTC_BASE,
1083         .intc_type              = DAVINCI_INTC_TYPE_CP_INTC,
1084         .intc_irq_prios         = da850_default_priorities,
1085         .intc_irq_num           = DA850_N_CP_INTC_IRQ,
1086         .timer_info             = &da850_timer_info,
1087         .gpio_type              = GPIO_TYPE_DAVINCI,
1088         .gpio_base              = DA8XX_GPIO_BASE,
1089         .gpio_num               = 144,
1090         .gpio_irq               = IRQ_DA8XX_GPIO0,
1091         .serial_dev             = &da8xx_serial_device,
1092         .emac_pdata             = &da8xx_emac_pdata,
1093         .sram_dma               = DA8XX_ARM_RAM_BASE,
1094         .sram_len               = SZ_8K,
1095         .reset_device           = &da8xx_wdt_device,
1096 };
1097
1098 void __init da850_init(void)
1099 {
1100         unsigned int v;
1101
1102         davinci_common_init(&davinci_soc_info_da850);
1103
1104         da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1105         if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1106                 return;
1107
1108         da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1109         if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
1110                 return;
1111
1112         /*
1113          * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1114          * This helps keeping the peripherals on this domain insulated
1115          * from CPU frequency changes caused by DVFS. The firmware sets
1116          * both PLL0 and PLL1 to the same frequency so, there should not
1117          * be any noticible change even in non-DVFS use cases.
1118          */
1119         da850_set_async3_src(1);
1120
1121         /* Unlock writing to PLL0 registers */
1122         v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1123         v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1124         __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1125
1126         /* Unlock writing to PLL1 registers */
1127         v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1128         v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
1129         __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1130 }