arch/arm/mach-davinci/cpuidle.c

   1 /*
   2  * CPU idle for DaVinci SoCs
   3  *
   4  * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
   5  *
   6  * Derived from Marvell Kirkwood CPU idle code
   7  * (arch/arm/mach-kirkwood/cpuidle.c)
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/cpuidle.h>
  18 #include <linux/io.h>
  19 #include <linux/export.h>
  20 #include <asm/proc-fns.h>
  21
  22 #include <mach/cpuidle.h>
  23 #include <mach/ddr2.h>
  24
  25 #define DAVINCI_CPUIDLE_MAX_STATES      2
  26
  27 struct davinci_ops {
  28         void (*enter) (u32 flags);
  29         void (*exit) (u32 flags);
  30         u32 flags;
  31 };
  32
  33 /* fields in davinci_ops.flags */
  34 #define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN BIT(0)
  35
  36 static struct cpuidle_driver davinci_idle_driver = {
  37         .name   = "cpuidle-davinci",
  38         .owner  = THIS_MODULE,
  39 };
  40
  41 static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
  42 static void __iomem *ddr2_reg_base;
  43
  44 static void davinci_save_ddr_power(int enter, bool pdown)
  45 {
  46         u32 val;
  47
  48         val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);
  49
  50         if (enter) {
  51                 if (pdown)
  52                         val |= DDR2_SRPD_BIT;
  53                 else
  54                         val &= ~DDR2_SRPD_BIT;
  55                 val |= DDR2_LPMODEN_BIT;
  56         } else {
  57                 val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);
  58         }
  59
  60         __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);
  61 }
  62
  63 static void davinci_c2state_enter(u32 flags)
  64 {
  65         davinci_save_ddr_power(1, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
  66 }
  67
  68 static void davinci_c2state_exit(u32 flags)
  69 {
  70         davinci_save_ddr_power(0, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
  71 }
  72
  73 static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = {
  74         [1] = {
  75                 .enter  = davinci_c2state_enter,
  76                 .exit   = davinci_c2state_exit,
  77         },
  78 };
  79
  80 /* Actual code that puts the SoC in different idle states */
  81 static int davinci_enter_idle(struct cpuidle_device *dev,
  82                                                 struct cpuidle_state *state)
  83 {
  84         struct davinci_ops *ops = cpuidle_get_statedata(state);
  85         struct timeval before, after;
  86         int idle_time;
  87
  88         local_irq_disable();
  89         do_gettimeofday(&before);
  90
  91         if (ops && ops->enter)
  92                 ops->enter(ops->flags);
  93         /* Wait for interrupt state */
  94         cpu_do_idle();
  95         if (ops && ops->exit)
  96                 ops->exit(ops->flags);
  97
  98         do_gettimeofday(&after);
  99         local_irq_enable();
 100         idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
 101                         (after.tv_usec - before.tv_usec);
 102         return idle_time;
 103 }
 104
 105 static int __init davinci_cpuidle_probe(struct platform_device *pdev)
 106 {
 107         int ret;
 108         struct cpuidle_device *device;
 109         struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
 110
 111         device = &per_cpu(davinci_cpuidle_device, smp_processor_id());
 112
 113         if (!pdata) {
 114                 dev_err(&pdev->dev, "cannot get platform data\n");
 115                 return -ENOENT;
 116         }
 117
 118         ddr2_reg_base = pdata->ddr2_ctlr_base;
 119
 120         ret = cpuidle_register_driver(&davinci_idle_driver);
 121         if (ret) {
 122                 dev_err(&pdev->dev, "failed to register driver\n");
 123                 return ret;
 124         }
 125
 126         /* Wait for interrupt state */
 127         device->states[0].enter = davinci_enter_idle;
 128         device->states[0].exit_latency = 1;
 129         device->states[0].target_residency = 10000;
 130         device->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
 131         strcpy(device->states[0].name, "WFI");
 132         strcpy(device->states[0].desc, "Wait for interrupt");
 133
 134         /* Wait for interrupt and DDR self refresh state */
 135         device->states[1].enter = davinci_enter_idle;
 136         device->states[1].exit_latency = 10;
 137         device->states[1].target_residency = 10000;
 138         device->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
 139         strcpy(device->states[1].name, "DDR SR");
 140         strcpy(device->states[1].desc, "WFI and DDR Self Refresh");
 141         if (pdata->ddr2_pdown)
 142                 davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN;
 143         cpuidle_set_statedata(&device->states[1], &davinci_states[1]);
 144
 145         device->state_count = DAVINCI_CPUIDLE_MAX_STATES;
 146
 147         ret = cpuidle_register_device(device);
 148         if (ret) {
 149                 dev_err(&pdev->dev, "failed to register device\n");
 150                 cpuidle_unregister_driver(&davinci_idle_driver);
 151                 return ret;
 152         }
 153
 154         return 0;
 155 }
 156
 157 static struct platform_driver davinci_cpuidle_driver = {
 158         .driver = {
 159                 .name   = "cpuidle-davinci",
 160                 .owner  = THIS_MODULE,
 161         },
 162 };
 163
 164 static int __init davinci_cpuidle_init(void)
 165 {
 166         return platform_driver_probe(&davinci_cpuidle_driver,
 167                                                 davinci_cpuidle_probe);
 168 }
 169 device_initcall(davinci_cpuidle_init);
 170