arch/arm/mach-at91/setup.c

   1 /*
   2  * Copyright (C) 2007 Atmel Corporation.
   3  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   4  *
   5  * Under GPLv2
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/io.h>
  10
  11 #include <asm/mach/map.h>
  12
  13 #include <mach/hardware.h>
  14 #include <mach/cpu.h>
  15 #include <mach/at91_dbgu.h>
  16 #include <mach/at91_pmc.h>
  17
  18 #include "soc.h"
  19 #include "generic.h"
  20
  21 struct at91_init_soc __initdata at91_boot_soc;
  22
  23 struct at91_socinfo at91_soc_initdata;
  24 EXPORT_SYMBOL(at91_soc_initdata);
  25
  26 void __init at91rm9200_set_type(int type)
  27 {
  28         if (type == ARCH_REVISON_9200_PQFP)
  29                 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
  30         else
  31                 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
  32 }
  33
  34 void __init at91_init_irq_default(void)
  35 {
  36         at91_init_interrupts(at91_boot_soc.default_irq_priority);
  37 }
  38
  39 void __init at91_init_interrupts(unsigned int *priority)
  40 {
  41         /* Initialize the AIC interrupt controller */
  42         at91_aic_init(priority);
  43
  44         /* Enable GPIO interrupts */
  45         at91_gpio_irq_setup();
  46 }
  47
  48 static struct map_desc at91_io_desc __initdata = {
  49         .virtual        = AT91_VA_BASE_SYS,
  50         .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  51         .length         = SZ_16K,
  52         .type           = MT_DEVICE,
  53 };
  54
  55 #define AT91_DBGU0      0xfffff200
  56 #define AT91_DBGU1      0xffffee00
  57
  58 static void __init soc_detect(u32 dbgu_base)
  59 {
  60         u32 cidr, socid;
  61
  62         cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
  63         socid = cidr & ~AT91_CIDR_VERSION;
  64
  65         switch (socid) {
  66         case ARCH_ID_AT91CAP9: {
  67 #ifdef CONFIG_AT91_PMC_UNIT
  68                 u32 pmc_ver = at91_sys_read(AT91_PMC_VER);
  69
  70                 if (pmc_ver == ARCH_REVISION_CAP9_B)
  71                         at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_B;
  72                 else if (pmc_ver == ARCH_REVISION_CAP9_C)
  73                         at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_C;
  74 #endif
  75                 at91_soc_initdata.type = AT91_SOC_CAP9;
  76                 at91_boot_soc = at91cap9_soc;
  77                 break;
  78         }
  79
  80         case ARCH_ID_AT91RM9200:
  81                 at91_soc_initdata.type = AT91_SOC_RM9200;
  82                 at91_boot_soc = at91rm9200_soc;
  83                 break;
  84
  85         case ARCH_ID_AT91SAM9260:
  86                 at91_soc_initdata.type = AT91_SOC_SAM9260;
  87                 at91_boot_soc = at91sam9260_soc;
  88                 break;
  89
  90         case ARCH_ID_AT91SAM9261:
  91                 at91_soc_initdata.type = AT91_SOC_SAM9261;
  92                 at91_boot_soc = at91sam9261_soc;
  93                 break;
  94
  95         case ARCH_ID_AT91SAM9263:
  96                 at91_soc_initdata.type = AT91_SOC_SAM9263;
  97                 at91_boot_soc = at91sam9263_soc;
  98                 break;
  99
 100         case ARCH_ID_AT91SAM9G20:
 101                 at91_soc_initdata.type = AT91_SOC_SAM9G20;
 102                 at91_boot_soc = at91sam9260_soc;
 103                 break;
 104
 105         case ARCH_ID_AT91SAM9G45:
 106                 at91_soc_initdata.type = AT91_SOC_SAM9G45;
 107                 if (cidr == ARCH_ID_AT91SAM9G45ES)
 108                         at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
 109                 at91_boot_soc = at91sam9g45_soc;
 110                 break;
 111
 112         case ARCH_ID_AT91SAM9RL64:
 113                 at91_soc_initdata.type = AT91_SOC_SAM9RL;
 114                 at91_boot_soc = at91sam9rl_soc;
 115                 break;
 116
 117         case ARCH_ID_AT91SAM9X5:
 118                 at91_soc_initdata.type = AT91_SOC_SAM9X5;
 119                 at91_boot_soc = at91sam9x5_soc;
 120                 break;
 121         }
 122
 123         /* at91sam9g10 */
 124         if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
 125                 at91_soc_initdata.type = AT91_SOC_SAM9G10;
 126                 at91_boot_soc = at91sam9261_soc;
 127         }
 128         /* at91sam9xe */
 129         else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
 130                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 131                 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
 132                 at91_boot_soc = at91sam9260_soc;
 133         }
 134
 135         if (!at91_soc_is_detected())
 136                 return;
 137
 138         at91_soc_initdata.cidr = cidr;
 139
 140         /* sub version of soc */
 141         at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 142
 143         if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
 144                 switch (at91_soc_initdata.exid) {
 145                 case ARCH_EXID_AT91SAM9M10:
 146                         at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
 147                         break;
 148                 case ARCH_EXID_AT91SAM9G46:
 149                         at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
 150                         break;
 151                 case ARCH_EXID_AT91SAM9M11:
 152                         at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
 153                         break;
 154                 }
 155         }
 156
 157         if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
 158                 switch (at91_soc_initdata.exid) {
 159                 case ARCH_EXID_AT91SAM9G15:
 160                         at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
 161                         break;
 162                 case ARCH_EXID_AT91SAM9G35:
 163                         at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
 164                         break;
 165                 case ARCH_EXID_AT91SAM9X35:
 166                         at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
 167                         break;
 168                 case ARCH_EXID_AT91SAM9G25:
 169                         at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
 170                         break;
 171                 case ARCH_EXID_AT91SAM9X25:
 172                         at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
 173                         break;
 174                 }
 175         }
 176 }
 177
 178 static const char *soc_name[] = {
 179         [AT91_SOC_RM9200]       = "at91rm9200",
 180         [AT91_SOC_CAP9]         = "at91cap9",
 181         [AT91_SOC_SAM9260]      = "at91sam9260",
 182         [AT91_SOC_SAM9261]      = "at91sam9261",
 183         [AT91_SOC_SAM9263]      = "at91sam9263",
 184         [AT91_SOC_SAM9G10]      = "at91sam9g10",
 185         [AT91_SOC_SAM9G20]      = "at91sam9g20",
 186         [AT91_SOC_SAM9G45]      = "at91sam9g45",
 187         [AT91_SOC_SAM9RL]       = "at91sam9rl",
 188         [AT91_SOC_SAM9X5]       = "at91sam9x5",
 189         [AT91_SOC_NONE]         = "Unknown"
 190 };
 191
 192 const char *at91_get_soc_type(struct at91_socinfo *c)
 193 {
 194         return soc_name[c->type];
 195 }
 196 EXPORT_SYMBOL(at91_get_soc_type);
 197
 198 static const char *soc_subtype_name[] = {
 199         [AT91_SOC_RM9200_BGA]   = "at91rm9200 BGA",
 200         [AT91_SOC_RM9200_PQFP]  = "at91rm9200 PQFP",
 201         [AT91_SOC_CAP9_REV_B]   = "at91cap9 revB",
 202         [AT91_SOC_CAP9_REV_C]   = "at91cap9 revC",
 203         [AT91_SOC_SAM9XE]       = "at91sam9xe",
 204         [AT91_SOC_SAM9G45ES]    = "at91sam9g45es",
 205         [AT91_SOC_SAM9M10]      = "at91sam9m10",
 206         [AT91_SOC_SAM9G46]      = "at91sam9g46",
 207         [AT91_SOC_SAM9M11]      = "at91sam9m11",
 208         [AT91_SOC_SAM9G15]      = "at91sam9g15",
 209         [AT91_SOC_SAM9G35]      = "at91sam9g35",
 210         [AT91_SOC_SAM9X35]      = "at91sam9x35",
 211         [AT91_SOC_SAM9G25]      = "at91sam9g25",
 212         [AT91_SOC_SAM9X25]      = "at91sam9x25",
 213         [AT91_SOC_SUBTYPE_NONE] = "Unknown"
 214 };
 215
 216 const char *at91_get_soc_subtype(struct at91_socinfo *c)
 217 {
 218         return soc_subtype_name[c->subtype];
 219 }
 220 EXPORT_SYMBOL(at91_get_soc_subtype);
 221
 222 void __init at91_map_io(void)
 223 {
 224         /* Map peripherals */
 225         iotable_init(&at91_io_desc, 1);
 226
 227         at91_soc_initdata.type = AT91_SOC_NONE;
 228         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 229
 230         soc_detect(AT91_DBGU0);
 231         if (!at91_soc_is_detected())
 232                 soc_detect(AT91_DBGU1);
 233
 234         if (!at91_soc_is_detected())
 235                 panic("AT91: Impossible to detect the SOC type");
 236
 237         pr_info("AT91: Detected soc type: %s\n",
 238                 at91_get_soc_type(&at91_soc_initdata));
 239         pr_info("AT91: Detected soc subtype: %s\n",
 240                 at91_get_soc_subtype(&at91_soc_initdata));
 241
 242         if (!at91_soc_is_enabled())
 243                 panic("AT91: Soc not enabled");
 244
 245         if (at91_boot_soc.map_io)
 246                 at91_boot_soc.map_io();
 247 }
 248
 249 void __init at91_initialize(unsigned long main_clock)
 250 {
 251         /* Init clock subsystem */
 252         at91_clock_init(main_clock);
 253
 254         /* Register the processor-specific clocks */
 255         at91_boot_soc.register_clocks();
 256
 257         at91_boot_soc.init();
 258 }