2 * arch/arm/mach-at91/at91sam9rl.c
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Atmel Corporation
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
12 #include <linux/module.h>
16 #include <asm/mach/arch.h>
17 #include <asm/mach/map.h>
19 #include <mach/at91_dbgu.h>
20 #include <mach/at91sam9rl.h>
21 #include <mach/at91_pmc.h>
22 #include <mach/at91_rstc.h>
23 #include <mach/at91_shdwc.h>
29 static struct map_desc at91sam9rl_sram_desc[] __initdata = {
31 .pfn = __phys_to_pfn(AT91SAM9RL_SRAM_BASE),
36 /* --------------------------------------------------------------------
38 * -------------------------------------------------------------------- */
41 * The peripheral clocks.
43 static struct clk pioA_clk = {
45 .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
46 .type = CLK_TYPE_PERIPHERAL,
48 static struct clk pioB_clk = {
50 .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
51 .type = CLK_TYPE_PERIPHERAL,
53 static struct clk pioC_clk = {
55 .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
56 .type = CLK_TYPE_PERIPHERAL,
58 static struct clk pioD_clk = {
60 .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
61 .type = CLK_TYPE_PERIPHERAL,
63 static struct clk usart0_clk = {
65 .pmc_mask = 1 << AT91SAM9RL_ID_US0,
66 .type = CLK_TYPE_PERIPHERAL,
68 static struct clk usart1_clk = {
70 .pmc_mask = 1 << AT91SAM9RL_ID_US1,
71 .type = CLK_TYPE_PERIPHERAL,
73 static struct clk usart2_clk = {
75 .pmc_mask = 1 << AT91SAM9RL_ID_US2,
76 .type = CLK_TYPE_PERIPHERAL,
78 static struct clk usart3_clk = {
80 .pmc_mask = 1 << AT91SAM9RL_ID_US3,
81 .type = CLK_TYPE_PERIPHERAL,
83 static struct clk mmc_clk = {
85 .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
86 .type = CLK_TYPE_PERIPHERAL,
88 static struct clk twi0_clk = {
90 .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
91 .type = CLK_TYPE_PERIPHERAL,
93 static struct clk twi1_clk = {
95 .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
96 .type = CLK_TYPE_PERIPHERAL,
98 static struct clk spi_clk = {
100 .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
101 .type = CLK_TYPE_PERIPHERAL,
103 static struct clk ssc0_clk = {
105 .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
106 .type = CLK_TYPE_PERIPHERAL,
108 static struct clk ssc1_clk = {
110 .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
111 .type = CLK_TYPE_PERIPHERAL,
113 static struct clk tc0_clk = {
115 .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
116 .type = CLK_TYPE_PERIPHERAL,
118 static struct clk tc1_clk = {
120 .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
121 .type = CLK_TYPE_PERIPHERAL,
123 static struct clk tc2_clk = {
125 .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
126 .type = CLK_TYPE_PERIPHERAL,
128 static struct clk pwm_clk = {
130 .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
131 .type = CLK_TYPE_PERIPHERAL,
133 static struct clk tsc_clk = {
135 .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
136 .type = CLK_TYPE_PERIPHERAL,
138 static struct clk dma_clk = {
140 .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
141 .type = CLK_TYPE_PERIPHERAL,
143 static struct clk udphs_clk = {
145 .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
146 .type = CLK_TYPE_PERIPHERAL,
148 static struct clk lcdc_clk = {
150 .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
151 .type = CLK_TYPE_PERIPHERAL,
153 static struct clk ac97_clk = {
155 .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
156 .type = CLK_TYPE_PERIPHERAL,
159 static struct clk *periph_clocks[] __initdata = {
186 static struct clk_lookup periph_clocks_lookups[] = {
187 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
188 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
189 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
190 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
191 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
192 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
193 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
196 static struct clk_lookup usart_clocks_lookups[] = {
197 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
198 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
199 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
200 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
201 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
205 * The two programmable clocks.
206 * You must configure pin multiplexing to bring these signals out.
208 static struct clk pck0 = {
210 .pmc_mask = AT91_PMC_PCK0,
211 .type = CLK_TYPE_PROGRAMMABLE,
214 static struct clk pck1 = {
216 .pmc_mask = AT91_PMC_PCK1,
217 .type = CLK_TYPE_PROGRAMMABLE,
221 static void __init at91sam9rl_register_clocks(void)
225 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
226 clk_register(periph_clocks[i]);
228 clkdev_add_table(periph_clocks_lookups,
229 ARRAY_SIZE(periph_clocks_lookups));
230 clkdev_add_table(usart_clocks_lookups,
231 ARRAY_SIZE(usart_clocks_lookups));
237 static struct clk_lookup console_clock_lookup;
239 void __init at91sam9rl_set_console_clock(int id)
241 if (id >= ARRAY_SIZE(usart_clocks_lookups))
244 console_clock_lookup.con_id = "usart";
245 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
246 clkdev_add(&console_clock_lookup);
249 /* --------------------------------------------------------------------
251 * -------------------------------------------------------------------- */
253 static struct at91_gpio_bank at91sam9rl_gpio[] = {
255 .id = AT91SAM9RL_ID_PIOA,
259 .id = AT91SAM9RL_ID_PIOB,
263 .id = AT91SAM9RL_ID_PIOC,
267 .id = AT91SAM9RL_ID_PIOD,
273 static void at91sam9rl_poweroff(void)
275 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
279 /* --------------------------------------------------------------------
280 * AT91SAM9RL processor initialization
281 * -------------------------------------------------------------------- */
283 static void __init at91sam9rl_map_io(void)
285 unsigned long sram_size;
287 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
288 case AT91_CIDR_SRAMSIZ_32K:
289 sram_size = 2 * SZ_16K;
291 case AT91_CIDR_SRAMSIZ_16K:
296 at91sam9rl_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
297 at91sam9rl_sram_desc->length = sram_size;
300 iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
303 static void __init at91sam9rl_initialize(void)
305 at91_arch_reset = at91sam9_alt_reset;
306 pm_power_off = at91sam9rl_poweroff;
307 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
309 /* Register GPIO subsystem */
310 at91_gpio_init(at91sam9rl_gpio, 4);
313 /* --------------------------------------------------------------------
314 * Interrupt initialization
315 * -------------------------------------------------------------------- */
318 * The default interrupt priority levels (0 = lowest, 7 = highest).
320 static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
321 7, /* Advanced Interrupt Controller */
322 7, /* System Peripherals */
323 1, /* Parallel IO Controller A */
324 1, /* Parallel IO Controller B */
325 1, /* Parallel IO Controller C */
326 1, /* Parallel IO Controller D */
331 0, /* Multimedia Card Interface */
332 6, /* Two-Wire Interface 0 */
333 6, /* Two-Wire Interface 1 */
334 5, /* Serial Peripheral Interface */
335 4, /* Serial Synchronous Controller 0 */
336 4, /* Serial Synchronous Controller 1 */
337 0, /* Timer Counter 0 */
338 0, /* Timer Counter 1 */
339 0, /* Timer Counter 2 */
341 0, /* Touch Screen Controller */
342 0, /* DMA Controller */
343 2, /* USB Device High speed port */
344 2, /* LCD Controller */
345 6, /* AC97 Controller */
352 0, /* Advanced Interrupt Controller */
355 struct at91_init_soc __initdata at91sam9rl_soc = {
356 .map_io = at91sam9rl_map_io,
357 .default_irq_priority = at91sam9rl_default_irq_priority,
358 .register_clocks = at91sam9rl_register_clocks,
359 .init = at91sam9rl_initialize,