arch/arm/mach-at91/at91sam9g45_devices.c

   1 /*
   2  *  On-Chip devices setup code for the AT91SAM9G45 family
   3  *
   4  *  Copyright (C) 2009 Atmel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12 #include <asm/mach/arch.h>
  13 #include <asm/mach/map.h>
  14
  15 #include <linux/dma-mapping.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/i2c-gpio.h>
  18 #include <linux/atmel-mci.h>
  19
  20 #include <linux/fb.h>
  21 #include <video/atmel_lcdc.h>
  22
  23 #include <mach/board.h>
  24 #include <mach/gpio.h>
  25 #include <mach/at91sam9g45.h>
  26 #include <mach/at91sam9g45_matrix.h>
  27 #include <mach/at91sam9_smc.h>
  28 #include <mach/at_hdmac.h>
  29 #include <mach/atmel-mci.h>
  30
  31 #include "generic.h"
  32
  33
  34 /* --------------------------------------------------------------------
  35  *  HDMAC - AHB DMA Controller
  36  * -------------------------------------------------------------------- */
  37
  38 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
  39 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
  40
  41 static struct at_dma_platform_data atdma_pdata = {
  42         .nr_channels    = 8,
  43 };
  44
  45 static struct resource hdmac_resources[] = {
  46         [0] = {
  47                 .start  = AT91_BASE_SYS + AT91_DMA,
  48                 .end    = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1,
  49                 .flags  = IORESOURCE_MEM,
  50         },
  51         [1] = {
  52                 .start  = AT91SAM9G45_ID_DMA,
  53                 .end    = AT91SAM9G45_ID_DMA,
  54                 .flags  = IORESOURCE_IRQ,
  55         },
  56 };
  57
  58 static struct platform_device at_hdmac_device = {
  59         .name           = "at_hdmac",
  60         .id             = -1,
  61         .dev            = {
  62                                 .dma_mask               = &hdmac_dmamask,
  63                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
  64                                 .platform_data          = &atdma_pdata,
  65         },
  66         .resource       = hdmac_resources,
  67         .num_resources  = ARRAY_SIZE(hdmac_resources),
  68 };
  69
  70 void __init at91_add_device_hdmac(void)
  71 {
  72         dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
  73         dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask);
  74         platform_device_register(&at_hdmac_device);
  75 }
  76 #else
  77 void __init at91_add_device_hdmac(void) {}
  78 #endif
  79
  80
  81 /* --------------------------------------------------------------------
  82  *  USB Host (OHCI)
  83  * -------------------------------------------------------------------- */
  84
  85 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  86 static u64 ohci_dmamask = DMA_BIT_MASK(32);
  87 static struct at91_usbh_data usbh_ohci_data;
  88
  89 static struct resource usbh_ohci_resources[] = {
  90         [0] = {
  91                 .start  = AT91SAM9G45_OHCI_BASE,
  92                 .end    = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
  93                 .flags  = IORESOURCE_MEM,
  94         },
  95         [1] = {
  96                 .start  = AT91SAM9G45_ID_UHPHS,
  97                 .end    = AT91SAM9G45_ID_UHPHS,
  98                 .flags  = IORESOURCE_IRQ,
  99         },
 100 };
 101
 102 static struct platform_device at91_usbh_ohci_device = {
 103         .name           = "at91_ohci",
 104         .id             = -1,
 105         .dev            = {
 106                                 .dma_mask               = &ohci_dmamask,
 107                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 108                                 .platform_data          = &usbh_ohci_data,
 109         },
 110         .resource       = usbh_ohci_resources,
 111         .num_resources  = ARRAY_SIZE(usbh_ohci_resources),
 112 };
 113
 114 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
 115 {
 116         int i;
 117
 118         if (!data)
 119                 return;
 120
 121         /* Enable VBus control for UHP ports */
 122         for (i = 0; i < data->ports; i++) {
 123                 if (data->vbus_pin[i])
 124                         at91_set_gpio_output(data->vbus_pin[i], 0);
 125         }
 126
 127         usbh_ohci_data = *data;
 128         platform_device_register(&at91_usbh_ohci_device);
 129 }
 130 #else
 131 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
 132 #endif
 133
 134
 135 /* --------------------------------------------------------------------
 136  *  USB Host HS (EHCI)
 137  *  Needs an OHCI host for low and full speed management
 138  * -------------------------------------------------------------------- */
 139
 140 #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
 141 static u64 ehci_dmamask = DMA_BIT_MASK(32);
 142 static struct at91_usbh_data usbh_ehci_data;
 143
 144 static struct resource usbh_ehci_resources[] = {
 145         [0] = {
 146                 .start  = AT91SAM9G45_EHCI_BASE,
 147                 .end    = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
 148                 .flags  = IORESOURCE_MEM,
 149         },
 150         [1] = {
 151                 .start  = AT91SAM9G45_ID_UHPHS,
 152                 .end    = AT91SAM9G45_ID_UHPHS,
 153                 .flags  = IORESOURCE_IRQ,
 154         },
 155 };
 156
 157 static struct platform_device at91_usbh_ehci_device = {
 158         .name           = "atmel-ehci",
 159         .id             = -1,
 160         .dev            = {
 161                                 .dma_mask               = &ehci_dmamask,
 162                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 163                                 .platform_data          = &usbh_ehci_data,
 164         },
 165         .resource       = usbh_ehci_resources,
 166         .num_resources  = ARRAY_SIZE(usbh_ehci_resources),
 167 };
 168
 169 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
 170 {
 171         int i;
 172
 173         if (!data)
 174                 return;
 175
 176         /* Enable VBus control for UHP ports */
 177         for (i = 0; i < data->ports; i++) {
 178                 if (data->vbus_pin[i])
 179                         at91_set_gpio_output(data->vbus_pin[i], 0);
 180         }
 181
 182         usbh_ehci_data = *data;
 183         at91_clock_associate("uhphs_clk", &at91_usbh_ehci_device.dev, "ehci_clk");
 184         platform_device_register(&at91_usbh_ehci_device);
 185 }
 186 #else
 187 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
 188 #endif
 189
 190
 191 /* --------------------------------------------------------------------
 192  *  USB HS Device (Gadget)
 193  * -------------------------------------------------------------------- */
 194
 195 #if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
 196 static struct resource usba_udc_resources[] = {
 197         [0] = {
 198                 .start  = AT91SAM9G45_UDPHS_FIFO,
 199                 .end    = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
 200                 .flags  = IORESOURCE_MEM,
 201         },
 202         [1] = {
 203                 .start  = AT91SAM9G45_BASE_UDPHS,
 204                 .end    = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
 205                 .flags  = IORESOURCE_MEM,
 206         },
 207         [2] = {
 208                 .start  = AT91SAM9G45_ID_UDPHS,
 209                 .end    = AT91SAM9G45_ID_UDPHS,
 210                 .flags  = IORESOURCE_IRQ,
 211         },
 212 };
 213
 214 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
 215         [idx] = {                                               \
 216                 .name           = nam,                          \
 217                 .index          = idx,                          \
 218                 .fifo_size      = maxpkt,                       \
 219                 .nr_banks       = maxbk,                        \
 220                 .can_dma        = dma,                          \
 221                 .can_isoc       = isoc,                         \
 222         }
 223
 224 static struct usba_ep_data usba_udc_ep[] __initdata = {
 225         EP("ep0", 0, 64, 1, 0, 0),
 226         EP("ep1", 1, 1024, 2, 1, 1),
 227         EP("ep2", 2, 1024, 2, 1, 1),
 228         EP("ep3", 3, 1024, 3, 1, 0),
 229         EP("ep4", 4, 1024, 3, 1, 0),
 230         EP("ep5", 5, 1024, 3, 1, 1),
 231         EP("ep6", 6, 1024, 3, 1, 1),
 232 };
 233
 234 #undef EP
 235
 236 /*
 237  * pdata doesn't have room for any endpoints, so we need to
 238  * append room for the ones we need right after it.
 239  */
 240 static struct {
 241         struct usba_platform_data pdata;
 242         struct usba_ep_data ep[7];
 243 } usba_udc_data;
 244
 245 static struct platform_device at91_usba_udc_device = {
 246         .name           = "atmel_usba_udc",
 247         .id             = -1,
 248         .dev            = {
 249                                 .platform_data  = &usba_udc_data.pdata,
 250         },
 251         .resource       = usba_udc_resources,
 252         .num_resources  = ARRAY_SIZE(usba_udc_resources),
 253 };
 254
 255 void __init at91_add_device_usba(struct usba_platform_data *data)
 256 {
 257         usba_udc_data.pdata.vbus_pin = -EINVAL;
 258         usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
 259         memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
 260
 261         if (data && data->vbus_pin > 0) {
 262                 at91_set_gpio_input(data->vbus_pin, 0);
 263                 at91_set_deglitch(data->vbus_pin, 1);
 264                 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
 265         }
 266
 267         /* Pullup pin is handled internally by USB device peripheral */
 268
 269         /* Clocks */
 270         at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
 271         at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
 272
 273         platform_device_register(&at91_usba_udc_device);
 274 }
 275 #else
 276 void __init at91_add_device_usba(struct usba_platform_data *data) {}
 277 #endif
 278
 279
 280 /* --------------------------------------------------------------------
 281  *  Ethernet
 282  * -------------------------------------------------------------------- */
 283
 284 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
 285 static u64 eth_dmamask = DMA_BIT_MASK(32);
 286 static struct at91_eth_data eth_data;
 287
 288 static struct resource eth_resources[] = {
 289         [0] = {
 290                 .start  = AT91SAM9G45_BASE_EMAC,
 291                 .end    = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
 292                 .flags  = IORESOURCE_MEM,
 293         },
 294         [1] = {
 295                 .start  = AT91SAM9G45_ID_EMAC,
 296                 .end    = AT91SAM9G45_ID_EMAC,
 297                 .flags  = IORESOURCE_IRQ,
 298         },
 299 };
 300
 301 static struct platform_device at91sam9g45_eth_device = {
 302         .name           = "macb",
 303         .id             = -1,
 304         .dev            = {
 305                                 .dma_mask               = &eth_dmamask,
 306                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 307                                 .platform_data          = &eth_data,
 308         },
 309         .resource       = eth_resources,
 310         .num_resources  = ARRAY_SIZE(eth_resources),
 311 };
 312
 313 void __init at91_add_device_eth(struct at91_eth_data *data)
 314 {
 315         if (!data)
 316                 return;
 317
 318         if (data->phy_irq_pin) {
 319                 at91_set_gpio_input(data->phy_irq_pin, 0);
 320                 at91_set_deglitch(data->phy_irq_pin, 1);
 321         }
 322
 323         /* Pins used for MII and RMII */
 324         at91_set_A_periph(AT91_PIN_PA17, 0);    /* ETXCK_EREFCK */
 325         at91_set_A_periph(AT91_PIN_PA15, 0);    /* ERXDV */
 326         at91_set_A_periph(AT91_PIN_PA12, 0);    /* ERX0 */
 327         at91_set_A_periph(AT91_PIN_PA13, 0);    /* ERX1 */
 328         at91_set_A_periph(AT91_PIN_PA16, 0);    /* ERXER */
 329         at91_set_A_periph(AT91_PIN_PA14, 0);    /* ETXEN */
 330         at91_set_A_periph(AT91_PIN_PA10, 0);    /* ETX0 */
 331         at91_set_A_periph(AT91_PIN_PA11, 0);    /* ETX1 */
 332         at91_set_A_periph(AT91_PIN_PA19, 0);    /* EMDIO */
 333         at91_set_A_periph(AT91_PIN_PA18, 0);    /* EMDC */
 334
 335         if (!data->is_rmii) {
 336                 at91_set_B_periph(AT91_PIN_PA29, 0);    /* ECRS */
 337                 at91_set_B_periph(AT91_PIN_PA30, 0);    /* ECOL */
 338                 at91_set_B_periph(AT91_PIN_PA8,  0);    /* ERX2 */
 339                 at91_set_B_periph(AT91_PIN_PA9,  0);    /* ERX3 */
 340                 at91_set_B_periph(AT91_PIN_PA28, 0);    /* ERXCK */
 341                 at91_set_B_periph(AT91_PIN_PA6,  0);    /* ETX2 */
 342                 at91_set_B_periph(AT91_PIN_PA7,  0);    /* ETX3 */
 343                 at91_set_B_periph(AT91_PIN_PA27, 0);    /* ETXER */
 344         }
 345
 346         eth_data = *data;
 347         platform_device_register(&at91sam9g45_eth_device);
 348 }
 349 #else
 350 void __init at91_add_device_eth(struct at91_eth_data *data) {}
 351 #endif
 352
 353
 354 /* --------------------------------------------------------------------
 355  *  MMC / SD
 356  * -------------------------------------------------------------------- */
 357
 358 #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
 359 static u64 mmc_dmamask = DMA_BIT_MASK(32);
 360 static struct mci_platform_data mmc0_data, mmc1_data;
 361
 362 static struct resource mmc0_resources[] = {
 363         [0] = {
 364                 .start  = AT91SAM9G45_BASE_MCI0,
 365                 .end    = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
 366                 .flags  = IORESOURCE_MEM,
 367         },
 368         [1] = {
 369                 .start  = AT91SAM9G45_ID_MCI0,
 370                 .end    = AT91SAM9G45_ID_MCI0,
 371                 .flags  = IORESOURCE_IRQ,
 372         },
 373 };
 374
 375 static struct platform_device at91sam9g45_mmc0_device = {
 376         .name           = "atmel_mci",
 377         .id             = 0,
 378         .dev            = {
 379                                 .dma_mask               = &mmc_dmamask,
 380                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 381                                 .platform_data          = &mmc0_data,
 382         },
 383         .resource       = mmc0_resources,
 384         .num_resources  = ARRAY_SIZE(mmc0_resources),
 385 };
 386
 387 static struct resource mmc1_resources[] = {
 388         [0] = {
 389                 .start  = AT91SAM9G45_BASE_MCI1,
 390                 .end    = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
 391                 .flags  = IORESOURCE_MEM,
 392         },
 393         [1] = {
 394                 .start  = AT91SAM9G45_ID_MCI1,
 395                 .end    = AT91SAM9G45_ID_MCI1,
 396                 .flags  = IORESOURCE_IRQ,
 397         },
 398 };
 399
 400 static struct platform_device at91sam9g45_mmc1_device = {
 401         .name           = "atmel_mci",
 402         .id             = 1,
 403         .dev            = {
 404                                 .dma_mask               = &mmc_dmamask,
 405                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 406                                 .platform_data          = &mmc1_data,
 407         },
 408         .resource       = mmc1_resources,
 409         .num_resources  = ARRAY_SIZE(mmc1_resources),
 410 };
 411
 412 /* Consider only one slot : slot 0 */
 413 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
 414 {
 415
 416         if (!data)
 417                 return;
 418
 419         /* Must have at least one usable slot */
 420         if (!data->slot[0].bus_width)
 421                 return;
 422
 423 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
 424         {
 425         struct at_dma_slave     *atslave;
 426         struct mci_dma_data     *alt_atslave;
 427
 428         alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
 429         atslave = &alt_atslave->sdata;
 430
 431         /* DMA slave channel configuration */
 432         atslave->dma_dev = &at_hdmac_device.dev;
 433         atslave->reg_width = AT_DMA_SLAVE_WIDTH_32BIT;
 434         atslave->cfg = ATC_FIFOCFG_HALFFIFO
 435                         | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
 436         atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16;
 437         if (mmc_id == 0)        /* MCI0 */
 438                 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
 439                               | ATC_DST_PER(AT_DMA_ID_MCI0);
 440
 441         else                    /* MCI1 */
 442                 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
 443                               | ATC_DST_PER(AT_DMA_ID_MCI1);
 444
 445         data->dma_slave = alt_atslave;
 446         }
 447 #endif
 448
 449
 450         /* input/irq */
 451         if (data->slot[0].detect_pin) {
 452                 at91_set_gpio_input(data->slot[0].detect_pin, 1);
 453                 at91_set_deglitch(data->slot[0].detect_pin, 1);
 454         }
 455         if (data->slot[0].wp_pin)
 456                 at91_set_gpio_input(data->slot[0].wp_pin, 1);
 457
 458         if (mmc_id == 0) {              /* MCI0 */
 459
 460                 /* CLK */
 461                 at91_set_A_periph(AT91_PIN_PA0, 0);
 462
 463                 /* CMD */
 464                 at91_set_A_periph(AT91_PIN_PA1, 1);
 465
 466                 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
 467                 at91_set_A_periph(AT91_PIN_PA2, 1);
 468                 if (data->slot[0].bus_width == 4) {
 469                         at91_set_A_periph(AT91_PIN_PA3, 1);
 470                         at91_set_A_periph(AT91_PIN_PA4, 1);
 471                         at91_set_A_periph(AT91_PIN_PA5, 1);
 472                         if (data->slot[0].bus_width == 8) {
 473                                 at91_set_A_periph(AT91_PIN_PA6, 1);
 474                                 at91_set_A_periph(AT91_PIN_PA7, 1);
 475                                 at91_set_A_periph(AT91_PIN_PA8, 1);
 476                                 at91_set_A_periph(AT91_PIN_PA9, 1);
 477                         }
 478                 }
 479
 480                 mmc0_data = *data;
 481                 at91_clock_associate("mci0_clk", &at91sam9g45_mmc0_device.dev, "mci_clk");
 482                 platform_device_register(&at91sam9g45_mmc0_device);
 483
 484         } else {                        /* MCI1 */
 485
 486                 /* CLK */
 487                 at91_set_A_periph(AT91_PIN_PA31, 0);
 488
 489                 /* CMD */
 490                 at91_set_A_periph(AT91_PIN_PA22, 1);
 491
 492                 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
 493                 at91_set_A_periph(AT91_PIN_PA23, 1);
 494                 if (data->slot[0].bus_width == 4) {
 495                         at91_set_A_periph(AT91_PIN_PA24, 1);
 496                         at91_set_A_periph(AT91_PIN_PA25, 1);
 497                         at91_set_A_periph(AT91_PIN_PA26, 1);
 498                         if (data->slot[0].bus_width == 8) {
 499                                 at91_set_A_periph(AT91_PIN_PA27, 1);
 500                                 at91_set_A_periph(AT91_PIN_PA28, 1);
 501                                 at91_set_A_periph(AT91_PIN_PA29, 1);
 502                                 at91_set_A_periph(AT91_PIN_PA30, 1);
 503                         }
 504                 }
 505
 506                 mmc1_data = *data;
 507                 at91_clock_associate("mci1_clk", &at91sam9g45_mmc1_device.dev, "mci_clk");
 508                 platform_device_register(&at91sam9g45_mmc1_device);
 509
 510         }
 511 }
 512 #else
 513 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
 514 #endif
 515
 516
 517 /* --------------------------------------------------------------------
 518  *  NAND / SmartMedia
 519  * -------------------------------------------------------------------- */
 520
 521 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
 522 static struct atmel_nand_data nand_data;
 523
 524 #define NAND_BASE       AT91_CHIPSELECT_3
 525
 526 static struct resource nand_resources[] = {
 527         [0] = {
 528                 .start  = NAND_BASE,
 529                 .end    = NAND_BASE + SZ_256M - 1,
 530                 .flags  = IORESOURCE_MEM,
 531         },
 532         [1] = {
 533                 .start  = AT91_BASE_SYS + AT91_ECC,
 534                 .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
 535                 .flags  = IORESOURCE_MEM,
 536         }
 537 };
 538
 539 static struct platform_device at91sam9g45_nand_device = {
 540         .name           = "atmel_nand",
 541         .id             = -1,
 542         .dev            = {
 543                                 .platform_data  = &nand_data,
 544         },
 545         .resource       = nand_resources,
 546         .num_resources  = ARRAY_SIZE(nand_resources),
 547 };
 548
 549 void __init at91_add_device_nand(struct atmel_nand_data *data)
 550 {
 551         unsigned long csa;
 552
 553         if (!data)
 554                 return;
 555
 556         csa = at91_sys_read(AT91_MATRIX_EBICSA);
 557         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
 558
 559         /* enable pin */
 560         if (data->enable_pin)
 561                 at91_set_gpio_output(data->enable_pin, 1);
 562
 563         /* ready/busy pin */
 564         if (data->rdy_pin)
 565                 at91_set_gpio_input(data->rdy_pin, 1);
 566
 567         /* card detect pin */
 568         if (data->det_pin)
 569                 at91_set_gpio_input(data->det_pin, 1);
 570
 571         nand_data = *data;
 572         platform_device_register(&at91sam9g45_nand_device);
 573 }
 574 #else
 575 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
 576 #endif
 577
 578
 579 /* --------------------------------------------------------------------
 580  *  TWI (i2c)
 581  * -------------------------------------------------------------------- */
 582
 583 /*
 584  * Prefer the GPIO code since the TWI controller isn't robust
 585  * (gets overruns and underruns under load) and can only issue
 586  * repeated STARTs in one scenario (the driver doesn't yet handle them).
 587  */
 588 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
 589 static struct i2c_gpio_platform_data pdata_i2c0 = {
 590         .sda_pin                = AT91_PIN_PA20,
 591         .sda_is_open_drain      = 1,
 592         .scl_pin                = AT91_PIN_PA21,
 593         .scl_is_open_drain      = 1,
 594         .udelay                 = 5,            /* ~100 kHz */
 595 };
 596
 597 static struct platform_device at91sam9g45_twi0_device = {
 598         .name                   = "i2c-gpio",
 599         .id                     = 0,
 600         .dev.platform_data      = &pdata_i2c0,
 601 };
 602
 603 static struct i2c_gpio_platform_data pdata_i2c1 = {
 604         .sda_pin                = AT91_PIN_PB10,
 605         .sda_is_open_drain      = 1,
 606         .scl_pin                = AT91_PIN_PB11,
 607         .scl_is_open_drain      = 1,
 608         .udelay                 = 5,            /* ~100 kHz */
 609 };
 610
 611 static struct platform_device at91sam9g45_twi1_device = {
 612         .name                   = "i2c-gpio",
 613         .id                     = 1,
 614         .dev.platform_data      = &pdata_i2c1,
 615 };
 616
 617 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
 618 {
 619         i2c_register_board_info(i2c_id, devices, nr_devices);
 620
 621         if (i2c_id == 0) {
 622                 at91_set_GPIO_periph(AT91_PIN_PA20, 1);         /* TWD (SDA) */
 623                 at91_set_multi_drive(AT91_PIN_PA20, 1);
 624
 625                 at91_set_GPIO_periph(AT91_PIN_PA21, 1);         /* TWCK (SCL) */
 626                 at91_set_multi_drive(AT91_PIN_PA21, 1);
 627
 628                 platform_device_register(&at91sam9g45_twi0_device);
 629         } else {
 630                 at91_set_GPIO_periph(AT91_PIN_PB10, 1);         /* TWD (SDA) */
 631                 at91_set_multi_drive(AT91_PIN_PB10, 1);
 632
 633                 at91_set_GPIO_periph(AT91_PIN_PB11, 1);         /* TWCK (SCL) */
 634                 at91_set_multi_drive(AT91_PIN_PB11, 1);
 635
 636                 platform_device_register(&at91sam9g45_twi1_device);
 637         }
 638 }
 639
 640 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
 641 static struct resource twi0_resources[] = {
 642         [0] = {
 643                 .start  = AT91SAM9G45_BASE_TWI0,
 644                 .end    = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
 645                 .flags  = IORESOURCE_MEM,
 646         },
 647         [1] = {
 648                 .start  = AT91SAM9G45_ID_TWI0,
 649                 .end    = AT91SAM9G45_ID_TWI0,
 650                 .flags  = IORESOURCE_IRQ,
 651         },
 652 };
 653
 654 static struct platform_device at91sam9g45_twi0_device = {
 655         .name           = "at91_i2c",
 656         .id             = 0,
 657         .resource       = twi0_resources,
 658         .num_resources  = ARRAY_SIZE(twi0_resources),
 659 };
 660
 661 static struct resource twi1_resources[] = {
 662         [0] = {
 663                 .start  = AT91SAM9G45_BASE_TWI1,
 664                 .end    = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
 665                 .flags  = IORESOURCE_MEM,
 666         },
 667         [1] = {
 668                 .start  = AT91SAM9G45_ID_TWI1,
 669                 .end    = AT91SAM9G45_ID_TWI1,
 670                 .flags  = IORESOURCE_IRQ,
 671         },
 672 };
 673
 674 static struct platform_device at91sam9g45_twi1_device = {
 675         .name           = "at91_i2c",
 676         .id             = 1,
 677         .resource       = twi1_resources,
 678         .num_resources  = ARRAY_SIZE(twi1_resources),
 679 };
 680
 681 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
 682 {
 683         i2c_register_board_info(i2c_id, devices, nr_devices);
 684
 685         /* pins used for TWI interface */
 686         if (i2c_id == 0) {
 687                 at91_set_A_periph(AT91_PIN_PA20, 0);            /* TWD */
 688                 at91_set_multi_drive(AT91_PIN_PA20, 1);
 689
 690                 at91_set_A_periph(AT91_PIN_PA21, 0);            /* TWCK */
 691                 at91_set_multi_drive(AT91_PIN_PA21, 1);
 692
 693                 platform_device_register(&at91sam9g45_twi0_device);
 694         } else {
 695                 at91_set_A_periph(AT91_PIN_PB10, 0);            /* TWD */
 696                 at91_set_multi_drive(AT91_PIN_PB10, 1);
 697
 698                 at91_set_A_periph(AT91_PIN_PB11, 0);            /* TWCK */
 699                 at91_set_multi_drive(AT91_PIN_PB11, 1);
 700
 701                 platform_device_register(&at91sam9g45_twi1_device);
 702         }
 703 }
 704 #else
 705 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
 706 #endif
 707
 708
 709 /* --------------------------------------------------------------------
 710  *  SPI
 711  * -------------------------------------------------------------------- */
 712
 713 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
 714 static u64 spi_dmamask = DMA_BIT_MASK(32);
 715
 716 static struct resource spi0_resources[] = {
 717         [0] = {
 718                 .start  = AT91SAM9G45_BASE_SPI0,
 719                 .end    = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
 720                 .flags  = IORESOURCE_MEM,
 721         },
 722         [1] = {
 723                 .start  = AT91SAM9G45_ID_SPI0,
 724                 .end    = AT91SAM9G45_ID_SPI0,
 725                 .flags  = IORESOURCE_IRQ,
 726         },
 727 };
 728
 729 static struct platform_device at91sam9g45_spi0_device = {
 730         .name           = "atmel_spi",
 731         .id             = 0,
 732         .dev            = {
 733                                 .dma_mask               = &spi_dmamask,
 734                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 735         },
 736         .resource       = spi0_resources,
 737         .num_resources  = ARRAY_SIZE(spi0_resources),
 738 };
 739
 740 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
 741
 742 static struct resource spi1_resources[] = {
 743         [0] = {
 744                 .start  = AT91SAM9G45_BASE_SPI1,
 745                 .end    = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
 746                 .flags  = IORESOURCE_MEM,
 747         },
 748         [1] = {
 749                 .start  = AT91SAM9G45_ID_SPI1,
 750                 .end    = AT91SAM9G45_ID_SPI1,
 751                 .flags  = IORESOURCE_IRQ,
 752         },
 753 };
 754
 755 static struct platform_device at91sam9g45_spi1_device = {
 756         .name           = "atmel_spi",
 757         .id             = 1,
 758         .dev            = {
 759                                 .dma_mask               = &spi_dmamask,
 760                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 761         },
 762         .resource       = spi1_resources,
 763         .num_resources  = ARRAY_SIZE(spi1_resources),
 764 };
 765
 766 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
 767
 768 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 769 {
 770         int i;
 771         unsigned long cs_pin;
 772         short enable_spi0 = 0;
 773         short enable_spi1 = 0;
 774
 775         /* Choose SPI chip-selects */
 776         for (i = 0; i < nr_devices; i++) {
 777                 if (devices[i].controller_data)
 778                         cs_pin = (unsigned long) devices[i].controller_data;
 779                 else if (devices[i].bus_num == 0)
 780                         cs_pin = spi0_standard_cs[devices[i].chip_select];
 781                 else
 782                         cs_pin = spi1_standard_cs[devices[i].chip_select];
 783
 784                 if (devices[i].bus_num == 0)
 785                         enable_spi0 = 1;
 786                 else
 787                         enable_spi1 = 1;
 788
 789                 /* enable chip-select pin */
 790                 at91_set_gpio_output(cs_pin, 1);
 791
 792                 /* pass chip-select pin to driver */
 793                 devices[i].controller_data = (void *) cs_pin;
 794         }
 795
 796         spi_register_board_info(devices, nr_devices);
 797
 798         /* Configure SPI bus(es) */
 799         if (enable_spi0) {
 800                 at91_set_A_periph(AT91_PIN_PB0, 0);     /* SPI0_MISO */
 801                 at91_set_A_periph(AT91_PIN_PB1, 0);     /* SPI0_MOSI */
 802                 at91_set_A_periph(AT91_PIN_PB2, 0);     /* SPI0_SPCK */
 803
 804                 at91_clock_associate("spi0_clk", &at91sam9g45_spi0_device.dev, "spi_clk");
 805                 platform_device_register(&at91sam9g45_spi0_device);
 806         }
 807         if (enable_spi1) {
 808                 at91_set_A_periph(AT91_PIN_PB14, 0);    /* SPI1_MISO */
 809                 at91_set_A_periph(AT91_PIN_PB15, 0);    /* SPI1_MOSI */
 810                 at91_set_A_periph(AT91_PIN_PB16, 0);    /* SPI1_SPCK */
 811
 812                 at91_clock_associate("spi1_clk", &at91sam9g45_spi1_device.dev, "spi_clk");
 813                 platform_device_register(&at91sam9g45_spi1_device);
 814         }
 815 }
 816 #else
 817 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
 818 #endif
 819
 820
 821 /* --------------------------------------------------------------------
 822  *  AC97
 823  * -------------------------------------------------------------------- */
 824
 825 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
 826 static u64 ac97_dmamask = DMA_BIT_MASK(32);
 827 static struct ac97c_platform_data ac97_data;
 828
 829 static struct resource ac97_resources[] = {
 830         [0] = {
 831                 .start  = AT91SAM9G45_BASE_AC97C,
 832                 .end    = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
 833                 .flags  = IORESOURCE_MEM,
 834         },
 835         [1] = {
 836                 .start  = AT91SAM9G45_ID_AC97C,
 837                 .end    = AT91SAM9G45_ID_AC97C,
 838                 .flags  = IORESOURCE_IRQ,
 839         },
 840 };
 841
 842 static struct platform_device at91sam9g45_ac97_device = {
 843         .name           = "atmel_ac97c",
 844         .id             = 0,
 845         .dev            = {
 846                                 .dma_mask               = &ac97_dmamask,
 847                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 848                                 .platform_data          = &ac97_data,
 849         },
 850         .resource       = ac97_resources,
 851         .num_resources  = ARRAY_SIZE(ac97_resources),
 852 };
 853
 854 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
 855 {
 856         if (!data)
 857                 return;
 858
 859         at91_set_A_periph(AT91_PIN_PD8, 0);     /* AC97FS */
 860         at91_set_A_periph(AT91_PIN_PD9, 0);     /* AC97CK */
 861         at91_set_A_periph(AT91_PIN_PD7, 0);     /* AC97TX */
 862         at91_set_A_periph(AT91_PIN_PD6, 0);     /* AC97RX */
 863
 864         /* reset */
 865         if (data->reset_pin)
 866                 at91_set_gpio_output(data->reset_pin, 0);
 867
 868         ac97_data = *data;
 869         platform_device_register(&at91sam9g45_ac97_device);
 870 }
 871 #else
 872 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
 873 #endif
 874
 875
 876 /* --------------------------------------------------------------------
 877  *  LCD Controller
 878  * -------------------------------------------------------------------- */
 879
 880 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
 881 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
 882 static struct atmel_lcdfb_info lcdc_data;
 883
 884 static struct resource lcdc_resources[] = {
 885         [0] = {
 886                 .start  = AT91SAM9G45_LCDC_BASE,
 887                 .end    = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
 888                 .flags  = IORESOURCE_MEM,
 889         },
 890         [1] = {
 891                 .start  = AT91SAM9G45_ID_LCDC,
 892                 .end    = AT91SAM9G45_ID_LCDC,
 893                 .flags  = IORESOURCE_IRQ,
 894         },
 895 };
 896
 897 static struct platform_device at91_lcdc_device = {
 898         .name           = "atmel_lcdfb",
 899         .id             = 0,
 900         .dev            = {
 901                                 .dma_mask               = &lcdc_dmamask,
 902                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 903                                 .platform_data          = &lcdc_data,
 904         },
 905         .resource       = lcdc_resources,
 906         .num_resources  = ARRAY_SIZE(lcdc_resources),
 907 };
 908
 909 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
 910 {
 911         if (!data)
 912                 return;
 913
 914         at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
 915
 916         at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
 917         at91_set_A_periph(AT91_PIN_PE3, 0);     /* LCDVSYNC */
 918         at91_set_A_periph(AT91_PIN_PE4, 0);     /* LCDHSYNC */
 919         at91_set_A_periph(AT91_PIN_PE5, 0);     /* LCDDOTCK */
 920         at91_set_A_periph(AT91_PIN_PE6, 0);     /* LCDDEN */
 921         at91_set_A_periph(AT91_PIN_PE7, 0);     /* LCDD0 */
 922         at91_set_A_periph(AT91_PIN_PE8, 0);     /* LCDD1 */
 923         at91_set_A_periph(AT91_PIN_PE9, 0);     /* LCDD2 */
 924         at91_set_A_periph(AT91_PIN_PE10, 0);    /* LCDD3 */
 925         at91_set_A_periph(AT91_PIN_PE11, 0);    /* LCDD4 */
 926         at91_set_A_periph(AT91_PIN_PE12, 0);    /* LCDD5 */
 927         at91_set_A_periph(AT91_PIN_PE13, 0);    /* LCDD6 */
 928         at91_set_A_periph(AT91_PIN_PE14, 0);    /* LCDD7 */
 929         at91_set_A_periph(AT91_PIN_PE15, 0);    /* LCDD8 */
 930         at91_set_A_periph(AT91_PIN_PE16, 0);    /* LCDD9 */
 931         at91_set_A_periph(AT91_PIN_PE17, 0);    /* LCDD10 */
 932         at91_set_A_periph(AT91_PIN_PE18, 0);    /* LCDD11 */
 933         at91_set_A_periph(AT91_PIN_PE19, 0);    /* LCDD12 */
 934         at91_set_A_periph(AT91_PIN_PE20, 0);    /* LCDD13 */
 935         at91_set_A_periph(AT91_PIN_PE21, 0);    /* LCDD14 */
 936         at91_set_A_periph(AT91_PIN_PE22, 0);    /* LCDD15 */
 937         at91_set_A_periph(AT91_PIN_PE23, 0);    /* LCDD16 */
 938         at91_set_A_periph(AT91_PIN_PE24, 0);    /* LCDD17 */
 939         at91_set_A_periph(AT91_PIN_PE25, 0);    /* LCDD18 */
 940         at91_set_A_periph(AT91_PIN_PE26, 0);    /* LCDD19 */
 941         at91_set_A_periph(AT91_PIN_PE27, 0);    /* LCDD20 */
 942         at91_set_A_periph(AT91_PIN_PE28, 0);    /* LCDD21 */
 943         at91_set_A_periph(AT91_PIN_PE29, 0);    /* LCDD22 */
 944         at91_set_A_periph(AT91_PIN_PE30, 0);    /* LCDD23 */
 945
 946         lcdc_data = *data;
 947         platform_device_register(&at91_lcdc_device);
 948 }
 949 #else
 950 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
 951 #endif
 952
 953
 954 /* --------------------------------------------------------------------
 955  *  Timer/Counter block
 956  * -------------------------------------------------------------------- */
 957
 958 #ifdef CONFIG_ATMEL_TCLIB
 959 static struct resource tcb0_resources[] = {
 960         [0] = {
 961                 .start  = AT91SAM9G45_BASE_TCB0,
 962                 .end    = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
 963                 .flags  = IORESOURCE_MEM,
 964         },
 965         [1] = {
 966                 .start  = AT91SAM9G45_ID_TCB,
 967                 .end    = AT91SAM9G45_ID_TCB,
 968                 .flags  = IORESOURCE_IRQ,
 969         },
 970 };
 971
 972 static struct platform_device at91sam9g45_tcb0_device = {
 973         .name           = "atmel_tcb",
 974         .id             = 0,
 975         .resource       = tcb0_resources,
 976         .num_resources  = ARRAY_SIZE(tcb0_resources),
 977 };
 978
 979 /* TCB1 begins with TC3 */
 980 static struct resource tcb1_resources[] = {
 981         [0] = {
 982                 .start  = AT91SAM9G45_BASE_TCB1,
 983                 .end    = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
 984                 .flags  = IORESOURCE_MEM,
 985         },
 986         [1] = {
 987                 .start  = AT91SAM9G45_ID_TCB,
 988                 .end    = AT91SAM9G45_ID_TCB,
 989                 .flags  = IORESOURCE_IRQ,
 990         },
 991 };
 992
 993 static struct platform_device at91sam9g45_tcb1_device = {
 994         .name           = "atmel_tcb",
 995         .id             = 1,
 996         .resource       = tcb1_resources,
 997         .num_resources  = ARRAY_SIZE(tcb1_resources),
 998 };
 999
1000 static void __init at91_add_device_tc(void)
1001 {
1002         /* this chip has one clock and irq for all six TC channels */
1003         at91_clock_associate("tcb0_clk", &at91sam9g45_tcb0_device.dev, "t0_clk");
1004         platform_device_register(&at91sam9g45_tcb0_device);
1005         at91_clock_associate("tcb1_clk", &at91sam9g45_tcb1_device.dev, "t0_clk");
1006         platform_device_register(&at91sam9g45_tcb1_device);
1007 }
1008 #else
1009 static void __init at91_add_device_tc(void) { }
1010 #endif
1011
1012
1013 /* --------------------------------------------------------------------
1014  *  RTC
1015  * -------------------------------------------------------------------- */
1016
1017 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
1018 static struct platform_device at91sam9g45_rtc_device = {
1019         .name           = "at91_rtc",
1020         .id             = -1,
1021         .num_resources  = 0,
1022 };
1023
1024 static void __init at91_add_device_rtc(void)
1025 {
1026         platform_device_register(&at91sam9g45_rtc_device);
1027 }
1028 #else
1029 static void __init at91_add_device_rtc(void) {}
1030 #endif
1031
1032
1033 /* --------------------------------------------------------------------
1034  *  Touchscreen
1035  * -------------------------------------------------------------------- */
1036
1037 #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
1038 static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
1039 static struct at91_tsadcc_data tsadcc_data;
1040
1041 static struct resource tsadcc_resources[] = {
1042         [0] = {
1043                 .start  = AT91SAM9G45_BASE_TSC,
1044                 .end    = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1045                 .flags  = IORESOURCE_MEM,
1046         },
1047         [1] = {
1048                 .start  = AT91SAM9G45_ID_TSC,
1049                 .end    = AT91SAM9G45_ID_TSC,
1050                 .flags  = IORESOURCE_IRQ,
1051         }
1052 };
1053
1054 static struct platform_device at91sam9g45_tsadcc_device = {
1055         .name           = "atmel_tsadcc",
1056         .id             = -1,
1057         .dev            = {
1058                                 .dma_mask               = &tsadcc_dmamask,
1059                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1060                                 .platform_data          = &tsadcc_data,
1061         },
1062         .resource       = tsadcc_resources,
1063         .num_resources  = ARRAY_SIZE(tsadcc_resources),
1064 };
1065
1066 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
1067 {
1068         if (!data)
1069                 return;
1070
1071         at91_set_gpio_input(AT91_PIN_PD20, 0);  /* AD0_XR */
1072         at91_set_gpio_input(AT91_PIN_PD21, 0);  /* AD1_XL */
1073         at91_set_gpio_input(AT91_PIN_PD22, 0);  /* AD2_YT */
1074         at91_set_gpio_input(AT91_PIN_PD23, 0);  /* AD3_TB */
1075
1076         tsadcc_data = *data;
1077         platform_device_register(&at91sam9g45_tsadcc_device);
1078 }
1079 #else
1080 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
1081 #endif
1082
1083
1084 /* --------------------------------------------------------------------
1085  *  RTT
1086  * -------------------------------------------------------------------- */
1087
1088 static struct resource rtt_resources[] = {
1089         {
1090                 .start  = AT91_BASE_SYS + AT91_RTT,
1091                 .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
1092                 .flags  = IORESOURCE_MEM,
1093         }
1094 };
1095
1096 static struct platform_device at91sam9g45_rtt_device = {
1097         .name           = "at91_rtt",
1098         .id             = 0,
1099         .resource       = rtt_resources,
1100         .num_resources  = ARRAY_SIZE(rtt_resources),
1101 };
1102
1103 static void __init at91_add_device_rtt(void)
1104 {
1105         platform_device_register(&at91sam9g45_rtt_device);
1106 }
1107
1108
1109 /* --------------------------------------------------------------------
1110  *  Watchdog
1111  * -------------------------------------------------------------------- */
1112
1113 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1114 static struct platform_device at91sam9g45_wdt_device = {
1115         .name           = "at91_wdt",
1116         .id             = -1,
1117         .num_resources  = 0,
1118 };
1119
1120 static void __init at91_add_device_watchdog(void)
1121 {
1122         platform_device_register(&at91sam9g45_wdt_device);
1123 }
1124 #else
1125 static void __init at91_add_device_watchdog(void) {}
1126 #endif
1127
1128
1129 /* --------------------------------------------------------------------
1130  *  PWM
1131  * --------------------------------------------------------------------*/
1132
1133 #if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
1134 static u32 pwm_mask;
1135
1136 static struct resource pwm_resources[] = {
1137         [0] = {
1138                 .start  = AT91SAM9G45_BASE_PWMC,
1139                 .end    = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
1140                 .flags  = IORESOURCE_MEM,
1141         },
1142         [1] = {
1143                 .start  = AT91SAM9G45_ID_PWMC,
1144                 .end    = AT91SAM9G45_ID_PWMC,
1145                 .flags  = IORESOURCE_IRQ,
1146         },
1147 };
1148
1149 static struct platform_device at91sam9g45_pwm0_device = {
1150         .name   = "atmel_pwm",
1151         .id     = -1,
1152         .dev    = {
1153                 .platform_data          = &pwm_mask,
1154         },
1155         .resource       = pwm_resources,
1156         .num_resources  = ARRAY_SIZE(pwm_resources),
1157 };
1158
1159 void __init at91_add_device_pwm(u32 mask)
1160 {
1161         if (mask & (1 << AT91_PWM0))
1162                 at91_set_B_periph(AT91_PIN_PD24, 1);    /* enable PWM0 */
1163
1164         if (mask & (1 << AT91_PWM1))
1165                 at91_set_B_periph(AT91_PIN_PD31, 1);    /* enable PWM1 */
1166
1167         if (mask & (1 << AT91_PWM2))
1168                 at91_set_B_periph(AT91_PIN_PD26, 1);    /* enable PWM2 */
1169
1170         if (mask & (1 << AT91_PWM3))
1171                 at91_set_B_periph(AT91_PIN_PD0, 1);     /* enable PWM3 */
1172
1173         pwm_mask = mask;
1174
1175         platform_device_register(&at91sam9g45_pwm0_device);
1176 }
1177 #else
1178 void __init at91_add_device_pwm(u32 mask) {}
1179 #endif
1180
1181
1182 /* --------------------------------------------------------------------
1183  *  SSC -- Synchronous Serial Controller
1184  * -------------------------------------------------------------------- */
1185
1186 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1187 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1188
1189 static struct resource ssc0_resources[] = {
1190         [0] = {
1191                 .start  = AT91SAM9G45_BASE_SSC0,
1192                 .end    = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
1193                 .flags  = IORESOURCE_MEM,
1194         },
1195         [1] = {
1196                 .start  = AT91SAM9G45_ID_SSC0,
1197                 .end    = AT91SAM9G45_ID_SSC0,
1198                 .flags  = IORESOURCE_IRQ,
1199         },
1200 };
1201
1202 static struct platform_device at91sam9g45_ssc0_device = {
1203         .name   = "ssc",
1204         .id     = 0,
1205         .dev    = {
1206                 .dma_mask               = &ssc0_dmamask,
1207                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1208         },
1209         .resource       = ssc0_resources,
1210         .num_resources  = ARRAY_SIZE(ssc0_resources),
1211 };
1212
1213 static inline void configure_ssc0_pins(unsigned pins)
1214 {
1215         if (pins & ATMEL_SSC_TF)
1216                 at91_set_A_periph(AT91_PIN_PD1, 1);
1217         if (pins & ATMEL_SSC_TK)
1218                 at91_set_A_periph(AT91_PIN_PD0, 1);
1219         if (pins & ATMEL_SSC_TD)
1220                 at91_set_A_periph(AT91_PIN_PD2, 1);
1221         if (pins & ATMEL_SSC_RD)
1222                 at91_set_A_periph(AT91_PIN_PD3, 1);
1223         if (pins & ATMEL_SSC_RK)
1224                 at91_set_A_periph(AT91_PIN_PD4, 1);
1225         if (pins & ATMEL_SSC_RF)
1226                 at91_set_A_periph(AT91_PIN_PD5, 1);
1227 }
1228
1229 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1230
1231 static struct resource ssc1_resources[] = {
1232         [0] = {
1233                 .start  = AT91SAM9G45_BASE_SSC1,
1234                 .end    = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
1235                 .flags  = IORESOURCE_MEM,
1236         },
1237         [1] = {
1238                 .start  = AT91SAM9G45_ID_SSC1,
1239                 .end    = AT91SAM9G45_ID_SSC1,
1240                 .flags  = IORESOURCE_IRQ,
1241         },
1242 };
1243
1244 static struct platform_device at91sam9g45_ssc1_device = {
1245         .name   = "ssc",
1246         .id     = 1,
1247         .dev    = {
1248                 .dma_mask               = &ssc1_dmamask,
1249                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1250         },
1251         .resource       = ssc1_resources,
1252         .num_resources  = ARRAY_SIZE(ssc1_resources),
1253 };
1254
1255 static inline void configure_ssc1_pins(unsigned pins)
1256 {
1257         if (pins & ATMEL_SSC_TF)
1258                 at91_set_A_periph(AT91_PIN_PD14, 1);
1259         if (pins & ATMEL_SSC_TK)
1260                 at91_set_A_periph(AT91_PIN_PD12, 1);
1261         if (pins & ATMEL_SSC_TD)
1262                 at91_set_A_periph(AT91_PIN_PD10, 1);
1263         if (pins & ATMEL_SSC_RD)
1264                 at91_set_A_periph(AT91_PIN_PD11, 1);
1265         if (pins & ATMEL_SSC_RK)
1266                 at91_set_A_periph(AT91_PIN_PD13, 1);
1267         if (pins & ATMEL_SSC_RF)
1268                 at91_set_A_periph(AT91_PIN_PD15, 1);
1269 }
1270
1271 /*
1272  * SSC controllers are accessed through library code, instead of any
1273  * kind of all-singing/all-dancing driver.  For example one could be
1274  * used by a particular I2S audio codec's driver, while another one
1275  * on the same system might be used by a custom data capture driver.
1276  */
1277 void __init at91_add_device_ssc(unsigned id, unsigned pins)
1278 {
1279         struct platform_device *pdev;
1280
1281         /*
1282          * NOTE: caller is responsible for passing information matching
1283          * "pins" to whatever will be using each particular controller.
1284          */
1285         switch (id) {
1286         case AT91SAM9G45_ID_SSC0:
1287                 pdev = &at91sam9g45_ssc0_device;
1288                 configure_ssc0_pins(pins);
1289                 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
1290                 break;
1291         case AT91SAM9G45_ID_SSC1:
1292                 pdev = &at91sam9g45_ssc1_device;
1293                 configure_ssc1_pins(pins);
1294                 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
1295                 break;
1296         default:
1297                 return;
1298         }
1299
1300         platform_device_register(pdev);
1301 }
1302
1303 #else
1304 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1305 #endif
1306
1307
1308 /* --------------------------------------------------------------------
1309  *  UART
1310  * -------------------------------------------------------------------- */
1311
1312 #if defined(CONFIG_SERIAL_ATMEL)
1313 static struct resource dbgu_resources[] = {
1314         [0] = {
1315                 .start  = AT91_VA_BASE_SYS + AT91_DBGU,
1316                 .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
1317                 .flags  = IORESOURCE_MEM,
1318         },
1319         [1] = {
1320                 .start  = AT91_ID_SYS,
1321                 .end    = AT91_ID_SYS,
1322                 .flags  = IORESOURCE_IRQ,
1323         },
1324 };
1325
1326 static struct atmel_uart_data dbgu_data = {
1327         .use_dma_tx     = 0,
1328         .use_dma_rx     = 0,
1329         .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
1330 };
1331
1332 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1333
1334 static struct platform_device at91sam9g45_dbgu_device = {
1335         .name           = "atmel_usart",
1336         .id             = 0,
1337         .dev            = {
1338                                 .dma_mask               = &dbgu_dmamask,
1339                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1340                                 .platform_data          = &dbgu_data,
1341         },
1342         .resource       = dbgu_resources,
1343         .num_resources  = ARRAY_SIZE(dbgu_resources),
1344 };
1345
1346 static inline void configure_dbgu_pins(void)
1347 {
1348         at91_set_A_periph(AT91_PIN_PB12, 0);            /* DRXD */
1349         at91_set_A_periph(AT91_PIN_PB13, 1);            /* DTXD */
1350 }
1351
1352 static struct resource uart0_resources[] = {
1353         [0] = {
1354                 .start  = AT91SAM9G45_BASE_US0,
1355                 .end    = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1356                 .flags  = IORESOURCE_MEM,
1357         },
1358         [1] = {
1359                 .start  = AT91SAM9G45_ID_US0,
1360                 .end    = AT91SAM9G45_ID_US0,
1361                 .flags  = IORESOURCE_IRQ,
1362         },
1363 };
1364
1365 static struct atmel_uart_data uart0_data = {
1366         .use_dma_tx     = 1,
1367         .use_dma_rx     = 1,
1368 };
1369
1370 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1371
1372 static struct platform_device at91sam9g45_uart0_device = {
1373         .name           = "atmel_usart",
1374         .id             = 1,
1375         .dev            = {
1376                                 .dma_mask               = &uart0_dmamask,
1377                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1378                                 .platform_data          = &uart0_data,
1379         },
1380         .resource       = uart0_resources,
1381         .num_resources  = ARRAY_SIZE(uart0_resources),
1382 };
1383
1384 static inline void configure_usart0_pins(unsigned pins)
1385 {
1386         at91_set_A_periph(AT91_PIN_PB19, 1);            /* TXD0 */
1387         at91_set_A_periph(AT91_PIN_PB18, 0);            /* RXD0 */
1388
1389         if (pins & ATMEL_UART_RTS)
1390                 at91_set_B_periph(AT91_PIN_PB17, 0);    /* RTS0 */
1391         if (pins & ATMEL_UART_CTS)
1392                 at91_set_B_periph(AT91_PIN_PB15, 0);    /* CTS0 */
1393 }
1394
1395 static struct resource uart1_resources[] = {
1396         [0] = {
1397                 .start  = AT91SAM9G45_BASE_US1,
1398                 .end    = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1399                 .flags  = IORESOURCE_MEM,
1400         },
1401         [1] = {
1402                 .start  = AT91SAM9G45_ID_US1,
1403                 .end    = AT91SAM9G45_ID_US1,
1404                 .flags  = IORESOURCE_IRQ,
1405         },
1406 };
1407
1408 static struct atmel_uart_data uart1_data = {
1409         .use_dma_tx     = 1,
1410         .use_dma_rx     = 1,
1411 };
1412
1413 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1414
1415 static struct platform_device at91sam9g45_uart1_device = {
1416         .name           = "atmel_usart",
1417         .id             = 2,
1418         .dev            = {
1419                                 .dma_mask               = &uart1_dmamask,
1420                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1421                                 .platform_data          = &uart1_data,
1422         },
1423         .resource       = uart1_resources,
1424         .num_resources  = ARRAY_SIZE(uart1_resources),
1425 };
1426
1427 static inline void configure_usart1_pins(unsigned pins)
1428 {
1429         at91_set_A_periph(AT91_PIN_PB4, 1);             /* TXD1 */
1430         at91_set_A_periph(AT91_PIN_PB5, 0);             /* RXD1 */
1431
1432         if (pins & ATMEL_UART_RTS)
1433                 at91_set_A_periph(AT91_PIN_PD16, 0);    /* RTS1 */
1434         if (pins & ATMEL_UART_CTS)
1435                 at91_set_A_periph(AT91_PIN_PD17, 0);    /* CTS1 */
1436 }
1437
1438 static struct resource uart2_resources[] = {
1439         [0] = {
1440                 .start  = AT91SAM9G45_BASE_US2,
1441                 .end    = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1442                 .flags  = IORESOURCE_MEM,
1443         },
1444         [1] = {
1445                 .start  = AT91SAM9G45_ID_US2,
1446                 .end    = AT91SAM9G45_ID_US2,
1447                 .flags  = IORESOURCE_IRQ,
1448         },
1449 };
1450
1451 static struct atmel_uart_data uart2_data = {
1452         .use_dma_tx     = 1,
1453         .use_dma_rx     = 1,
1454 };
1455
1456 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1457
1458 static struct platform_device at91sam9g45_uart2_device = {
1459         .name           = "atmel_usart",
1460         .id             = 3,
1461         .dev            = {
1462                                 .dma_mask               = &uart2_dmamask,
1463                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1464                                 .platform_data          = &uart2_data,
1465         },
1466         .resource       = uart2_resources,
1467         .num_resources  = ARRAY_SIZE(uart2_resources),
1468 };
1469
1470 static inline void configure_usart2_pins(unsigned pins)
1471 {
1472         at91_set_A_periph(AT91_PIN_PB6, 1);             /* TXD2 */
1473         at91_set_A_periph(AT91_PIN_PB7, 0);             /* RXD2 */
1474
1475         if (pins & ATMEL_UART_RTS)
1476                 at91_set_B_periph(AT91_PIN_PC9, 0);     /* RTS2 */
1477         if (pins & ATMEL_UART_CTS)
1478                 at91_set_B_periph(AT91_PIN_PC11, 0);    /* CTS2 */
1479 }
1480
1481 static struct resource uart3_resources[] = {
1482         [0] = {
1483                 .start  = AT91SAM9G45_BASE_US3,
1484                 .end    = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1485                 .flags  = IORESOURCE_MEM,
1486         },
1487         [1] = {
1488                 .start  = AT91SAM9G45_ID_US3,
1489                 .end    = AT91SAM9G45_ID_US3,
1490                 .flags  = IORESOURCE_IRQ,
1491         },
1492 };
1493
1494 static struct atmel_uart_data uart3_data = {
1495         .use_dma_tx     = 1,
1496         .use_dma_rx     = 1,
1497 };
1498
1499 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1500
1501 static struct platform_device at91sam9g45_uart3_device = {
1502         .name           = "atmel_usart",
1503         .id             = 4,
1504         .dev            = {
1505                                 .dma_mask               = &uart3_dmamask,
1506                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1507                                 .platform_data          = &uart3_data,
1508         },
1509         .resource       = uart3_resources,
1510         .num_resources  = ARRAY_SIZE(uart3_resources),
1511 };
1512
1513 static inline void configure_usart3_pins(unsigned pins)
1514 {
1515         at91_set_A_periph(AT91_PIN_PB8, 1);             /* TXD3 */
1516         at91_set_A_periph(AT91_PIN_PB9, 0);             /* RXD3 */
1517
1518         if (pins & ATMEL_UART_RTS)
1519                 at91_set_B_periph(AT91_PIN_PA23, 0);    /* RTS3 */
1520         if (pins & ATMEL_UART_CTS)
1521                 at91_set_B_periph(AT91_PIN_PA24, 0);    /* CTS3 */
1522 }
1523
1524 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
1525 struct platform_device *atmel_default_console_device;   /* the serial console device */
1526
1527 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1528 {
1529         struct platform_device *pdev;
1530
1531         switch (id) {
1532                 case 0:         /* DBGU */
1533                         pdev = &at91sam9g45_dbgu_device;
1534                         configure_dbgu_pins();
1535                         at91_clock_associate("mck", &pdev->dev, "usart");
1536                         break;
1537                 case AT91SAM9G45_ID_US0:
1538                         pdev = &at91sam9g45_uart0_device;
1539                         configure_usart0_pins(pins);
1540                         at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1541                         break;
1542                 case AT91SAM9G45_ID_US1:
1543                         pdev = &at91sam9g45_uart1_device;
1544                         configure_usart1_pins(pins);
1545                         at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1546                         break;
1547                 case AT91SAM9G45_ID_US2:
1548                         pdev = &at91sam9g45_uart2_device;
1549                         configure_usart2_pins(pins);
1550                         at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1551                         break;
1552                 case AT91SAM9G45_ID_US3:
1553                         pdev = &at91sam9g45_uart3_device;
1554                         configure_usart3_pins(pins);
1555                         at91_clock_associate("usart3_clk", &pdev->dev, "usart");
1556                         break;
1557                 default:
1558                         return;
1559         }
1560         pdev->id = portnr;              /* update to mapped ID */
1561
1562         if (portnr < ATMEL_MAX_UART)
1563                 at91_uarts[portnr] = pdev;
1564 }
1565
1566 void __init at91_set_serial_console(unsigned portnr)
1567 {
1568         if (portnr < ATMEL_MAX_UART)
1569                 atmel_default_console_device = at91_uarts[portnr];
1570 }
1571
1572 void __init at91_add_device_serial(void)
1573 {
1574         int i;
1575
1576         for (i = 0; i < ATMEL_MAX_UART; i++) {
1577                 if (at91_uarts[i])
1578                         platform_device_register(at91_uarts[i]);
1579         }
1580
1581         if (!atmel_default_console_device)
1582                 printk(KERN_INFO "AT91: No default serial console defined.\n");
1583 }
1584 #else
1585 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1586 void __init at91_set_serial_console(unsigned portnr) {}
1587 void __init at91_add_device_serial(void) {}
1588 #endif
1589
1590
1591 /* -------------------------------------------------------------------- */
1592 /*
1593  * These devices are always present and don't need any board-specific
1594  * setup.
1595  */
1596 static int __init at91_add_standard_devices(void)
1597 {
1598         at91_add_device_hdmac();
1599         at91_add_device_rtc();
1600         at91_add_device_rtt();
1601         at91_add_device_watchdog();
1602         at91_add_device_tc();
1603         return 0;
1604 }
1605
1606 arch_initcall(at91_add_standard_devices);