arch/arm/mach-at91/at91sam9263.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9263.c
   3  *
   4  *  Copyright (C) 2007 Atmel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/pm.h>
  15
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <mach/at91sam9263.h>
  20 #include <mach/at91_pmc.h>
  21 #include <mach/at91_rstc.h>
  22 #include <mach/at91_shdwc.h>
  23
  24 #include "soc.h"
  25 #include "generic.h"
  26 #include "clock.h"
  27
  28 static struct map_desc at91sam9263_sram_desc[] __initdata = {
  29         {
  30                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE,
  31                 .pfn            = __phys_to_pfn(AT91SAM9263_SRAM0_BASE),
  32                 .length         = AT91SAM9263_SRAM0_SIZE,
  33                 .type           = MT_DEVICE,
  34         }, {
  35                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE - AT91SAM9263_SRAM1_SIZE,
  36                 .pfn            = __phys_to_pfn(AT91SAM9263_SRAM1_BASE),
  37                 .length         = AT91SAM9263_SRAM1_SIZE,
  38                 .type           = MT_DEVICE,
  39         },
  40 };
  41
  42 /* --------------------------------------------------------------------
  43  *  Clocks
  44  * -------------------------------------------------------------------- */
  45
  46 /*
  47  * The peripheral clocks.
  48  */
  49 static struct clk pioA_clk = {
  50         .name           = "pioA_clk",
  51         .pmc_mask       = 1 << AT91SAM9263_ID_PIOA,
  52         .type           = CLK_TYPE_PERIPHERAL,
  53 };
  54 static struct clk pioB_clk = {
  55         .name           = "pioB_clk",
  56         .pmc_mask       = 1 << AT91SAM9263_ID_PIOB,
  57         .type           = CLK_TYPE_PERIPHERAL,
  58 };
  59 static struct clk pioCDE_clk = {
  60         .name           = "pioCDE_clk",
  61         .pmc_mask       = 1 << AT91SAM9263_ID_PIOCDE,
  62         .type           = CLK_TYPE_PERIPHERAL,
  63 };
  64 static struct clk usart0_clk = {
  65         .name           = "usart0_clk",
  66         .pmc_mask       = 1 << AT91SAM9263_ID_US0,
  67         .type           = CLK_TYPE_PERIPHERAL,
  68 };
  69 static struct clk usart1_clk = {
  70         .name           = "usart1_clk",
  71         .pmc_mask       = 1 << AT91SAM9263_ID_US1,
  72         .type           = CLK_TYPE_PERIPHERAL,
  73 };
  74 static struct clk usart2_clk = {
  75         .name           = "usart2_clk",
  76         .pmc_mask       = 1 << AT91SAM9263_ID_US2,
  77         .type           = CLK_TYPE_PERIPHERAL,
  78 };
  79 static struct clk mmc0_clk = {
  80         .name           = "mci0_clk",
  81         .pmc_mask       = 1 << AT91SAM9263_ID_MCI0,
  82         .type           = CLK_TYPE_PERIPHERAL,
  83 };
  84 static struct clk mmc1_clk = {
  85         .name           = "mci1_clk",
  86         .pmc_mask       = 1 << AT91SAM9263_ID_MCI1,
  87         .type           = CLK_TYPE_PERIPHERAL,
  88 };
  89 static struct clk can_clk = {
  90         .name           = "can_clk",
  91         .pmc_mask       = 1 << AT91SAM9263_ID_CAN,
  92         .type           = CLK_TYPE_PERIPHERAL,
  93 };
  94 static struct clk twi_clk = {
  95         .name           = "twi_clk",
  96         .pmc_mask       = 1 << AT91SAM9263_ID_TWI,
  97         .type           = CLK_TYPE_PERIPHERAL,
  98 };
  99 static struct clk spi0_clk = {
 100         .name           = "spi0_clk",
 101         .pmc_mask       = 1 << AT91SAM9263_ID_SPI0,
 102         .type           = CLK_TYPE_PERIPHERAL,
 103 };
 104 static struct clk spi1_clk = {
 105         .name           = "spi1_clk",
 106         .pmc_mask       = 1 << AT91SAM9263_ID_SPI1,
 107         .type           = CLK_TYPE_PERIPHERAL,
 108 };
 109 static struct clk ssc0_clk = {
 110         .name           = "ssc0_clk",
 111         .pmc_mask       = 1 << AT91SAM9263_ID_SSC0,
 112         .type           = CLK_TYPE_PERIPHERAL,
 113 };
 114 static struct clk ssc1_clk = {
 115         .name           = "ssc1_clk",
 116         .pmc_mask       = 1 << AT91SAM9263_ID_SSC1,
 117         .type           = CLK_TYPE_PERIPHERAL,
 118 };
 119 static struct clk ac97_clk = {
 120         .name           = "ac97_clk",
 121         .pmc_mask       = 1 << AT91SAM9263_ID_AC97C,
 122         .type           = CLK_TYPE_PERIPHERAL,
 123 };
 124 static struct clk tcb_clk = {
 125         .name           = "tcb_clk",
 126         .pmc_mask       = 1 << AT91SAM9263_ID_TCB,
 127         .type           = CLK_TYPE_PERIPHERAL,
 128 };
 129 static struct clk pwm_clk = {
 130         .name           = "pwm_clk",
 131         .pmc_mask       = 1 << AT91SAM9263_ID_PWMC,
 132         .type           = CLK_TYPE_PERIPHERAL,
 133 };
 134 static struct clk macb_clk = {
 135         .name           = "macb_clk",
 136         .pmc_mask       = 1 << AT91SAM9263_ID_EMAC,
 137         .type           = CLK_TYPE_PERIPHERAL,
 138 };
 139 static struct clk dma_clk = {
 140         .name           = "dma_clk",
 141         .pmc_mask       = 1 << AT91SAM9263_ID_DMA,
 142         .type           = CLK_TYPE_PERIPHERAL,
 143 };
 144 static struct clk twodge_clk = {
 145         .name           = "2dge_clk",
 146         .pmc_mask       = 1 << AT91SAM9263_ID_2DGE,
 147         .type           = CLK_TYPE_PERIPHERAL,
 148 };
 149 static struct clk udc_clk = {
 150         .name           = "udc_clk",
 151         .pmc_mask       = 1 << AT91SAM9263_ID_UDP,
 152         .type           = CLK_TYPE_PERIPHERAL,
 153 };
 154 static struct clk isi_clk = {
 155         .name           = "isi_clk",
 156         .pmc_mask       = 1 << AT91SAM9263_ID_ISI,
 157         .type           = CLK_TYPE_PERIPHERAL,
 158 };
 159 static struct clk lcdc_clk = {
 160         .name           = "lcdc_clk",
 161         .pmc_mask       = 1 << AT91SAM9263_ID_LCDC,
 162         .type           = CLK_TYPE_PERIPHERAL,
 163 };
 164 static struct clk ohci_clk = {
 165         .name           = "ohci_clk",
 166         .pmc_mask       = 1 << AT91SAM9263_ID_UHP,
 167         .type           = CLK_TYPE_PERIPHERAL,
 168 };
 169
 170 static struct clk *periph_clocks[] __initdata = {
 171         &pioA_clk,
 172         &pioB_clk,
 173         &pioCDE_clk,
 174         &usart0_clk,
 175         &usart1_clk,
 176         &usart2_clk,
 177         &mmc0_clk,
 178         &mmc1_clk,
 179         &can_clk,
 180         &twi_clk,
 181         &spi0_clk,
 182         &spi1_clk,
 183         &ssc0_clk,
 184         &ssc1_clk,
 185         &ac97_clk,
 186         &tcb_clk,
 187         &pwm_clk,
 188         &macb_clk,
 189         &twodge_clk,
 190         &udc_clk,
 191         &isi_clk,
 192         &lcdc_clk,
 193         &dma_clk,
 194         &ohci_clk,
 195         // irq0 .. irq1
 196 };
 197
 198 static struct clk_lookup periph_clocks_lookups[] = {
 199         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 200         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 201         CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
 202         CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
 203         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 204         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 205         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
 206 };
 207
 208 static struct clk_lookup usart_clocks_lookups[] = {
 209         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 210         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 211         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 212         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 213 };
 214
 215 /*
 216  * The four programmable clocks.
 217  * You must configure pin multiplexing to bring these signals out.
 218  */
 219 static struct clk pck0 = {
 220         .name           = "pck0",
 221         .pmc_mask       = AT91_PMC_PCK0,
 222         .type           = CLK_TYPE_PROGRAMMABLE,
 223         .id             = 0,
 224 };
 225 static struct clk pck1 = {
 226         .name           = "pck1",
 227         .pmc_mask       = AT91_PMC_PCK1,
 228         .type           = CLK_TYPE_PROGRAMMABLE,
 229         .id             = 1,
 230 };
 231 static struct clk pck2 = {
 232         .name           = "pck2",
 233         .pmc_mask       = AT91_PMC_PCK2,
 234         .type           = CLK_TYPE_PROGRAMMABLE,
 235         .id             = 2,
 236 };
 237 static struct clk pck3 = {
 238         .name           = "pck3",
 239         .pmc_mask       = AT91_PMC_PCK3,
 240         .type           = CLK_TYPE_PROGRAMMABLE,
 241         .id             = 3,
 242 };
 243
 244 static void __init at91sam9263_register_clocks(void)
 245 {
 246         int i;
 247
 248         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 249                 clk_register(periph_clocks[i]);
 250
 251         clkdev_add_table(periph_clocks_lookups,
 252                          ARRAY_SIZE(periph_clocks_lookups));
 253         clkdev_add_table(usart_clocks_lookups,
 254                          ARRAY_SIZE(usart_clocks_lookups));
 255
 256         clk_register(&pck0);
 257         clk_register(&pck1);
 258         clk_register(&pck2);
 259         clk_register(&pck3);
 260 }
 261
 262 static struct clk_lookup console_clock_lookup;
 263
 264 void __init at91sam9263_set_console_clock(int id)
 265 {
 266         if (id >= ARRAY_SIZE(usart_clocks_lookups))
 267                 return;
 268
 269         console_clock_lookup.con_id = "usart";
 270         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
 271         clkdev_add(&console_clock_lookup);
 272 }
 273
 274 /* --------------------------------------------------------------------
 275  *  GPIO
 276  * -------------------------------------------------------------------- */
 277
 278 static struct at91_gpio_bank at91sam9263_gpio[] = {
 279         {
 280                 .id             = AT91SAM9263_ID_PIOA,
 281                 .offset         = AT91_PIOA,
 282                 .clock          = &pioA_clk,
 283         }, {
 284                 .id             = AT91SAM9263_ID_PIOB,
 285                 .offset         = AT91_PIOB,
 286                 .clock          = &pioB_clk,
 287         }, {
 288                 .id             = AT91SAM9263_ID_PIOCDE,
 289                 .offset         = AT91_PIOC,
 290                 .clock          = &pioCDE_clk,
 291         }, {
 292                 .id             = AT91SAM9263_ID_PIOCDE,
 293                 .offset         = AT91_PIOD,
 294                 .clock          = &pioCDE_clk,
 295         }, {
 296                 .id             = AT91SAM9263_ID_PIOCDE,
 297                 .offset         = AT91_PIOE,
 298                 .clock          = &pioCDE_clk,
 299         }
 300 };
 301
 302 static void at91sam9263_poweroff(void)
 303 {
 304         at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
 305 }
 306
 307
 308 /* --------------------------------------------------------------------
 309  *  AT91SAM9263 processor initialization
 310  * -------------------------------------------------------------------- */
 311
 312 static void __init at91sam9263_map_io(void)
 313 {
 314         iotable_init(at91sam9263_sram_desc, ARRAY_SIZE(at91sam9263_sram_desc));
 315 }
 316
 317 static void __init at91sam9263_initialize(void)
 318 {
 319         at91_arch_reset = at91sam9_alt_reset;
 320         pm_power_off = at91sam9263_poweroff;
 321         at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
 322
 323         /* Register the processor-specific clocks */
 324         at91sam9263_register_clocks();
 325
 326         /* Register GPIO subsystem */
 327         at91_gpio_init(at91sam9263_gpio, 5);
 328 }
 329
 330 /* --------------------------------------------------------------------
 331  *  Interrupt initialization
 332  * -------------------------------------------------------------------- */
 333
 334 /*
 335  * The default interrupt priority levels (0 = lowest, 7 = highest).
 336  */
 337 static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
 338         7,      /* Advanced Interrupt Controller (FIQ) */
 339         7,      /* System Peripherals */
 340         1,      /* Parallel IO Controller A */
 341         1,      /* Parallel IO Controller B */
 342         1,      /* Parallel IO Controller C, D and E */
 343         0,
 344         0,
 345         5,      /* USART 0 */
 346         5,      /* USART 1 */
 347         5,      /* USART 2 */
 348         0,      /* Multimedia Card Interface 0 */
 349         0,      /* Multimedia Card Interface 1 */
 350         3,      /* CAN */
 351         6,      /* Two-Wire Interface */
 352         5,      /* Serial Peripheral Interface 0 */
 353         5,      /* Serial Peripheral Interface 1 */
 354         4,      /* Serial Synchronous Controller 0 */
 355         4,      /* Serial Synchronous Controller 1 */
 356         5,      /* AC97 Controller */
 357         0,      /* Timer Counter 0, 1 and 2 */
 358         0,      /* Pulse Width Modulation Controller */
 359         3,      /* Ethernet */
 360         0,
 361         0,      /* 2D Graphic Engine */
 362         2,      /* USB Device Port */
 363         0,      /* Image Sensor Interface */
 364         3,      /* LDC Controller */
 365         0,      /* DMA Controller */
 366         0,
 367         2,      /* USB Host port */
 368         0,      /* Advanced Interrupt Controller (IRQ0) */
 369         0,      /* Advanced Interrupt Controller (IRQ1) */
 370 };
 371
 372 struct at91_init_soc __initdata at91sam9263_soc = {
 373         .map_io = at91sam9263_map_io,
 374         .default_irq_priority = at91sam9263_default_irq_priority,
 375         .init = at91sam9263_initialize,
 376 };