2 * arch/arm/mach-at91/at91sam9260.c
4 * Copyright (C) 2006 SAN People
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
20 #include <mach/at91_dbgu.h>
21 #include <mach/at91sam9260.h>
22 #include <mach/at91_pmc.h>
23 #include <mach/at91_rstc.h>
24 #include <mach/at91_shdwc.h>
30 static struct map_desc at91sam9260_sram_desc[] __initdata = {
32 .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
33 .pfn = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
34 .length = AT91SAM9260_SRAM0_SIZE,
37 .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE,
38 .pfn = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
39 .length = AT91SAM9260_SRAM1_SIZE,
44 static struct map_desc at91sam9g20_sram_desc[] __initdata = {
46 .virtual = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE,
47 .pfn = __phys_to_pfn(AT91SAM9G20_SRAM0_BASE),
48 .length = AT91SAM9G20_SRAM0_SIZE,
51 .virtual = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE - AT91SAM9G20_SRAM1_SIZE,
52 .pfn = __phys_to_pfn(AT91SAM9G20_SRAM1_BASE),
53 .length = AT91SAM9G20_SRAM1_SIZE,
58 static struct map_desc at91sam9xe_sram_desc[] __initdata = {
60 .pfn = __phys_to_pfn(AT91SAM9XE_SRAM_BASE),
65 /* --------------------------------------------------------------------
67 * -------------------------------------------------------------------- */
70 * The peripheral clocks.
72 static struct clk pioA_clk = {
74 .pmc_mask = 1 << AT91SAM9260_ID_PIOA,
75 .type = CLK_TYPE_PERIPHERAL,
77 static struct clk pioB_clk = {
79 .pmc_mask = 1 << AT91SAM9260_ID_PIOB,
80 .type = CLK_TYPE_PERIPHERAL,
82 static struct clk pioC_clk = {
84 .pmc_mask = 1 << AT91SAM9260_ID_PIOC,
85 .type = CLK_TYPE_PERIPHERAL,
87 static struct clk adc_clk = {
89 .pmc_mask = 1 << AT91SAM9260_ID_ADC,
90 .type = CLK_TYPE_PERIPHERAL,
92 static struct clk usart0_clk = {
94 .pmc_mask = 1 << AT91SAM9260_ID_US0,
95 .type = CLK_TYPE_PERIPHERAL,
97 static struct clk usart1_clk = {
99 .pmc_mask = 1 << AT91SAM9260_ID_US1,
100 .type = CLK_TYPE_PERIPHERAL,
102 static struct clk usart2_clk = {
103 .name = "usart2_clk",
104 .pmc_mask = 1 << AT91SAM9260_ID_US2,
105 .type = CLK_TYPE_PERIPHERAL,
107 static struct clk mmc_clk = {
109 .pmc_mask = 1 << AT91SAM9260_ID_MCI,
110 .type = CLK_TYPE_PERIPHERAL,
112 static struct clk udc_clk = {
114 .pmc_mask = 1 << AT91SAM9260_ID_UDP,
115 .type = CLK_TYPE_PERIPHERAL,
117 static struct clk twi_clk = {
119 .pmc_mask = 1 << AT91SAM9260_ID_TWI,
120 .type = CLK_TYPE_PERIPHERAL,
122 static struct clk spi0_clk = {
124 .pmc_mask = 1 << AT91SAM9260_ID_SPI0,
125 .type = CLK_TYPE_PERIPHERAL,
127 static struct clk spi1_clk = {
129 .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
130 .type = CLK_TYPE_PERIPHERAL,
132 static struct clk ssc_clk = {
134 .pmc_mask = 1 << AT91SAM9260_ID_SSC,
135 .type = CLK_TYPE_PERIPHERAL,
137 static struct clk tc0_clk = {
139 .pmc_mask = 1 << AT91SAM9260_ID_TC0,
140 .type = CLK_TYPE_PERIPHERAL,
142 static struct clk tc1_clk = {
144 .pmc_mask = 1 << AT91SAM9260_ID_TC1,
145 .type = CLK_TYPE_PERIPHERAL,
147 static struct clk tc2_clk = {
149 .pmc_mask = 1 << AT91SAM9260_ID_TC2,
150 .type = CLK_TYPE_PERIPHERAL,
152 static struct clk ohci_clk = {
154 .pmc_mask = 1 << AT91SAM9260_ID_UHP,
155 .type = CLK_TYPE_PERIPHERAL,
157 static struct clk macb_clk = {
159 .pmc_mask = 1 << AT91SAM9260_ID_EMAC,
160 .type = CLK_TYPE_PERIPHERAL,
162 static struct clk isi_clk = {
164 .pmc_mask = 1 << AT91SAM9260_ID_ISI,
165 .type = CLK_TYPE_PERIPHERAL,
167 static struct clk usart3_clk = {
168 .name = "usart3_clk",
169 .pmc_mask = 1 << AT91SAM9260_ID_US3,
170 .type = CLK_TYPE_PERIPHERAL,
172 static struct clk usart4_clk = {
173 .name = "usart4_clk",
174 .pmc_mask = 1 << AT91SAM9260_ID_US4,
175 .type = CLK_TYPE_PERIPHERAL,
177 static struct clk usart5_clk = {
178 .name = "usart5_clk",
179 .pmc_mask = 1 << AT91SAM9260_ID_US5,
180 .type = CLK_TYPE_PERIPHERAL,
182 static struct clk tc3_clk = {
184 .pmc_mask = 1 << AT91SAM9260_ID_TC3,
185 .type = CLK_TYPE_PERIPHERAL,
187 static struct clk tc4_clk = {
189 .pmc_mask = 1 << AT91SAM9260_ID_TC4,
190 .type = CLK_TYPE_PERIPHERAL,
192 static struct clk tc5_clk = {
194 .pmc_mask = 1 << AT91SAM9260_ID_TC5,
195 .type = CLK_TYPE_PERIPHERAL,
198 static struct clk *periph_clocks[] __initdata = {
227 static struct clk_lookup periph_clocks_lookups[] = {
228 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
229 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
230 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
231 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
232 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
233 CLKDEV_CON_DEV_ID("t3_clk", "atmel_tcb.1", &tc3_clk),
234 CLKDEV_CON_DEV_ID("t4_clk", "atmel_tcb.1", &tc4_clk),
235 CLKDEV_CON_DEV_ID("t5_clk", "atmel_tcb.1", &tc5_clk),
236 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
239 static struct clk_lookup usart_clocks_lookups[] = {
240 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
241 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
242 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
243 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
244 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
245 CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
246 CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
250 * The two programmable clocks.
251 * You must configure pin multiplexing to bring these signals out.
253 static struct clk pck0 = {
255 .pmc_mask = AT91_PMC_PCK0,
256 .type = CLK_TYPE_PROGRAMMABLE,
259 static struct clk pck1 = {
261 .pmc_mask = AT91_PMC_PCK1,
262 .type = CLK_TYPE_PROGRAMMABLE,
266 static void __init at91sam9260_register_clocks(void)
270 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
271 clk_register(periph_clocks[i]);
273 clkdev_add_table(periph_clocks_lookups,
274 ARRAY_SIZE(periph_clocks_lookups));
275 clkdev_add_table(usart_clocks_lookups,
276 ARRAY_SIZE(usart_clocks_lookups));
282 static struct clk_lookup console_clock_lookup;
284 void __init at91sam9260_set_console_clock(int id)
286 if (id >= ARRAY_SIZE(usart_clocks_lookups))
289 console_clock_lookup.con_id = "usart";
290 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
291 clkdev_add(&console_clock_lookup);
294 /* --------------------------------------------------------------------
296 * -------------------------------------------------------------------- */
298 static struct at91_gpio_bank at91sam9260_gpio[] = {
300 .id = AT91SAM9260_ID_PIOA,
304 .id = AT91SAM9260_ID_PIOB,
308 .id = AT91SAM9260_ID_PIOC,
314 static void at91sam9260_poweroff(void)
316 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
320 /* --------------------------------------------------------------------
321 * AT91SAM9260 processor initialization
322 * -------------------------------------------------------------------- */
324 static void __init at91sam9xe_map_io(void)
326 unsigned long sram_size;
328 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
329 case AT91_CIDR_SRAMSIZ_32K:
330 sram_size = 2 * SZ_16K;
332 case AT91_CIDR_SRAMSIZ_16K:
337 at91sam9xe_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
338 at91sam9xe_sram_desc->length = sram_size;
340 iotable_init(at91sam9xe_sram_desc, ARRAY_SIZE(at91sam9xe_sram_desc));
343 static void __init at91sam9260_map_io(void)
345 if (cpu_is_at91sam9xe())
347 else if (cpu_is_at91sam9g20())
348 iotable_init(at91sam9g20_sram_desc, ARRAY_SIZE(at91sam9g20_sram_desc));
350 iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
353 static void __init at91sam9260_initialize(unsigned long main_clock)
355 at91_arch_reset = at91sam9_alt_reset;
356 pm_power_off = at91sam9260_poweroff;
357 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
358 | (1 << AT91SAM9260_ID_IRQ2);
360 /* Init clock subsystem */
361 at91_clock_init(main_clock);
363 /* Register the processor-specific clocks */
364 at91sam9260_register_clocks();
366 /* Register GPIO subsystem */
367 at91_gpio_init(at91sam9260_gpio, 3);
370 /* --------------------------------------------------------------------
371 * Interrupt initialization
372 * -------------------------------------------------------------------- */
375 * The default interrupt priority levels (0 = lowest, 7 = highest).
377 static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
378 7, /* Advanced Interrupt Controller */
379 7, /* System Peripherals */
380 1, /* Parallel IO Controller A */
381 1, /* Parallel IO Controller B */
382 1, /* Parallel IO Controller C */
383 0, /* Analog-to-Digital Converter */
387 0, /* Multimedia Card Interface */
388 2, /* USB Device Port */
389 6, /* Two-Wire Interface */
390 5, /* Serial Peripheral Interface 0 */
391 5, /* Serial Peripheral Interface 1 */
392 5, /* Serial Synchronous Controller */
395 0, /* Timer Counter 0 */
396 0, /* Timer Counter 1 */
397 0, /* Timer Counter 2 */
398 2, /* USB Host port */
400 0, /* Image Sensor Interface */
404 0, /* Timer Counter 3 */
405 0, /* Timer Counter 4 */
406 0, /* Timer Counter 5 */
407 0, /* Advanced Interrupt Controller */
408 0, /* Advanced Interrupt Controller */
409 0, /* Advanced Interrupt Controller */
412 struct at91_init_soc __initdata at91sam9260_soc = {
413 .map_io = at91sam9260_map_io,
414 .default_irq_priority = at91sam9260_default_irq_priority,
415 .init = at91sam9260_initialize,