arch/arm/mach-at91/at91sam9260.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9260.c
   3  *
   4  *  Copyright (C) 2006 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/pm.h>
  15
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <mach/cpu.h>
  20 #include <mach/at91_dbgu.h>
  21 #include <mach/at91sam9260.h>
  22 #include <mach/at91_pmc.h>
  23 #include <mach/at91_rstc.h>
  24 #include <mach/at91_shdwc.h>
  25
  26 #include "soc.h"
  27 #include "generic.h"
  28 #include "clock.h"
  29
  30 static struct map_desc at91sam9260_sram_desc[] __initdata = {
  31         {
  32                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
  33                 .pfn            = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
  34                 .length         = AT91SAM9260_SRAM0_SIZE,
  35                 .type           = MT_DEVICE,
  36         }, {
  37                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE,
  38                 .pfn            = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
  39                 .length         = AT91SAM9260_SRAM1_SIZE,
  40                 .type           = MT_DEVICE,
  41         }
  42 };
  43
  44 static struct map_desc at91sam9g20_sram_desc[] __initdata = {
  45         {
  46                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE,
  47                 .pfn            = __phys_to_pfn(AT91SAM9G20_SRAM0_BASE),
  48                 .length         = AT91SAM9G20_SRAM0_SIZE,
  49                 .type           = MT_DEVICE,
  50         }, {
  51                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE - AT91SAM9G20_SRAM1_SIZE,
  52                 .pfn            = __phys_to_pfn(AT91SAM9G20_SRAM1_BASE),
  53                 .length         = AT91SAM9G20_SRAM1_SIZE,
  54                 .type           = MT_DEVICE,
  55         }
  56 };
  57
  58 static struct map_desc at91sam9xe_sram_desc[] __initdata = {
  59         {
  60                 .pfn            = __phys_to_pfn(AT91SAM9XE_SRAM_BASE),
  61                 .type           = MT_DEVICE,
  62         }
  63 };
  64
  65 /* --------------------------------------------------------------------
  66  *  Clocks
  67  * -------------------------------------------------------------------- */
  68
  69 /*
  70  * The peripheral clocks.
  71  */
  72 static struct clk pioA_clk = {
  73         .name           = "pioA_clk",
  74         .pmc_mask       = 1 << AT91SAM9260_ID_PIOA,
  75         .type           = CLK_TYPE_PERIPHERAL,
  76 };
  77 static struct clk pioB_clk = {
  78         .name           = "pioB_clk",
  79         .pmc_mask       = 1 << AT91SAM9260_ID_PIOB,
  80         .type           = CLK_TYPE_PERIPHERAL,
  81 };
  82 static struct clk pioC_clk = {
  83         .name           = "pioC_clk",
  84         .pmc_mask       = 1 << AT91SAM9260_ID_PIOC,
  85         .type           = CLK_TYPE_PERIPHERAL,
  86 };
  87 static struct clk adc_clk = {
  88         .name           = "adc_clk",
  89         .pmc_mask       = 1 << AT91SAM9260_ID_ADC,
  90         .type           = CLK_TYPE_PERIPHERAL,
  91 };
  92 static struct clk usart0_clk = {
  93         .name           = "usart0_clk",
  94         .pmc_mask       = 1 << AT91SAM9260_ID_US0,
  95         .type           = CLK_TYPE_PERIPHERAL,
  96 };
  97 static struct clk usart1_clk = {
  98         .name           = "usart1_clk",
  99         .pmc_mask       = 1 << AT91SAM9260_ID_US1,
 100         .type           = CLK_TYPE_PERIPHERAL,
 101 };
 102 static struct clk usart2_clk = {
 103         .name           = "usart2_clk",
 104         .pmc_mask       = 1 << AT91SAM9260_ID_US2,
 105         .type           = CLK_TYPE_PERIPHERAL,
 106 };
 107 static struct clk mmc_clk = {
 108         .name           = "mci_clk",
 109         .pmc_mask       = 1 << AT91SAM9260_ID_MCI,
 110         .type           = CLK_TYPE_PERIPHERAL,
 111 };
 112 static struct clk udc_clk = {
 113         .name           = "udc_clk",
 114         .pmc_mask       = 1 << AT91SAM9260_ID_UDP,
 115         .type           = CLK_TYPE_PERIPHERAL,
 116 };
 117 static struct clk twi_clk = {
 118         .name           = "twi_clk",
 119         .pmc_mask       = 1 << AT91SAM9260_ID_TWI,
 120         .type           = CLK_TYPE_PERIPHERAL,
 121 };
 122 static struct clk spi0_clk = {
 123         .name           = "spi0_clk",
 124         .pmc_mask       = 1 << AT91SAM9260_ID_SPI0,
 125         .type           = CLK_TYPE_PERIPHERAL,
 126 };
 127 static struct clk spi1_clk = {
 128         .name           = "spi1_clk",
 129         .pmc_mask       = 1 << AT91SAM9260_ID_SPI1,
 130         .type           = CLK_TYPE_PERIPHERAL,
 131 };
 132 static struct clk ssc_clk = {
 133         .name           = "ssc_clk",
 134         .pmc_mask       = 1 << AT91SAM9260_ID_SSC,
 135         .type           = CLK_TYPE_PERIPHERAL,
 136 };
 137 static struct clk tc0_clk = {
 138         .name           = "tc0_clk",
 139         .pmc_mask       = 1 << AT91SAM9260_ID_TC0,
 140         .type           = CLK_TYPE_PERIPHERAL,
 141 };
 142 static struct clk tc1_clk = {
 143         .name           = "tc1_clk",
 144         .pmc_mask       = 1 << AT91SAM9260_ID_TC1,
 145         .type           = CLK_TYPE_PERIPHERAL,
 146 };
 147 static struct clk tc2_clk = {
 148         .name           = "tc2_clk",
 149         .pmc_mask       = 1 << AT91SAM9260_ID_TC2,
 150         .type           = CLK_TYPE_PERIPHERAL,
 151 };
 152 static struct clk ohci_clk = {
 153         .name           = "ohci_clk",
 154         .pmc_mask       = 1 << AT91SAM9260_ID_UHP,
 155         .type           = CLK_TYPE_PERIPHERAL,
 156 };
 157 static struct clk macb_clk = {
 158         .name           = "macb_clk",
 159         .pmc_mask       = 1 << AT91SAM9260_ID_EMAC,
 160         .type           = CLK_TYPE_PERIPHERAL,
 161 };
 162 static struct clk isi_clk = {
 163         .name           = "isi_clk",
 164         .pmc_mask       = 1 << AT91SAM9260_ID_ISI,
 165         .type           = CLK_TYPE_PERIPHERAL,
 166 };
 167 static struct clk usart3_clk = {
 168         .name           = "usart3_clk",
 169         .pmc_mask       = 1 << AT91SAM9260_ID_US3,
 170         .type           = CLK_TYPE_PERIPHERAL,
 171 };
 172 static struct clk usart4_clk = {
 173         .name           = "usart4_clk",
 174         .pmc_mask       = 1 << AT91SAM9260_ID_US4,
 175         .type           = CLK_TYPE_PERIPHERAL,
 176 };
 177 static struct clk usart5_clk = {
 178         .name           = "usart5_clk",
 179         .pmc_mask       = 1 << AT91SAM9260_ID_US5,
 180         .type           = CLK_TYPE_PERIPHERAL,
 181 };
 182 static struct clk tc3_clk = {
 183         .name           = "tc3_clk",
 184         .pmc_mask       = 1 << AT91SAM9260_ID_TC3,
 185         .type           = CLK_TYPE_PERIPHERAL,
 186 };
 187 static struct clk tc4_clk = {
 188         .name           = "tc4_clk",
 189         .pmc_mask       = 1 << AT91SAM9260_ID_TC4,
 190         .type           = CLK_TYPE_PERIPHERAL,
 191 };
 192 static struct clk tc5_clk = {
 193         .name           = "tc5_clk",
 194         .pmc_mask       = 1 << AT91SAM9260_ID_TC5,
 195         .type           = CLK_TYPE_PERIPHERAL,
 196 };
 197
 198 static struct clk *periph_clocks[] __initdata = {
 199         &pioA_clk,
 200         &pioB_clk,
 201         &pioC_clk,
 202         &adc_clk,
 203         &usart0_clk,
 204         &usart1_clk,
 205         &usart2_clk,
 206         &mmc_clk,
 207         &udc_clk,
 208         &twi_clk,
 209         &spi0_clk,
 210         &spi1_clk,
 211         &ssc_clk,
 212         &tc0_clk,
 213         &tc1_clk,
 214         &tc2_clk,
 215         &ohci_clk,
 216         &macb_clk,
 217         &isi_clk,
 218         &usart3_clk,
 219         &usart4_clk,
 220         &usart5_clk,
 221         &tc3_clk,
 222         &tc4_clk,
 223         &tc5_clk,
 224         // irq0 .. irq2
 225 };
 226
 227 static struct clk_lookup periph_clocks_lookups[] = {
 228         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 229         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 230         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 231         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 232         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 233         CLKDEV_CON_DEV_ID("t3_clk", "atmel_tcb.1", &tc3_clk),
 234         CLKDEV_CON_DEV_ID("t4_clk", "atmel_tcb.1", &tc4_clk),
 235         CLKDEV_CON_DEV_ID("t5_clk", "atmel_tcb.1", &tc5_clk),
 236         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
 237 };
 238
 239 static struct clk_lookup usart_clocks_lookups[] = {
 240         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 241         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 242         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 243         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 244         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 245         CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
 246         CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
 247 };
 248
 249 /*
 250  * The two programmable clocks.
 251  * You must configure pin multiplexing to bring these signals out.
 252  */
 253 static struct clk pck0 = {
 254         .name           = "pck0",
 255         .pmc_mask       = AT91_PMC_PCK0,
 256         .type           = CLK_TYPE_PROGRAMMABLE,
 257         .id             = 0,
 258 };
 259 static struct clk pck1 = {
 260         .name           = "pck1",
 261         .pmc_mask       = AT91_PMC_PCK1,
 262         .type           = CLK_TYPE_PROGRAMMABLE,
 263         .id             = 1,
 264 };
 265
 266 static void __init at91sam9260_register_clocks(void)
 267 {
 268         int i;
 269
 270         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 271                 clk_register(periph_clocks[i]);
 272
 273         clkdev_add_table(periph_clocks_lookups,
 274                          ARRAY_SIZE(periph_clocks_lookups));
 275         clkdev_add_table(usart_clocks_lookups,
 276                          ARRAY_SIZE(usart_clocks_lookups));
 277
 278         clk_register(&pck0);
 279         clk_register(&pck1);
 280 }
 281
 282 static struct clk_lookup console_clock_lookup;
 283
 284 void __init at91sam9260_set_console_clock(int id)
 285 {
 286         if (id >= ARRAY_SIZE(usart_clocks_lookups))
 287                 return;
 288
 289         console_clock_lookup.con_id = "usart";
 290         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
 291         clkdev_add(&console_clock_lookup);
 292 }
 293
 294 /* --------------------------------------------------------------------
 295  *  GPIO
 296  * -------------------------------------------------------------------- */
 297
 298 static struct at91_gpio_bank at91sam9260_gpio[] = {
 299         {
 300                 .id             = AT91SAM9260_ID_PIOA,
 301                 .offset         = AT91_PIOA,
 302                 .clock          = &pioA_clk,
 303         }, {
 304                 .id             = AT91SAM9260_ID_PIOB,
 305                 .offset         = AT91_PIOB,
 306                 .clock          = &pioB_clk,
 307         }, {
 308                 .id             = AT91SAM9260_ID_PIOC,
 309                 .offset         = AT91_PIOC,
 310                 .clock          = &pioC_clk,
 311         }
 312 };
 313
 314 static void at91sam9260_poweroff(void)
 315 {
 316         at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
 317 }
 318
 319
 320 /* --------------------------------------------------------------------
 321  *  AT91SAM9260 processor initialization
 322  * -------------------------------------------------------------------- */
 323
 324 static void __init at91sam9xe_map_io(void)
 325 {
 326         unsigned long sram_size;
 327
 328         switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
 329                 case AT91_CIDR_SRAMSIZ_32K:
 330                         sram_size = 2 * SZ_16K;
 331                         break;
 332                 case AT91_CIDR_SRAMSIZ_16K:
 333                 default:
 334                         sram_size = SZ_16K;
 335         }
 336
 337         at91sam9xe_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
 338         at91sam9xe_sram_desc->length = sram_size;
 339
 340         iotable_init(at91sam9xe_sram_desc, ARRAY_SIZE(at91sam9xe_sram_desc));
 341 }
 342
 343 static void __init at91sam9260_map_io(void)
 344 {
 345         if (cpu_is_at91sam9xe())
 346                 at91sam9xe_map_io();
 347         else if (cpu_is_at91sam9g20())
 348                 iotable_init(at91sam9g20_sram_desc, ARRAY_SIZE(at91sam9g20_sram_desc));
 349         else
 350                 iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
 351 }
 352
 353 static void __init at91sam9260_initialize(void)
 354 {
 355         at91_arch_reset = at91sam9_alt_reset;
 356         pm_power_off = at91sam9260_poweroff;
 357         at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
 358                         | (1 << AT91SAM9260_ID_IRQ2);
 359
 360         /* Register GPIO subsystem */
 361         at91_gpio_init(at91sam9260_gpio, 3);
 362 }
 363
 364 /* --------------------------------------------------------------------
 365  *  Interrupt initialization
 366  * -------------------------------------------------------------------- */
 367
 368 /*
 369  * The default interrupt priority levels (0 = lowest, 7 = highest).
 370  */
 371 static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
 372         7,      /* Advanced Interrupt Controller */
 373         7,      /* System Peripherals */
 374         1,      /* Parallel IO Controller A */
 375         1,      /* Parallel IO Controller B */
 376         1,      /* Parallel IO Controller C */
 377         0,      /* Analog-to-Digital Converter */
 378         5,      /* USART 0 */
 379         5,      /* USART 1 */
 380         5,      /* USART 2 */
 381         0,      /* Multimedia Card Interface */
 382         2,      /* USB Device Port */
 383         6,      /* Two-Wire Interface */
 384         5,      /* Serial Peripheral Interface 0 */
 385         5,      /* Serial Peripheral Interface 1 */
 386         5,      /* Serial Synchronous Controller */
 387         0,
 388         0,
 389         0,      /* Timer Counter 0 */
 390         0,      /* Timer Counter 1 */
 391         0,      /* Timer Counter 2 */
 392         2,      /* USB Host port */
 393         3,      /* Ethernet */
 394         0,      /* Image Sensor Interface */
 395         5,      /* USART 3 */
 396         5,      /* USART 4 */
 397         5,      /* USART 5 */
 398         0,      /* Timer Counter 3 */
 399         0,      /* Timer Counter 4 */
 400         0,      /* Timer Counter 5 */
 401         0,      /* Advanced Interrupt Controller */
 402         0,      /* Advanced Interrupt Controller */
 403         0,      /* Advanced Interrupt Controller */
 404 };
 405
 406 struct at91_init_soc __initdata at91sam9260_soc = {
 407         .map_io = at91sam9260_map_io,
 408         .default_irq_priority = at91sam9260_default_irq_priority,
 409         .register_clocks = at91sam9260_register_clocks,
 410         .init = at91sam9260_initialize,
 411 };