arch/arm/mach-at91/at91rm9200.c

   1 /*
   2  * arch/arm/mach-at91/at91rm9200.c
   3  *
   4  *  Copyright (C) 2005 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14
  15 #include <asm/irq.h>
  16 #include <asm/mach/arch.h>
  17 #include <asm/mach/map.h>
  18 #include <mach/at91rm9200.h>
  19 #include <mach/at91_pmc.h>
  20 #include <mach/at91_st.h>
  21 #include <mach/cpu.h>
  22
  23 #include "soc.h"
  24 #include "generic.h"
  25 #include "clock.h"
  26
  27 static struct map_desc at91rm9200_io_desc[] __initdata = {
  28         {
  29                 .virtual        = AT91_VA_BASE_EMAC,
  30                 .pfn            = __phys_to_pfn(AT91RM9200_BASE_EMAC),
  31                 .length         = SZ_16K,
  32                 .type           = MT_DEVICE,
  33         },
  34 };
  35
  36 /* --------------------------------------------------------------------
  37  *  Clocks
  38  * -------------------------------------------------------------------- */
  39
  40 /*
  41  * The peripheral clocks.
  42  */
  43 static struct clk udc_clk = {
  44         .name           = "udc_clk",
  45         .pmc_mask       = 1 << AT91RM9200_ID_UDP,
  46         .type           = CLK_TYPE_PERIPHERAL,
  47 };
  48 static struct clk ohci_clk = {
  49         .name           = "ohci_clk",
  50         .pmc_mask       = 1 << AT91RM9200_ID_UHP,
  51         .type           = CLK_TYPE_PERIPHERAL,
  52 };
  53 static struct clk ether_clk = {
  54         .name           = "ether_clk",
  55         .pmc_mask       = 1 << AT91RM9200_ID_EMAC,
  56         .type           = CLK_TYPE_PERIPHERAL,
  57 };
  58 static struct clk mmc_clk = {
  59         .name           = "mci_clk",
  60         .pmc_mask       = 1 << AT91RM9200_ID_MCI,
  61         .type           = CLK_TYPE_PERIPHERAL,
  62 };
  63 static struct clk twi_clk = {
  64         .name           = "twi_clk",
  65         .pmc_mask       = 1 << AT91RM9200_ID_TWI,
  66         .type           = CLK_TYPE_PERIPHERAL,
  67 };
  68 static struct clk usart0_clk = {
  69         .name           = "usart0_clk",
  70         .pmc_mask       = 1 << AT91RM9200_ID_US0,
  71         .type           = CLK_TYPE_PERIPHERAL,
  72 };
  73 static struct clk usart1_clk = {
  74         .name           = "usart1_clk",
  75         .pmc_mask       = 1 << AT91RM9200_ID_US1,
  76         .type           = CLK_TYPE_PERIPHERAL,
  77 };
  78 static struct clk usart2_clk = {
  79         .name           = "usart2_clk",
  80         .pmc_mask       = 1 << AT91RM9200_ID_US2,
  81         .type           = CLK_TYPE_PERIPHERAL,
  82 };
  83 static struct clk usart3_clk = {
  84         .name           = "usart3_clk",
  85         .pmc_mask       = 1 << AT91RM9200_ID_US3,
  86         .type           = CLK_TYPE_PERIPHERAL,
  87 };
  88 static struct clk spi_clk = {
  89         .name           = "spi_clk",
  90         .pmc_mask       = 1 << AT91RM9200_ID_SPI,
  91         .type           = CLK_TYPE_PERIPHERAL,
  92 };
  93 static struct clk pioA_clk = {
  94         .name           = "pioA_clk",
  95         .pmc_mask       = 1 << AT91RM9200_ID_PIOA,
  96         .type           = CLK_TYPE_PERIPHERAL,
  97 };
  98 static struct clk pioB_clk = {
  99         .name           = "pioB_clk",
 100         .pmc_mask       = 1 << AT91RM9200_ID_PIOB,
 101         .type           = CLK_TYPE_PERIPHERAL,
 102 };
 103 static struct clk pioC_clk = {
 104         .name           = "pioC_clk",
 105         .pmc_mask       = 1 << AT91RM9200_ID_PIOC,
 106         .type           = CLK_TYPE_PERIPHERAL,
 107 };
 108 static struct clk pioD_clk = {
 109         .name           = "pioD_clk",
 110         .pmc_mask       = 1 << AT91RM9200_ID_PIOD,
 111         .type           = CLK_TYPE_PERIPHERAL,
 112 };
 113 static struct clk ssc0_clk = {
 114         .name           = "ssc0_clk",
 115         .pmc_mask       = 1 << AT91RM9200_ID_SSC0,
 116         .type           = CLK_TYPE_PERIPHERAL,
 117 };
 118 static struct clk ssc1_clk = {
 119         .name           = "ssc1_clk",
 120         .pmc_mask       = 1 << AT91RM9200_ID_SSC1,
 121         .type           = CLK_TYPE_PERIPHERAL,
 122 };
 123 static struct clk ssc2_clk = {
 124         .name           = "ssc2_clk",
 125         .pmc_mask       = 1 << AT91RM9200_ID_SSC2,
 126         .type           = CLK_TYPE_PERIPHERAL,
 127 };
 128 static struct clk tc0_clk = {
 129         .name           = "tc0_clk",
 130         .pmc_mask       = 1 << AT91RM9200_ID_TC0,
 131         .type           = CLK_TYPE_PERIPHERAL,
 132 };
 133 static struct clk tc1_clk = {
 134         .name           = "tc1_clk",
 135         .pmc_mask       = 1 << AT91RM9200_ID_TC1,
 136         .type           = CLK_TYPE_PERIPHERAL,
 137 };
 138 static struct clk tc2_clk = {
 139         .name           = "tc2_clk",
 140         .pmc_mask       = 1 << AT91RM9200_ID_TC2,
 141         .type           = CLK_TYPE_PERIPHERAL,
 142 };
 143 static struct clk tc3_clk = {
 144         .name           = "tc3_clk",
 145         .pmc_mask       = 1 << AT91RM9200_ID_TC3,
 146         .type           = CLK_TYPE_PERIPHERAL,
 147 };
 148 static struct clk tc4_clk = {
 149         .name           = "tc4_clk",
 150         .pmc_mask       = 1 << AT91RM9200_ID_TC4,
 151         .type           = CLK_TYPE_PERIPHERAL,
 152 };
 153 static struct clk tc5_clk = {
 154         .name           = "tc5_clk",
 155         .pmc_mask       = 1 << AT91RM9200_ID_TC5,
 156         .type           = CLK_TYPE_PERIPHERAL,
 157 };
 158
 159 static struct clk *periph_clocks[] __initdata = {
 160         &pioA_clk,
 161         &pioB_clk,
 162         &pioC_clk,
 163         &pioD_clk,
 164         &usart0_clk,
 165         &usart1_clk,
 166         &usart2_clk,
 167         &usart3_clk,
 168         &mmc_clk,
 169         &udc_clk,
 170         &twi_clk,
 171         &spi_clk,
 172         &ssc0_clk,
 173         &ssc1_clk,
 174         &ssc2_clk,
 175         &tc0_clk,
 176         &tc1_clk,
 177         &tc2_clk,
 178         &tc3_clk,
 179         &tc4_clk,
 180         &tc5_clk,
 181         &ohci_clk,
 182         &ether_clk,
 183         // irq0 .. irq6
 184 };
 185
 186 static struct clk_lookup periph_clocks_lookups[] = {
 187         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 188         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 189         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 190         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
 191         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
 192         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
 193         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 194         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 195         CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
 196         /* fake hclk clock */
 197         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 198 };
 199
 200 static struct clk_lookup usart_clocks_lookups[] = {
 201         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 202         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 203         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 204         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 205         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 206 };
 207
 208 /*
 209  * The four programmable clocks.
 210  * You must configure pin multiplexing to bring these signals out.
 211  */
 212 static struct clk pck0 = {
 213         .name           = "pck0",
 214         .pmc_mask       = AT91_PMC_PCK0,
 215         .type           = CLK_TYPE_PROGRAMMABLE,
 216         .id             = 0,
 217 };
 218 static struct clk pck1 = {
 219         .name           = "pck1",
 220         .pmc_mask       = AT91_PMC_PCK1,
 221         .type           = CLK_TYPE_PROGRAMMABLE,
 222         .id             = 1,
 223 };
 224 static struct clk pck2 = {
 225         .name           = "pck2",
 226         .pmc_mask       = AT91_PMC_PCK2,
 227         .type           = CLK_TYPE_PROGRAMMABLE,
 228         .id             = 2,
 229 };
 230 static struct clk pck3 = {
 231         .name           = "pck3",
 232         .pmc_mask       = AT91_PMC_PCK3,
 233         .type           = CLK_TYPE_PROGRAMMABLE,
 234         .id             = 3,
 235 };
 236
 237 static void __init at91rm9200_register_clocks(void)
 238 {
 239         int i;
 240
 241         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 242                 clk_register(periph_clocks[i]);
 243
 244         clkdev_add_table(periph_clocks_lookups,
 245                          ARRAY_SIZE(periph_clocks_lookups));
 246         clkdev_add_table(usart_clocks_lookups,
 247                          ARRAY_SIZE(usart_clocks_lookups));
 248
 249         clk_register(&pck0);
 250         clk_register(&pck1);
 251         clk_register(&pck2);
 252         clk_register(&pck3);
 253 }
 254
 255 static struct clk_lookup console_clock_lookup;
 256
 257 void __init at91rm9200_set_console_clock(int id)
 258 {
 259         if (id >= ARRAY_SIZE(usart_clocks_lookups))
 260                 return;
 261
 262         console_clock_lookup.con_id = "usart";
 263         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
 264         clkdev_add(&console_clock_lookup);
 265 }
 266
 267 /* --------------------------------------------------------------------
 268  *  GPIO
 269  * -------------------------------------------------------------------- */
 270
 271 static struct at91_gpio_bank at91rm9200_gpio[] = {
 272         {
 273                 .id             = AT91RM9200_ID_PIOA,
 274                 .offset         = AT91_PIOA,
 275                 .clock          = &pioA_clk,
 276         }, {
 277                 .id             = AT91RM9200_ID_PIOB,
 278                 .offset         = AT91_PIOB,
 279                 .clock          = &pioB_clk,
 280         }, {
 281                 .id             = AT91RM9200_ID_PIOC,
 282                 .offset         = AT91_PIOC,
 283                 .clock          = &pioC_clk,
 284         }, {
 285                 .id             = AT91RM9200_ID_PIOD,
 286                 .offset         = AT91_PIOD,
 287                 .clock          = &pioD_clk,
 288         }
 289 };
 290
 291 static void at91rm9200_reset(void)
 292 {
 293         /*
 294          * Perform a hardware reset with the use of the Watchdog timer.
 295          */
 296         at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
 297         at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
 298 }
 299
 300 /* --------------------------------------------------------------------
 301  *  AT91RM9200 processor initialization
 302  * -------------------------------------------------------------------- */
 303 static void __init at91rm9200_map_io(void)
 304 {
 305         /* Map peripherals */
 306         at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
 307         iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
 308 }
 309
 310 static void __init at91rm9200_initialize(void)
 311 {
 312         at91_arch_reset = at91rm9200_reset;
 313         at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
 314                         | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
 315                         | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
 316                         | (1 << AT91RM9200_ID_IRQ6);
 317
 318         /* Initialize GPIO subsystem */
 319         at91_gpio_init(at91rm9200_gpio,
 320                 cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
 321 }
 322
 323
 324 /* --------------------------------------------------------------------
 325  *  Interrupt initialization
 326  * -------------------------------------------------------------------- */
 327
 328 /*
 329  * The default interrupt priority levels (0 = lowest, 7 = highest).
 330  */
 331 static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
 332         7,      /* Advanced Interrupt Controller (FIQ) */
 333         7,      /* System Peripherals */
 334         1,      /* Parallel IO Controller A */
 335         1,      /* Parallel IO Controller B */
 336         1,      /* Parallel IO Controller C */
 337         1,      /* Parallel IO Controller D */
 338         5,      /* USART 0 */
 339         5,      /* USART 1 */
 340         5,      /* USART 2 */
 341         5,      /* USART 3 */
 342         0,      /* Multimedia Card Interface */
 343         2,      /* USB Device Port */
 344         6,      /* Two-Wire Interface */
 345         5,      /* Serial Peripheral Interface */
 346         4,      /* Serial Synchronous Controller 0 */
 347         4,      /* Serial Synchronous Controller 1 */
 348         4,      /* Serial Synchronous Controller 2 */
 349         0,      /* Timer Counter 0 */
 350         0,      /* Timer Counter 1 */
 351         0,      /* Timer Counter 2 */
 352         0,      /* Timer Counter 3 */
 353         0,      /* Timer Counter 4 */
 354         0,      /* Timer Counter 5 */
 355         2,      /* USB Host port */
 356         3,      /* Ethernet MAC */
 357         0,      /* Advanced Interrupt Controller (IRQ0) */
 358         0,      /* Advanced Interrupt Controller (IRQ1) */
 359         0,      /* Advanced Interrupt Controller (IRQ2) */
 360         0,      /* Advanced Interrupt Controller (IRQ3) */
 361         0,      /* Advanced Interrupt Controller (IRQ4) */
 362         0,      /* Advanced Interrupt Controller (IRQ5) */
 363         0       /* Advanced Interrupt Controller (IRQ6) */
 364 };
 365
 366 struct at91_init_soc __initdata at91rm9200_soc = {
 367         .map_io = at91rm9200_map_io,
 368         .default_irq_priority = at91rm9200_default_irq_priority,
 369         .register_clocks = at91rm9200_register_clocks,
 370         .init = at91rm9200_initialize,
 371 };