arch/arm/mach-at91/at91rm9200.c

   1 /*
   2  * arch/arm/mach-at91/at91rm9200.c
   3  *
   4  *  Copyright (C) 2005 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14
  15 #include <asm/irq.h>
  16 #include <asm/mach/arch.h>
  17 #include <asm/mach/map.h>
  18 #include <mach/at91rm9200.h>
  19 #include <mach/at91_pmc.h>
  20 #include <mach/at91_st.h>
  21 #include <mach/cpu.h>
  22
  23 #include "soc.h"
  24 #include "generic.h"
  25 #include "clock.h"
  26
  27 static struct map_desc at91rm9200_io_desc[] __initdata = {
  28         {
  29                 .virtual        = AT91_VA_BASE_EMAC,
  30                 .pfn            = __phys_to_pfn(AT91RM9200_BASE_EMAC),
  31                 .length         = SZ_16K,
  32                 .type           = MT_DEVICE,
  33         }, {
  34                 .virtual        = AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE,
  35                 .pfn            = __phys_to_pfn(AT91RM9200_SRAM_BASE),
  36                 .length         = AT91RM9200_SRAM_SIZE,
  37                 .type           = MT_DEVICE,
  38         },
  39 };
  40
  41 /* --------------------------------------------------------------------
  42  *  Clocks
  43  * -------------------------------------------------------------------- */
  44
  45 /*
  46  * The peripheral clocks.
  47  */
  48 static struct clk udc_clk = {
  49         .name           = "udc_clk",
  50         .pmc_mask       = 1 << AT91RM9200_ID_UDP,
  51         .type           = CLK_TYPE_PERIPHERAL,
  52 };
  53 static struct clk ohci_clk = {
  54         .name           = "ohci_clk",
  55         .pmc_mask       = 1 << AT91RM9200_ID_UHP,
  56         .type           = CLK_TYPE_PERIPHERAL,
  57 };
  58 static struct clk ether_clk = {
  59         .name           = "ether_clk",
  60         .pmc_mask       = 1 << AT91RM9200_ID_EMAC,
  61         .type           = CLK_TYPE_PERIPHERAL,
  62 };
  63 static struct clk mmc_clk = {
  64         .name           = "mci_clk",
  65         .pmc_mask       = 1 << AT91RM9200_ID_MCI,
  66         .type           = CLK_TYPE_PERIPHERAL,
  67 };
  68 static struct clk twi_clk = {
  69         .name           = "twi_clk",
  70         .pmc_mask       = 1 << AT91RM9200_ID_TWI,
  71         .type           = CLK_TYPE_PERIPHERAL,
  72 };
  73 static struct clk usart0_clk = {
  74         .name           = "usart0_clk",
  75         .pmc_mask       = 1 << AT91RM9200_ID_US0,
  76         .type           = CLK_TYPE_PERIPHERAL,
  77 };
  78 static struct clk usart1_clk = {
  79         .name           = "usart1_clk",
  80         .pmc_mask       = 1 << AT91RM9200_ID_US1,
  81         .type           = CLK_TYPE_PERIPHERAL,
  82 };
  83 static struct clk usart2_clk = {
  84         .name           = "usart2_clk",
  85         .pmc_mask       = 1 << AT91RM9200_ID_US2,
  86         .type           = CLK_TYPE_PERIPHERAL,
  87 };
  88 static struct clk usart3_clk = {
  89         .name           = "usart3_clk",
  90         .pmc_mask       = 1 << AT91RM9200_ID_US3,
  91         .type           = CLK_TYPE_PERIPHERAL,
  92 };
  93 static struct clk spi_clk = {
  94         .name           = "spi_clk",
  95         .pmc_mask       = 1 << AT91RM9200_ID_SPI,
  96         .type           = CLK_TYPE_PERIPHERAL,
  97 };
  98 static struct clk pioA_clk = {
  99         .name           = "pioA_clk",
 100         .pmc_mask       = 1 << AT91RM9200_ID_PIOA,
 101         .type           = CLK_TYPE_PERIPHERAL,
 102 };
 103 static struct clk pioB_clk = {
 104         .name           = "pioB_clk",
 105         .pmc_mask       = 1 << AT91RM9200_ID_PIOB,
 106         .type           = CLK_TYPE_PERIPHERAL,
 107 };
 108 static struct clk pioC_clk = {
 109         .name           = "pioC_clk",
 110         .pmc_mask       = 1 << AT91RM9200_ID_PIOC,
 111         .type           = CLK_TYPE_PERIPHERAL,
 112 };
 113 static struct clk pioD_clk = {
 114         .name           = "pioD_clk",
 115         .pmc_mask       = 1 << AT91RM9200_ID_PIOD,
 116         .type           = CLK_TYPE_PERIPHERAL,
 117 };
 118 static struct clk ssc0_clk = {
 119         .name           = "ssc0_clk",
 120         .pmc_mask       = 1 << AT91RM9200_ID_SSC0,
 121         .type           = CLK_TYPE_PERIPHERAL,
 122 };
 123 static struct clk ssc1_clk = {
 124         .name           = "ssc1_clk",
 125         .pmc_mask       = 1 << AT91RM9200_ID_SSC1,
 126         .type           = CLK_TYPE_PERIPHERAL,
 127 };
 128 static struct clk ssc2_clk = {
 129         .name           = "ssc2_clk",
 130         .pmc_mask       = 1 << AT91RM9200_ID_SSC2,
 131         .type           = CLK_TYPE_PERIPHERAL,
 132 };
 133 static struct clk tc0_clk = {
 134         .name           = "tc0_clk",
 135         .pmc_mask       = 1 << AT91RM9200_ID_TC0,
 136         .type           = CLK_TYPE_PERIPHERAL,
 137 };
 138 static struct clk tc1_clk = {
 139         .name           = "tc1_clk",
 140         .pmc_mask       = 1 << AT91RM9200_ID_TC1,
 141         .type           = CLK_TYPE_PERIPHERAL,
 142 };
 143 static struct clk tc2_clk = {
 144         .name           = "tc2_clk",
 145         .pmc_mask       = 1 << AT91RM9200_ID_TC2,
 146         .type           = CLK_TYPE_PERIPHERAL,
 147 };
 148 static struct clk tc3_clk = {
 149         .name           = "tc3_clk",
 150         .pmc_mask       = 1 << AT91RM9200_ID_TC3,
 151         .type           = CLK_TYPE_PERIPHERAL,
 152 };
 153 static struct clk tc4_clk = {
 154         .name           = "tc4_clk",
 155         .pmc_mask       = 1 << AT91RM9200_ID_TC4,
 156         .type           = CLK_TYPE_PERIPHERAL,
 157 };
 158 static struct clk tc5_clk = {
 159         .name           = "tc5_clk",
 160         .pmc_mask       = 1 << AT91RM9200_ID_TC5,
 161         .type           = CLK_TYPE_PERIPHERAL,
 162 };
 163
 164 static struct clk *periph_clocks[] __initdata = {
 165         &pioA_clk,
 166         &pioB_clk,
 167         &pioC_clk,
 168         &pioD_clk,
 169         &usart0_clk,
 170         &usart1_clk,
 171         &usart2_clk,
 172         &usart3_clk,
 173         &mmc_clk,
 174         &udc_clk,
 175         &twi_clk,
 176         &spi_clk,
 177         &ssc0_clk,
 178         &ssc1_clk,
 179         &ssc2_clk,
 180         &tc0_clk,
 181         &tc1_clk,
 182         &tc2_clk,
 183         &tc3_clk,
 184         &tc4_clk,
 185         &tc5_clk,
 186         &ohci_clk,
 187         &ether_clk,
 188         // irq0 .. irq6
 189 };
 190
 191 static struct clk_lookup periph_clocks_lookups[] = {
 192         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 193         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 194         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 195         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
 196         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
 197         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
 198         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 199         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 200         CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
 201 };
 202
 203 static struct clk_lookup usart_clocks_lookups[] = {
 204         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 205         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 206         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 207         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 208         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 209 };
 210
 211 /*
 212  * The four programmable clocks.
 213  * You must configure pin multiplexing to bring these signals out.
 214  */
 215 static struct clk pck0 = {
 216         .name           = "pck0",
 217         .pmc_mask       = AT91_PMC_PCK0,
 218         .type           = CLK_TYPE_PROGRAMMABLE,
 219         .id             = 0,
 220 };
 221 static struct clk pck1 = {
 222         .name           = "pck1",
 223         .pmc_mask       = AT91_PMC_PCK1,
 224         .type           = CLK_TYPE_PROGRAMMABLE,
 225         .id             = 1,
 226 };
 227 static struct clk pck2 = {
 228         .name           = "pck2",
 229         .pmc_mask       = AT91_PMC_PCK2,
 230         .type           = CLK_TYPE_PROGRAMMABLE,
 231         .id             = 2,
 232 };
 233 static struct clk pck3 = {
 234         .name           = "pck3",
 235         .pmc_mask       = AT91_PMC_PCK3,
 236         .type           = CLK_TYPE_PROGRAMMABLE,
 237         .id             = 3,
 238 };
 239
 240 static void __init at91rm9200_register_clocks(void)
 241 {
 242         int i;
 243
 244         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 245                 clk_register(periph_clocks[i]);
 246
 247         clkdev_add_table(periph_clocks_lookups,
 248                          ARRAY_SIZE(periph_clocks_lookups));
 249         clkdev_add_table(usart_clocks_lookups,
 250                          ARRAY_SIZE(usart_clocks_lookups));
 251
 252         clk_register(&pck0);
 253         clk_register(&pck1);
 254         clk_register(&pck2);
 255         clk_register(&pck3);
 256 }
 257
 258 static struct clk_lookup console_clock_lookup;
 259
 260 void __init at91rm9200_set_console_clock(int id)
 261 {
 262         if (id >= ARRAY_SIZE(usart_clocks_lookups))
 263                 return;
 264
 265         console_clock_lookup.con_id = "usart";
 266         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
 267         clkdev_add(&console_clock_lookup);
 268 }
 269
 270 /* --------------------------------------------------------------------
 271  *  GPIO
 272  * -------------------------------------------------------------------- */
 273
 274 static struct at91_gpio_bank at91rm9200_gpio[] = {
 275         {
 276                 .id             = AT91RM9200_ID_PIOA,
 277                 .offset         = AT91_PIOA,
 278                 .clock          = &pioA_clk,
 279         }, {
 280                 .id             = AT91RM9200_ID_PIOB,
 281                 .offset         = AT91_PIOB,
 282                 .clock          = &pioB_clk,
 283         }, {
 284                 .id             = AT91RM9200_ID_PIOC,
 285                 .offset         = AT91_PIOC,
 286                 .clock          = &pioC_clk,
 287         }, {
 288                 .id             = AT91RM9200_ID_PIOD,
 289                 .offset         = AT91_PIOD,
 290                 .clock          = &pioD_clk,
 291         }
 292 };
 293
 294 static void at91rm9200_reset(void)
 295 {
 296         /*
 297          * Perform a hardware reset with the use of the Watchdog timer.
 298          */
 299         at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
 300         at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
 301 }
 302
 303 int rm9200_type;
 304 EXPORT_SYMBOL(rm9200_type);
 305
 306 void __init at91rm9200_set_type(int type)
 307 {
 308         rm9200_type = type;
 309 }
 310
 311 /* --------------------------------------------------------------------
 312  *  AT91RM9200 processor initialization
 313  * -------------------------------------------------------------------- */
 314 static void __init at91rm9200_map_io(void)
 315 {
 316         /* Map peripherals */
 317         iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
 318 }
 319
 320 static void __init at91rm9200_initialize(unsigned long main_clock)
 321 {
 322         at91_arch_reset = at91rm9200_reset;
 323         at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
 324                         | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
 325                         | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
 326                         | (1 << AT91RM9200_ID_IRQ6);
 327
 328         /* Init clock subsystem */
 329         at91_clock_init(main_clock);
 330
 331         /* Register the processor-specific clocks */
 332         at91rm9200_register_clocks();
 333
 334         /* Initialize GPIO subsystem */
 335         at91_gpio_init(at91rm9200_gpio,
 336                 cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
 337 }
 338
 339
 340 /* --------------------------------------------------------------------
 341  *  Interrupt initialization
 342  * -------------------------------------------------------------------- */
 343
 344 /*
 345  * The default interrupt priority levels (0 = lowest, 7 = highest).
 346  */
 347 static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
 348         7,      /* Advanced Interrupt Controller (FIQ) */
 349         7,      /* System Peripherals */
 350         1,      /* Parallel IO Controller A */
 351         1,      /* Parallel IO Controller B */
 352         1,      /* Parallel IO Controller C */
 353         1,      /* Parallel IO Controller D */
 354         5,      /* USART 0 */
 355         5,      /* USART 1 */
 356         5,      /* USART 2 */
 357         5,      /* USART 3 */
 358         0,      /* Multimedia Card Interface */
 359         2,      /* USB Device Port */
 360         6,      /* Two-Wire Interface */
 361         5,      /* Serial Peripheral Interface */
 362         4,      /* Serial Synchronous Controller 0 */
 363         4,      /* Serial Synchronous Controller 1 */
 364         4,      /* Serial Synchronous Controller 2 */
 365         0,      /* Timer Counter 0 */
 366         0,      /* Timer Counter 1 */
 367         0,      /* Timer Counter 2 */
 368         0,      /* Timer Counter 3 */
 369         0,      /* Timer Counter 4 */
 370         0,      /* Timer Counter 5 */
 371         2,      /* USB Host port */
 372         3,      /* Ethernet MAC */
 373         0,      /* Advanced Interrupt Controller (IRQ0) */
 374         0,      /* Advanced Interrupt Controller (IRQ1) */
 375         0,      /* Advanced Interrupt Controller (IRQ2) */
 376         0,      /* Advanced Interrupt Controller (IRQ3) */
 377         0,      /* Advanced Interrupt Controller (IRQ4) */
 378         0,      /* Advanced Interrupt Controller (IRQ5) */
 379         0       /* Advanced Interrupt Controller (IRQ6) */
 380 };
 381
 382 void __init at91rm9200_init_interrupts(unsigned int priority[NR_AIC_IRQS])
 383 {
 384         if (!priority)
 385                 priority = at91rm9200_default_irq_priority;
 386
 387         /* Initialize the AIC interrupt controller */
 388         at91_aic_init(priority);
 389
 390         /* Enable GPIO interrupts */
 391         at91_gpio_irq_setup();
 392 }
 393
 394 struct at91_soc __initdata at91rm9200_soc = {
 395         .map_io = at91rm9200_map_io,
 396         .init = at91rm9200_initialize,
 397 };