Merge branch 'linux-next' of git://git.infradead.org/~dedekind/ubi-2.6
[pandora-kernel.git] / arch / arm / mach-at91 / at91cap9_devices.c
1 /*
2  * arch/arm/mach-at91/at91cap9_devices.c
3  *
4  *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5  *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6  *  Copyright (C) 2007 Atmel Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  */
14 #include <asm/mach/arch.h>
15 #include <asm/mach/map.h>
16
17 #include <linux/dma-mapping.h>
18 #include <linux/platform_device.h>
19 #include <linux/i2c-gpio.h>
20
21 #include <video/atmel_lcdc.h>
22
23 #include <asm/arch/board.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/at91cap9.h>
26 #include <asm/arch/at91cap9_matrix.h>
27 #include <asm/arch/at91sam9_smc.h>
28
29 #include "generic.h"
30
31
32 /* --------------------------------------------------------------------
33  *  USB Host
34  * -------------------------------------------------------------------- */
35
36 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
37 static u64 ohci_dmamask = DMA_BIT_MASK(32);
38 static struct at91_usbh_data usbh_data;
39
40 static struct resource usbh_resources[] = {
41         [0] = {
42                 .start  = AT91CAP9_UHP_BASE,
43                 .end    = AT91CAP9_UHP_BASE + SZ_1M - 1,
44                 .flags  = IORESOURCE_MEM,
45         },
46         [1] = {
47                 .start  = AT91CAP9_ID_UHP,
48                 .end    = AT91CAP9_ID_UHP,
49                 .flags  = IORESOURCE_IRQ,
50         },
51 };
52
53 static struct platform_device at91_usbh_device = {
54         .name           = "at91_ohci",
55         .id             = -1,
56         .dev            = {
57                                 .dma_mask               = &ohci_dmamask,
58                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
59                                 .platform_data          = &usbh_data,
60         },
61         .resource       = usbh_resources,
62         .num_resources  = ARRAY_SIZE(usbh_resources),
63 };
64
65 void __init at91_add_device_usbh(struct at91_usbh_data *data)
66 {
67         int i;
68
69         if (!data)
70                 return;
71
72         /* Enable VBus control for UHP ports */
73         for (i = 0; i < data->ports; i++) {
74                 if (data->vbus_pin[i])
75                         at91_set_gpio_output(data->vbus_pin[i], 0);
76         }
77
78         usbh_data = *data;
79         platform_device_register(&at91_usbh_device);
80 }
81 #else
82 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
83 #endif
84
85
86 /* --------------------------------------------------------------------
87  *  USB HS Device (Gadget)
88  * -------------------------------------------------------------------- */
89
90 #if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
91
92 static struct resource usba_udc_resources[] = {
93         [0] = {
94                 .start  = AT91CAP9_UDPHS_FIFO,
95                 .end    = AT91CAP9_UDPHS_FIFO + SZ_512K - 1,
96                 .flags  = IORESOURCE_MEM,
97         },
98         [1] = {
99                 .start  = AT91CAP9_BASE_UDPHS,
100                 .end    = AT91CAP9_BASE_UDPHS + SZ_1K - 1,
101                 .flags  = IORESOURCE_MEM,
102         },
103         [2] = {
104                 .start  = AT91CAP9_ID_UDPHS,
105                 .end    = AT91CAP9_ID_UDPHS,
106                 .flags  = IORESOURCE_IRQ,
107         },
108 };
109
110 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
111         [idx] = {                                               \
112                 .name           = nam,                          \
113                 .index          = idx,                          \
114                 .fifo_size      = maxpkt,                       \
115                 .nr_banks       = maxbk,                        \
116                 .can_dma        = dma,                          \
117                 .can_isoc       = isoc,                         \
118         }
119
120 static struct usba_ep_data usba_udc_ep[] = {
121         EP("ep0", 0,   64, 1, 0, 0),
122         EP("ep1", 1, 1024, 3, 1, 1),
123         EP("ep2", 2, 1024, 3, 1, 1),
124         EP("ep3", 3, 1024, 2, 1, 1),
125         EP("ep4", 4, 1024, 2, 1, 1),
126         EP("ep5", 5, 1024, 2, 1, 0),
127         EP("ep6", 6, 1024, 2, 1, 0),
128         EP("ep7", 7, 1024, 2, 0, 0),
129 };
130
131 #undef EP
132
133 /*
134  * pdata doesn't have room for any endpoints, so we need to
135  * append room for the ones we need right after it.
136  */
137 static struct {
138         struct usba_platform_data pdata;
139         struct usba_ep_data ep[8];
140 } usba_udc_data;
141
142 static struct platform_device at91_usba_udc_device = {
143         .name           = "atmel_usba_udc",
144         .id             = -1,
145         .dev            = {
146                                 .platform_data  = &usba_udc_data.pdata,
147         },
148         .resource       = usba_udc_resources,
149         .num_resources  = ARRAY_SIZE(usba_udc_resources),
150 };
151
152 void __init at91_add_device_usba(struct usba_platform_data *data)
153 {
154         at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
155                                           AT91_MATRIX_UDPHS_BYPASS_LOCK);
156
157         /*
158          * Invalid pins are 0 on AT91, but the usba driver is shared
159          * with AVR32, which use negative values instead. Once/if
160          * gpio_is_valid() is ported to AT91, revisit this code.
161          */
162         usba_udc_data.pdata.vbus_pin = -EINVAL;
163         usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
164         memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
165
166         if (data && data->vbus_pin > 0) {
167                 at91_set_gpio_input(data->vbus_pin, 0);
168                 at91_set_deglitch(data->vbus_pin, 1);
169                 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
170         }
171
172         /* Pullup pin is handled internally by USB device peripheral */
173
174         /* Clocks */
175         at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
176         at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
177
178         platform_device_register(&at91_usba_udc_device);
179 }
180 #else
181 void __init at91_add_device_usba(struct usba_platform_data *data) {}
182 #endif
183
184
185 /* --------------------------------------------------------------------
186  *  Ethernet
187  * -------------------------------------------------------------------- */
188
189 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
190 static u64 eth_dmamask = DMA_BIT_MASK(32);
191 static struct at91_eth_data eth_data;
192
193 static struct resource eth_resources[] = {
194         [0] = {
195                 .start  = AT91CAP9_BASE_EMAC,
196                 .end    = AT91CAP9_BASE_EMAC + SZ_16K - 1,
197                 .flags  = IORESOURCE_MEM,
198         },
199         [1] = {
200                 .start  = AT91CAP9_ID_EMAC,
201                 .end    = AT91CAP9_ID_EMAC,
202                 .flags  = IORESOURCE_IRQ,
203         },
204 };
205
206 static struct platform_device at91cap9_eth_device = {
207         .name           = "macb",
208         .id             = -1,
209         .dev            = {
210                                 .dma_mask               = &eth_dmamask,
211                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
212                                 .platform_data          = &eth_data,
213         },
214         .resource       = eth_resources,
215         .num_resources  = ARRAY_SIZE(eth_resources),
216 };
217
218 void __init at91_add_device_eth(struct at91_eth_data *data)
219 {
220         if (!data)
221                 return;
222
223         if (data->phy_irq_pin) {
224                 at91_set_gpio_input(data->phy_irq_pin, 0);
225                 at91_set_deglitch(data->phy_irq_pin, 1);
226         }
227
228         /* Pins used for MII and RMII */
229         at91_set_A_periph(AT91_PIN_PB21, 0);    /* ETXCK_EREFCK */
230         at91_set_A_periph(AT91_PIN_PB22, 0);    /* ERXDV */
231         at91_set_A_periph(AT91_PIN_PB25, 0);    /* ERX0 */
232         at91_set_A_periph(AT91_PIN_PB26, 0);    /* ERX1 */
233         at91_set_A_periph(AT91_PIN_PB27, 0);    /* ERXER */
234         at91_set_A_periph(AT91_PIN_PB28, 0);    /* ETXEN */
235         at91_set_A_periph(AT91_PIN_PB23, 0);    /* ETX0 */
236         at91_set_A_periph(AT91_PIN_PB24, 0);    /* ETX1 */
237         at91_set_A_periph(AT91_PIN_PB30, 0);    /* EMDIO */
238         at91_set_A_periph(AT91_PIN_PB29, 0);    /* EMDC */
239
240         if (!data->is_rmii) {
241                 at91_set_B_periph(AT91_PIN_PC25, 0);    /* ECRS */
242                 at91_set_B_periph(AT91_PIN_PC26, 0);    /* ECOL */
243                 at91_set_B_periph(AT91_PIN_PC22, 0);    /* ERX2 */
244                 at91_set_B_periph(AT91_PIN_PC23, 0);    /* ERX3 */
245                 at91_set_B_periph(AT91_PIN_PC27, 0);    /* ERXCK */
246                 at91_set_B_periph(AT91_PIN_PC20, 0);    /* ETX2 */
247                 at91_set_B_periph(AT91_PIN_PC21, 0);    /* ETX3 */
248                 at91_set_B_periph(AT91_PIN_PC24, 0);    /* ETXER */
249         }
250
251         eth_data = *data;
252         platform_device_register(&at91cap9_eth_device);
253 }
254 #else
255 void __init at91_add_device_eth(struct at91_eth_data *data) {}
256 #endif
257
258
259 /* --------------------------------------------------------------------
260  *  MMC / SD
261  * -------------------------------------------------------------------- */
262
263 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
264 static u64 mmc_dmamask = DMA_BIT_MASK(32);
265 static struct at91_mmc_data mmc0_data, mmc1_data;
266
267 static struct resource mmc0_resources[] = {
268         [0] = {
269                 .start  = AT91CAP9_BASE_MCI0,
270                 .end    = AT91CAP9_BASE_MCI0 + SZ_16K - 1,
271                 .flags  = IORESOURCE_MEM,
272         },
273         [1] = {
274                 .start  = AT91CAP9_ID_MCI0,
275                 .end    = AT91CAP9_ID_MCI0,
276                 .flags  = IORESOURCE_IRQ,
277         },
278 };
279
280 static struct platform_device at91cap9_mmc0_device = {
281         .name           = "at91_mci",
282         .id             = 0,
283         .dev            = {
284                                 .dma_mask               = &mmc_dmamask,
285                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
286                                 .platform_data          = &mmc0_data,
287         },
288         .resource       = mmc0_resources,
289         .num_resources  = ARRAY_SIZE(mmc0_resources),
290 };
291
292 static struct resource mmc1_resources[] = {
293         [0] = {
294                 .start  = AT91CAP9_BASE_MCI1,
295                 .end    = AT91CAP9_BASE_MCI1 + SZ_16K - 1,
296                 .flags  = IORESOURCE_MEM,
297         },
298         [1] = {
299                 .start  = AT91CAP9_ID_MCI1,
300                 .end    = AT91CAP9_ID_MCI1,
301                 .flags  = IORESOURCE_IRQ,
302         },
303 };
304
305 static struct platform_device at91cap9_mmc1_device = {
306         .name           = "at91_mci",
307         .id             = 1,
308         .dev            = {
309                                 .dma_mask               = &mmc_dmamask,
310                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
311                                 .platform_data          = &mmc1_data,
312         },
313         .resource       = mmc1_resources,
314         .num_resources  = ARRAY_SIZE(mmc1_resources),
315 };
316
317 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
318 {
319         if (!data)
320                 return;
321
322         /* input/irq */
323         if (data->det_pin) {
324                 at91_set_gpio_input(data->det_pin, 1);
325                 at91_set_deglitch(data->det_pin, 1);
326         }
327         if (data->wp_pin)
328                 at91_set_gpio_input(data->wp_pin, 1);
329         if (data->vcc_pin)
330                 at91_set_gpio_output(data->vcc_pin, 0);
331
332         if (mmc_id == 0) {              /* MCI0 */
333                 /* CLK */
334                 at91_set_A_periph(AT91_PIN_PA2, 0);
335
336                 /* CMD */
337                 at91_set_A_periph(AT91_PIN_PA1, 1);
338
339                 /* DAT0, maybe DAT1..DAT3 */
340                 at91_set_A_periph(AT91_PIN_PA0, 1);
341                 if (data->wire4) {
342                         at91_set_A_periph(AT91_PIN_PA3, 1);
343                         at91_set_A_periph(AT91_PIN_PA4, 1);
344                         at91_set_A_periph(AT91_PIN_PA5, 1);
345                 }
346
347                 mmc0_data = *data;
348                 at91_clock_associate("mci0_clk", &at91cap9_mmc0_device.dev, "mci_clk");
349                 platform_device_register(&at91cap9_mmc0_device);
350         } else {                        /* MCI1 */
351                 /* CLK */
352                 at91_set_A_periph(AT91_PIN_PA16, 0);
353
354                 /* CMD */
355                 at91_set_A_periph(AT91_PIN_PA17, 1);
356
357                 /* DAT0, maybe DAT1..DAT3 */
358                 at91_set_A_periph(AT91_PIN_PA18, 1);
359                 if (data->wire4) {
360                         at91_set_A_periph(AT91_PIN_PA19, 1);
361                         at91_set_A_periph(AT91_PIN_PA20, 1);
362                         at91_set_A_periph(AT91_PIN_PA21, 1);
363                 }
364
365                 mmc1_data = *data;
366                 at91_clock_associate("mci1_clk", &at91cap9_mmc1_device.dev, "mci_clk");
367                 platform_device_register(&at91cap9_mmc1_device);
368         }
369 }
370 #else
371 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
372 #endif
373
374
375 /* --------------------------------------------------------------------
376  *  NAND / SmartMedia
377  * -------------------------------------------------------------------- */
378
379 #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
380 static struct atmel_nand_data nand_data;
381
382 #define NAND_BASE       AT91_CHIPSELECT_3
383
384 static struct resource nand_resources[] = {
385         [0] = {
386                 .start  = NAND_BASE,
387                 .end    = NAND_BASE + SZ_256M - 1,
388                 .flags  = IORESOURCE_MEM,
389         },
390         [1] = {
391                 .start  = AT91_BASE_SYS + AT91_ECC,
392                 .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
393                 .flags  = IORESOURCE_MEM,
394         }
395 };
396
397 static struct platform_device at91cap9_nand_device = {
398         .name           = "atmel_nand",
399         .id             = -1,
400         .dev            = {
401                                 .platform_data  = &nand_data,
402         },
403         .resource       = nand_resources,
404         .num_resources  = ARRAY_SIZE(nand_resources),
405 };
406
407 void __init at91_add_device_nand(struct atmel_nand_data *data)
408 {
409         unsigned long csa, mode;
410
411         if (!data)
412                 return;
413
414         csa = at91_sys_read(AT91_MATRIX_EBICSA);
415         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
416
417         /* set the bus interface characteristics */
418         at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1)
419                         | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
420
421         at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6)
422                         | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
423
424         at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
425
426         if (data->bus_width_16)
427                 mode = AT91_SMC_DBW_16;
428         else
429                 mode = AT91_SMC_DBW_8;
430         at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
431
432         /* enable pin */
433         if (data->enable_pin)
434                 at91_set_gpio_output(data->enable_pin, 1);
435
436         /* ready/busy pin */
437         if (data->rdy_pin)
438                 at91_set_gpio_input(data->rdy_pin, 1);
439
440         /* card detect pin */
441         if (data->det_pin)
442                 at91_set_gpio_input(data->det_pin, 1);
443
444         nand_data = *data;
445         platform_device_register(&at91cap9_nand_device);
446 }
447 #else
448 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
449 #endif
450
451
452 /* --------------------------------------------------------------------
453  *  TWI (i2c)
454  * -------------------------------------------------------------------- */
455
456 /*
457  * Prefer the GPIO code since the TWI controller isn't robust
458  * (gets overruns and underruns under load) and can only issue
459  * repeated STARTs in one scenario (the driver doesn't yet handle them).
460  */
461 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
462
463 static struct i2c_gpio_platform_data pdata = {
464         .sda_pin                = AT91_PIN_PB4,
465         .sda_is_open_drain      = 1,
466         .scl_pin                = AT91_PIN_PB5,
467         .scl_is_open_drain      = 1,
468         .udelay                 = 2,            /* ~100 kHz */
469 };
470
471 static struct platform_device at91cap9_twi_device = {
472         .name                   = "i2c-gpio",
473         .id                     = -1,
474         .dev.platform_data      = &pdata,
475 };
476
477 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
478 {
479         at91_set_GPIO_periph(AT91_PIN_PB4, 1);          /* TWD (SDA) */
480         at91_set_multi_drive(AT91_PIN_PB4, 1);
481
482         at91_set_GPIO_periph(AT91_PIN_PB5, 1);          /* TWCK (SCL) */
483         at91_set_multi_drive(AT91_PIN_PB5, 1);
484
485         i2c_register_board_info(0, devices, nr_devices);
486         platform_device_register(&at91cap9_twi_device);
487 }
488
489 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
490
491 static struct resource twi_resources[] = {
492         [0] = {
493                 .start  = AT91CAP9_BASE_TWI,
494                 .end    = AT91CAP9_BASE_TWI + SZ_16K - 1,
495                 .flags  = IORESOURCE_MEM,
496         },
497         [1] = {
498                 .start  = AT91CAP9_ID_TWI,
499                 .end    = AT91CAP9_ID_TWI,
500                 .flags  = IORESOURCE_IRQ,
501         },
502 };
503
504 static struct platform_device at91cap9_twi_device = {
505         .name           = "at91_i2c",
506         .id             = -1,
507         .resource       = twi_resources,
508         .num_resources  = ARRAY_SIZE(twi_resources),
509 };
510
511 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
512 {
513         /* pins used for TWI interface */
514         at91_set_B_periph(AT91_PIN_PB4, 0);             /* TWD */
515         at91_set_multi_drive(AT91_PIN_PB4, 1);
516
517         at91_set_B_periph(AT91_PIN_PB5, 0);             /* TWCK */
518         at91_set_multi_drive(AT91_PIN_PB5, 1);
519
520         i2c_register_board_info(0, devices, nr_devices);
521         platform_device_register(&at91cap9_twi_device);
522 }
523 #else
524 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
525 #endif
526
527 /* --------------------------------------------------------------------
528  *  SPI
529  * -------------------------------------------------------------------- */
530
531 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
532 static u64 spi_dmamask = DMA_BIT_MASK(32);
533
534 static struct resource spi0_resources[] = {
535         [0] = {
536                 .start  = AT91CAP9_BASE_SPI0,
537                 .end    = AT91CAP9_BASE_SPI0 + SZ_16K - 1,
538                 .flags  = IORESOURCE_MEM,
539         },
540         [1] = {
541                 .start  = AT91CAP9_ID_SPI0,
542                 .end    = AT91CAP9_ID_SPI0,
543                 .flags  = IORESOURCE_IRQ,
544         },
545 };
546
547 static struct platform_device at91cap9_spi0_device = {
548         .name           = "atmel_spi",
549         .id             = 0,
550         .dev            = {
551                                 .dma_mask               = &spi_dmamask,
552                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
553         },
554         .resource       = spi0_resources,
555         .num_resources  = ARRAY_SIZE(spi0_resources),
556 };
557
558 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PD0, AT91_PIN_PD1 };
559
560 static struct resource spi1_resources[] = {
561         [0] = {
562                 .start  = AT91CAP9_BASE_SPI1,
563                 .end    = AT91CAP9_BASE_SPI1 + SZ_16K - 1,
564                 .flags  = IORESOURCE_MEM,
565         },
566         [1] = {
567                 .start  = AT91CAP9_ID_SPI1,
568                 .end    = AT91CAP9_ID_SPI1,
569                 .flags  = IORESOURCE_IRQ,
570         },
571 };
572
573 static struct platform_device at91cap9_spi1_device = {
574         .name           = "atmel_spi",
575         .id             = 1,
576         .dev            = {
577                                 .dma_mask               = &spi_dmamask,
578                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
579         },
580         .resource       = spi1_resources,
581         .num_resources  = ARRAY_SIZE(spi1_resources),
582 };
583
584 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
585
586 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
587 {
588         int i;
589         unsigned long cs_pin;
590         short enable_spi0 = 0;
591         short enable_spi1 = 0;
592
593         /* Choose SPI chip-selects */
594         for (i = 0; i < nr_devices; i++) {
595                 if (devices[i].controller_data)
596                         cs_pin = (unsigned long) devices[i].controller_data;
597                 else if (devices[i].bus_num == 0)
598                         cs_pin = spi0_standard_cs[devices[i].chip_select];
599                 else
600                         cs_pin = spi1_standard_cs[devices[i].chip_select];
601
602                 if (devices[i].bus_num == 0)
603                         enable_spi0 = 1;
604                 else
605                         enable_spi1 = 1;
606
607                 /* enable chip-select pin */
608                 at91_set_gpio_output(cs_pin, 1);
609
610                 /* pass chip-select pin to driver */
611                 devices[i].controller_data = (void *) cs_pin;
612         }
613
614         spi_register_board_info(devices, nr_devices);
615
616         /* Configure SPI bus(es) */
617         if (enable_spi0) {
618                 at91_set_B_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
619                 at91_set_B_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
620                 at91_set_B_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
621
622                 at91_clock_associate("spi0_clk", &at91cap9_spi0_device.dev, "spi_clk");
623                 platform_device_register(&at91cap9_spi0_device);
624         }
625         if (enable_spi1) {
626                 at91_set_A_periph(AT91_PIN_PB12, 0);    /* SPI1_MISO */
627                 at91_set_A_periph(AT91_PIN_PB13, 0);    /* SPI1_MOSI */
628                 at91_set_A_periph(AT91_PIN_PB14, 0);    /* SPI1_SPCK */
629
630                 at91_clock_associate("spi1_clk", &at91cap9_spi1_device.dev, "spi_clk");
631                 platform_device_register(&at91cap9_spi1_device);
632         }
633 }
634 #else
635 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
636 #endif
637
638
639 /* --------------------------------------------------------------------
640  *  Timer/Counter block
641  * -------------------------------------------------------------------- */
642
643 #ifdef CONFIG_ATMEL_TCLIB
644
645 static struct resource tcb_resources[] = {
646         [0] = {
647                 .start  = AT91CAP9_BASE_TCB0,
648                 .end    = AT91CAP9_BASE_TCB0 + SZ_16K - 1,
649                 .flags  = IORESOURCE_MEM,
650         },
651         [1] = {
652                 .start  = AT91CAP9_ID_TCB,
653                 .end    = AT91CAP9_ID_TCB,
654                 .flags  = IORESOURCE_IRQ,
655         },
656 };
657
658 static struct platform_device at91cap9_tcb_device = {
659         .name           = "atmel_tcb",
660         .id             = 0,
661         .resource       = tcb_resources,
662         .num_resources  = ARRAY_SIZE(tcb_resources),
663 };
664
665 static void __init at91_add_device_tc(void)
666 {
667         /* this chip has one clock and irq for all three TC channels */
668         at91_clock_associate("tcb_clk", &at91cap9_tcb_device.dev, "t0_clk");
669         platform_device_register(&at91cap9_tcb_device);
670 }
671 #else
672 static void __init at91_add_device_tc(void) { }
673 #endif
674
675
676 /* --------------------------------------------------------------------
677  *  RTT
678  * -------------------------------------------------------------------- */
679
680 static struct resource rtt_resources[] = {
681         {
682                 .start  = AT91_BASE_SYS + AT91_RTT,
683                 .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
684                 .flags  = IORESOURCE_MEM,
685         }
686 };
687
688 static struct platform_device at91cap9_rtt_device = {
689         .name           = "at91_rtt",
690         .id             = 0,
691         .resource       = rtt_resources,
692         .num_resources  = ARRAY_SIZE(rtt_resources),
693 };
694
695 static void __init at91_add_device_rtt(void)
696 {
697         platform_device_register(&at91cap9_rtt_device);
698 }
699
700
701 /* --------------------------------------------------------------------
702  *  Watchdog
703  * -------------------------------------------------------------------- */
704
705 #if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
706 static struct platform_device at91cap9_wdt_device = {
707         .name           = "at91_wdt",
708         .id             = -1,
709         .num_resources  = 0,
710 };
711
712 static void __init at91_add_device_watchdog(void)
713 {
714         platform_device_register(&at91cap9_wdt_device);
715 }
716 #else
717 static void __init at91_add_device_watchdog(void) {}
718 #endif
719
720
721 /* --------------------------------------------------------------------
722  *  AC97
723  * -------------------------------------------------------------------- */
724
725 #if defined(CONFIG_SND_AT91_AC97) || defined(CONFIG_SND_AT91_AC97_MODULE)
726 static u64 ac97_dmamask = DMA_BIT_MASK(32);
727 static struct atmel_ac97_data ac97_data;
728
729 static struct resource ac97_resources[] = {
730         [0] = {
731                 .start  = AT91CAP9_BASE_AC97C,
732                 .end    = AT91CAP9_BASE_AC97C + SZ_16K - 1,
733                 .flags  = IORESOURCE_MEM,
734         },
735         [1] = {
736                 .start  = AT91CAP9_ID_AC97C,
737                 .end    = AT91CAP9_ID_AC97C,
738                 .flags  = IORESOURCE_IRQ,
739         },
740 };
741
742 static struct platform_device at91cap9_ac97_device = {
743         .name           = "ac97c",
744         .id             = 1,
745         .dev            = {
746                                 .dma_mask               = &ac97_dmamask,
747                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
748                                 .platform_data          = &ac97_data,
749         },
750         .resource       = ac97_resources,
751         .num_resources  = ARRAY_SIZE(ac97_resources),
752 };
753
754 void __init at91_add_device_ac97(struct atmel_ac97_data *data)
755 {
756         if (!data)
757                 return;
758
759         at91_set_A_periph(AT91_PIN_PA6, 0);     /* AC97FS */
760         at91_set_A_periph(AT91_PIN_PA7, 0);     /* AC97CK */
761         at91_set_A_periph(AT91_PIN_PA8, 0);     /* AC97TX */
762         at91_set_A_periph(AT91_PIN_PA9, 0);     /* AC97RX */
763
764         /* reset */
765         if (data->reset_pin)
766                 at91_set_gpio_output(data->reset_pin, 0);
767
768         ac97_data = *data;
769         platform_device_register(&at91cap9_ac97_device);
770 }
771 #else
772 void __init at91_add_device_ac97(struct atmel_ac97_data *data) {}
773 #endif
774
775
776 /* --------------------------------------------------------------------
777  *  LCD Controller
778  * -------------------------------------------------------------------- */
779
780 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
781 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
782 static struct atmel_lcdfb_info lcdc_data;
783
784 static struct resource lcdc_resources[] = {
785         [0] = {
786                 .start  = AT91CAP9_LCDC_BASE,
787                 .end    = AT91CAP9_LCDC_BASE + SZ_4K - 1,
788                 .flags  = IORESOURCE_MEM,
789         },
790         [1] = {
791                 .start  = AT91CAP9_ID_LCDC,
792                 .end    = AT91CAP9_ID_LCDC,
793                 .flags  = IORESOURCE_IRQ,
794         },
795 };
796
797 static struct platform_device at91_lcdc_device = {
798         .name           = "atmel_lcdfb",
799         .id             = 0,
800         .dev            = {
801                                 .dma_mask               = &lcdc_dmamask,
802                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
803                                 .platform_data          = &lcdc_data,
804         },
805         .resource       = lcdc_resources,
806         .num_resources  = ARRAY_SIZE(lcdc_resources),
807 };
808
809 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
810 {
811         if (!data)
812                 return;
813
814         at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
815         at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
816         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
817         at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
818         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
819         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
820         at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
821         at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
822         at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
823         at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
824         at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
825         at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
826         at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
827         at91_set_A_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
828         at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
829         at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
830         at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
831         at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
832         at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
833         at91_set_A_periph(AT91_PIN_PC25, 0);    /* LCDD21 */
834         at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
835         at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
836
837         lcdc_data = *data;
838         platform_device_register(&at91_lcdc_device);
839 }
840 #else
841 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
842 #endif
843
844
845 /* --------------------------------------------------------------------
846  *  SSC -- Synchronous Serial Controller
847  * -------------------------------------------------------------------- */
848
849 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
850 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
851
852 static struct resource ssc0_resources[] = {
853         [0] = {
854                 .start  = AT91CAP9_BASE_SSC0,
855                 .end    = AT91CAP9_BASE_SSC0 + SZ_16K - 1,
856                 .flags  = IORESOURCE_MEM,
857         },
858         [1] = {
859                 .start  = AT91CAP9_ID_SSC0,
860                 .end    = AT91CAP9_ID_SSC0,
861                 .flags  = IORESOURCE_IRQ,
862         },
863 };
864
865 static struct platform_device at91cap9_ssc0_device = {
866         .name   = "ssc",
867         .id     = 0,
868         .dev    = {
869                 .dma_mask               = &ssc0_dmamask,
870                 .coherent_dma_mask      = DMA_BIT_MASK(32),
871         },
872         .resource       = ssc0_resources,
873         .num_resources  = ARRAY_SIZE(ssc0_resources),
874 };
875
876 static inline void configure_ssc0_pins(unsigned pins)
877 {
878         if (pins & ATMEL_SSC_TF)
879                 at91_set_A_periph(AT91_PIN_PB0, 1);
880         if (pins & ATMEL_SSC_TK)
881                 at91_set_A_periph(AT91_PIN_PB1, 1);
882         if (pins & ATMEL_SSC_TD)
883                 at91_set_A_periph(AT91_PIN_PB2, 1);
884         if (pins & ATMEL_SSC_RD)
885                 at91_set_A_periph(AT91_PIN_PB3, 1);
886         if (pins & ATMEL_SSC_RK)
887                 at91_set_A_periph(AT91_PIN_PB4, 1);
888         if (pins & ATMEL_SSC_RF)
889                 at91_set_A_periph(AT91_PIN_PB5, 1);
890 }
891
892 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
893
894 static struct resource ssc1_resources[] = {
895         [0] = {
896                 .start  = AT91CAP9_BASE_SSC1,
897                 .end    = AT91CAP9_BASE_SSC1 + SZ_16K - 1,
898                 .flags  = IORESOURCE_MEM,
899         },
900         [1] = {
901                 .start  = AT91CAP9_ID_SSC1,
902                 .end    = AT91CAP9_ID_SSC1,
903                 .flags  = IORESOURCE_IRQ,
904         },
905 };
906
907 static struct platform_device at91cap9_ssc1_device = {
908         .name   = "ssc",
909         .id     = 1,
910         .dev    = {
911                 .dma_mask               = &ssc1_dmamask,
912                 .coherent_dma_mask      = DMA_BIT_MASK(32),
913         },
914         .resource       = ssc1_resources,
915         .num_resources  = ARRAY_SIZE(ssc1_resources),
916 };
917
918 static inline void configure_ssc1_pins(unsigned pins)
919 {
920         if (pins & ATMEL_SSC_TF)
921                 at91_set_A_periph(AT91_PIN_PB6, 1);
922         if (pins & ATMEL_SSC_TK)
923                 at91_set_A_periph(AT91_PIN_PB7, 1);
924         if (pins & ATMEL_SSC_TD)
925                 at91_set_A_periph(AT91_PIN_PB8, 1);
926         if (pins & ATMEL_SSC_RD)
927                 at91_set_A_periph(AT91_PIN_PB9, 1);
928         if (pins & ATMEL_SSC_RK)
929                 at91_set_A_periph(AT91_PIN_PB10, 1);
930         if (pins & ATMEL_SSC_RF)
931                 at91_set_A_periph(AT91_PIN_PB11, 1);
932 }
933
934 /*
935  * SSC controllers are accessed through library code, instead of any
936  * kind of all-singing/all-dancing driver.  For example one could be
937  * used by a particular I2S audio codec's driver, while another one
938  * on the same system might be used by a custom data capture driver.
939  */
940 void __init at91_add_device_ssc(unsigned id, unsigned pins)
941 {
942         struct platform_device *pdev;
943
944         /*
945          * NOTE: caller is responsible for passing information matching
946          * "pins" to whatever will be using each particular controller.
947          */
948         switch (id) {
949         case AT91CAP9_ID_SSC0:
950                 pdev = &at91cap9_ssc0_device;
951                 configure_ssc0_pins(pins);
952                 at91_clock_associate("ssc0_clk", &pdev->dev, "ssc");
953                 break;
954         case AT91CAP9_ID_SSC1:
955                 pdev = &at91cap9_ssc1_device;
956                 configure_ssc1_pins(pins);
957                 at91_clock_associate("ssc1_clk", &pdev->dev, "ssc");
958                 break;
959         default:
960                 return;
961         }
962
963         platform_device_register(pdev);
964 }
965
966 #else
967 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
968 #endif
969
970
971 /* --------------------------------------------------------------------
972  *  UART
973  * -------------------------------------------------------------------- */
974
975 #if defined(CONFIG_SERIAL_ATMEL)
976 static struct resource dbgu_resources[] = {
977         [0] = {
978                 .start  = AT91_VA_BASE_SYS + AT91_DBGU,
979                 .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
980                 .flags  = IORESOURCE_MEM,
981         },
982         [1] = {
983                 .start  = AT91_ID_SYS,
984                 .end    = AT91_ID_SYS,
985                 .flags  = IORESOURCE_IRQ,
986         },
987 };
988
989 static struct atmel_uart_data dbgu_data = {
990         .use_dma_tx     = 0,
991         .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
992         .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
993 };
994
995 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
996
997 static struct platform_device at91cap9_dbgu_device = {
998         .name           = "atmel_usart",
999         .id             = 0,
1000         .dev            = {
1001                                 .dma_mask               = &dbgu_dmamask,
1002                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1003                                 .platform_data          = &dbgu_data,
1004         },
1005         .resource       = dbgu_resources,
1006         .num_resources  = ARRAY_SIZE(dbgu_resources),
1007 };
1008
1009 static inline void configure_dbgu_pins(void)
1010 {
1011         at91_set_A_periph(AT91_PIN_PC30, 0);            /* DRXD */
1012         at91_set_A_periph(AT91_PIN_PC31, 1);            /* DTXD */
1013 }
1014
1015 static struct resource uart0_resources[] = {
1016         [0] = {
1017                 .start  = AT91CAP9_BASE_US0,
1018                 .end    = AT91CAP9_BASE_US0 + SZ_16K - 1,
1019                 .flags  = IORESOURCE_MEM,
1020         },
1021         [1] = {
1022                 .start  = AT91CAP9_ID_US0,
1023                 .end    = AT91CAP9_ID_US0,
1024                 .flags  = IORESOURCE_IRQ,
1025         },
1026 };
1027
1028 static struct atmel_uart_data uart0_data = {
1029         .use_dma_tx     = 1,
1030         .use_dma_rx     = 1,
1031 };
1032
1033 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1034
1035 static struct platform_device at91cap9_uart0_device = {
1036         .name           = "atmel_usart",
1037         .id             = 1,
1038         .dev            = {
1039                                 .dma_mask               = &uart0_dmamask,
1040                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1041                                 .platform_data          = &uart0_data,
1042         },
1043         .resource       = uart0_resources,
1044         .num_resources  = ARRAY_SIZE(uart0_resources),
1045 };
1046
1047 static inline void configure_usart0_pins(unsigned pins)
1048 {
1049         at91_set_A_periph(AT91_PIN_PA22, 1);            /* TXD0 */
1050         at91_set_A_periph(AT91_PIN_PA23, 0);            /* RXD0 */
1051
1052         if (pins & ATMEL_UART_RTS)
1053                 at91_set_A_periph(AT91_PIN_PA24, 0);    /* RTS0 */
1054         if (pins & ATMEL_UART_CTS)
1055                 at91_set_A_periph(AT91_PIN_PA25, 0);    /* CTS0 */
1056 }
1057
1058 static struct resource uart1_resources[] = {
1059         [0] = {
1060                 .start  = AT91CAP9_BASE_US1,
1061                 .end    = AT91CAP9_BASE_US1 + SZ_16K - 1,
1062                 .flags  = IORESOURCE_MEM,
1063         },
1064         [1] = {
1065                 .start  = AT91CAP9_ID_US1,
1066                 .end    = AT91CAP9_ID_US1,
1067                 .flags  = IORESOURCE_IRQ,
1068         },
1069 };
1070
1071 static struct atmel_uart_data uart1_data = {
1072         .use_dma_tx     = 1,
1073         .use_dma_rx     = 1,
1074 };
1075
1076 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1077
1078 static struct platform_device at91cap9_uart1_device = {
1079         .name           = "atmel_usart",
1080         .id             = 2,
1081         .dev            = {
1082                                 .dma_mask               = &uart1_dmamask,
1083                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1084                                 .platform_data          = &uart1_data,
1085         },
1086         .resource       = uart1_resources,
1087         .num_resources  = ARRAY_SIZE(uart1_resources),
1088 };
1089
1090 static inline void configure_usart1_pins(unsigned pins)
1091 {
1092         at91_set_A_periph(AT91_PIN_PD0, 1);             /* TXD1 */
1093         at91_set_A_periph(AT91_PIN_PD1, 0);             /* RXD1 */
1094
1095         if (pins & ATMEL_UART_RTS)
1096                 at91_set_B_periph(AT91_PIN_PD7, 0);     /* RTS1 */
1097         if (pins & ATMEL_UART_CTS)
1098                 at91_set_B_periph(AT91_PIN_PD8, 0);     /* CTS1 */
1099 }
1100
1101 static struct resource uart2_resources[] = {
1102         [0] = {
1103                 .start  = AT91CAP9_BASE_US2,
1104                 .end    = AT91CAP9_BASE_US2 + SZ_16K - 1,
1105                 .flags  = IORESOURCE_MEM,
1106         },
1107         [1] = {
1108                 .start  = AT91CAP9_ID_US2,
1109                 .end    = AT91CAP9_ID_US2,
1110                 .flags  = IORESOURCE_IRQ,
1111         },
1112 };
1113
1114 static struct atmel_uart_data uart2_data = {
1115         .use_dma_tx     = 1,
1116         .use_dma_rx     = 1,
1117 };
1118
1119 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1120
1121 static struct platform_device at91cap9_uart2_device = {
1122         .name           = "atmel_usart",
1123         .id             = 3,
1124         .dev            = {
1125                                 .dma_mask               = &uart2_dmamask,
1126                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1127                                 .platform_data          = &uart2_data,
1128         },
1129         .resource       = uart2_resources,
1130         .num_resources  = ARRAY_SIZE(uart2_resources),
1131 };
1132
1133 static inline void configure_usart2_pins(unsigned pins)
1134 {
1135         at91_set_A_periph(AT91_PIN_PD2, 1);             /* TXD2 */
1136         at91_set_A_periph(AT91_PIN_PD3, 0);             /* RXD2 */
1137
1138         if (pins & ATMEL_UART_RTS)
1139                 at91_set_B_periph(AT91_PIN_PD5, 0);     /* RTS2 */
1140         if (pins & ATMEL_UART_CTS)
1141                 at91_set_B_periph(AT91_PIN_PD6, 0);     /* CTS2 */
1142 }
1143
1144 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
1145 struct platform_device *atmel_default_console_device;   /* the serial console device */
1146
1147 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1148 {
1149         struct platform_device *pdev;
1150
1151         switch (id) {
1152                 case 0:         /* DBGU */
1153                         pdev = &at91cap9_dbgu_device;
1154                         configure_dbgu_pins();
1155                         at91_clock_associate("mck", &pdev->dev, "usart");
1156                         break;
1157                 case AT91CAP9_ID_US0:
1158                         pdev = &at91cap9_uart0_device;
1159                         configure_usart0_pins(pins);
1160                         at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1161                         break;
1162                 case AT91CAP9_ID_US1:
1163                         pdev = &at91cap9_uart1_device;
1164                         configure_usart1_pins(pins);
1165                         at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1166                         break;
1167                 case AT91CAP9_ID_US2:
1168                         pdev = &at91cap9_uart2_device;
1169                         configure_usart2_pins(pins);
1170                         at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1171                         break;
1172                 default:
1173                         return;
1174         }
1175         pdev->id = portnr;              /* update to mapped ID */
1176
1177         if (portnr < ATMEL_MAX_UART)
1178                 at91_uarts[portnr] = pdev;
1179 }
1180
1181 void __init at91_set_serial_console(unsigned portnr)
1182 {
1183         if (portnr < ATMEL_MAX_UART)
1184                 atmel_default_console_device = at91_uarts[portnr];
1185 }
1186
1187 void __init at91_add_device_serial(void)
1188 {
1189         int i;
1190
1191         for (i = 0; i < ATMEL_MAX_UART; i++) {
1192                 if (at91_uarts[i])
1193                         platform_device_register(at91_uarts[i]);
1194         }
1195
1196         if (!atmel_default_console_device)
1197                 printk(KERN_INFO "AT91: No default serial console defined.\n");
1198 }
1199 #else
1200 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1201 void __init at91_set_serial_console(unsigned portnr) {}
1202 void __init at91_add_device_serial(void) {}
1203 #endif
1204
1205
1206 /* -------------------------------------------------------------------- */
1207 /*
1208  * These devices are always present and don't need any board-specific
1209  * setup.
1210  */
1211 static int __init at91_add_standard_devices(void)
1212 {
1213         at91_add_device_rtt();
1214         at91_add_device_watchdog();
1215         at91_add_device_tc();
1216         return 0;
1217 }
1218
1219 arch_initcall(at91_add_standard_devices);